| fc3300a5 | 13-Jul-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
docs: add mt6795 to deprecated list
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2b3aa9bd0c23c360ecee673c68e1b2c92bc6d2be |
| 8d15e46c | 12-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: update supported FVP models as per release 11.15.14
Change-Id: I65da6ead356e3f4ee47c5a6bf391f65309bafcdd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> |
| 2baf5038 | 07-Jul-2021 |
Pali Rohár <pali@kernel.org> |
fix(plat/marvell/a3k): Fix check for external dependences
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Ext
fix(plat/marvell/a3k): Fix check for external dependences
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Extranet anymore. Public version on github repository contains all
patches and is working fine, so for public TF-A builds use only public
external dependencies from git.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
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|
| 528dafc3 | 28-Jun-2021 |
Pali Rohár <pali@kernel.org> |
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded a
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded at some
specific location and require user to specify correct path to mv_ddr
source code via MV_DDR_PATH build option.
TF-A code for Armada 37x0 platform also depends on mv_ddr source code
and already requires passing correct MV_DDR_PATH build option.
So for A8K implement same checks for validity of MV_DDR_PATH option as
are already used by TF-A code for Armada 37x0 platform.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
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|
| 7285fd5f | 10-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The un
feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The underlying changes for enabling PIE in aarch32 is submitted in
commit 4324a14bf
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469
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|
| ed0f0a09 | 15-Jun-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "docs: change Linaro release version to 20.01" into integration |
| e3c07d2f | 07-Jun-2021 |
Jacky Bai <ping.bai@nxp.com> |
docs(imx8m): update build support for imx8mq
Due to the small OCRAM space used for TF-A, we will
meet imx8mq build failure caused by too small RAM size.
We CANNOT support it in TF-A CI. It does NOT
docs(imx8m): update build support for imx8mq
Due to the small OCRAM space used for TF-A, we will
meet imx8mq build failure caused by too small RAM size.
We CANNOT support it in TF-A CI. It does NOT mean that
imx8mq will be dropped by NXP. NXP will still actively
maintain it in NXP official release.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Iad726ffbc4eedc5f6770612bb9750986b9324ae9
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|
| 99a99eb4 | 01-Jun-2021 |
Zelalem <zelalem.aweke@arm.com> |
docs: change Linaro release version to 20.01
We currently use Linaro release software stack version
20.01 in the CI. Reflect that change in the docs.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm
docs: change Linaro release version to 20.01
We currently use Linaro release software stack version
20.01 in the CI. Reflect that change in the docs.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I0fa9f0163afb0bf399ec503abe9af4f17231f173
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|
| b35f8f2d | 31-May-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(tc0): add support for trusted services" into integration |
| 92473b3b | 13-May-2021 |
Zelalem <zelalem.aweke@arm.com> |
docs(juno): update TF-A build instructions
Clean up instructions for building/running TF-A on the
Juno platform and add correct link to SCP binaries.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm
docs(juno): update TF-A build instructions
Clean up instructions for building/running TF-A on the
Juno platform and add correct link to SCP binaries.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I536f98082e167edbf45f29ca23cc0db44687bb3b
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|
| ca932481 | 10-Mar-2021 |
Davidson K <davidson.kumaresan@arm.com> |
feat(tc0): add support for trusted services
This patch adds support for the crypto and secure storage secure
partitions for the Total Compute platform. These secure partitions
have to be managed by
feat(tc0): add support for trusted services
This patch adds support for the crypto and secure storage secure
partitions for the Total Compute platform. These secure partitions
have to be managed by Hafnium executing at S-EL2
Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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|
| 9cfb878f | 04-May-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs: revert FVP versions for select models
Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4
and Neoverse-N2x4.
Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1
Signed-off-b
docs: revert FVP versions for select models
Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4
and Neoverse-N2x4.
Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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|
| 08532d75 | 30-Apr-2021 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "docs: update list of supported FVP platforms" into integration |
| 6f09bcce | 27-Apr-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs: update list of supported FVP platforms
Updated the list of supported FVP platforms as per the latest FVP
release.
Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e
Signed-off-by: Lauren We
docs: update list of supported FVP platforms
Updated the list of supported FVP platforms as per the latest FVP
release.
Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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|
| e3be1086 | 10-Mar-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: add build options for GPT support enablement
Documented the build options used in Arm GPT parser enablement.
Change-Id: I9d7ef2f44b8f9d2731dd17c2639e5ed0eb6d0b3a
Signed-off-by: Manish V Badar
docs: add build options for GPT support enablement
Documented the build options used in Arm GPT parser enablement.
Change-Id: I9d7ef2f44b8f9d2731dd17c2639e5ed0eb6d0b3a
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| f2800a47 | 06-Apr-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC
This new compile option is only for Armada 3720 Development Board. When
it is set to 1 then TF-A will setup PM wake up src c
plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC
This new compile option is only for Armada 3720 Development Board. When
it is set to 1 then TF-A will setup PM wake up src configuration.
By default this new option is disabled as it is board specific and no
other A37xx board has PM wake up src configuration.
Currently neither upstream U-Boot nor upstream Linux kernel has wakeup
support for A37xx platforms, so having it disabled does not cause any
issue.
Prior this commit PM wake up src configuration specific for Armada 3720
Development Board was enabled for every A37xx board. After this change it
is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
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|
| cfe1506e | 20-Mar-2021 |
Aditya Angadi <aditya.angadi@arm.com> |
feat(plat/sgi): introduce platform variant build option
A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reu
feat(plat/sgi): introduce platform variant build option
A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reuse
of platform code across all the variants of a platform, introduce build
option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design
platforms. The range of allowed values for the build option is platform
specific. The recommended range is an interval of non negative integers.
An example usage of the build option is
make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1
Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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|
| 303f543e | 26-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "sgm775_deprecation" into integration
* changes:
build: deprecate Arm sgm775 FVP platform
docs: introduce process for platform deprecation |
| a92b0256 | 26-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I20c73f6e,I9962263c,I177796e3,I6ff6875c,I21fe9d85, ... into integration
* changes:
mediatek: mt8195: add rtc power off sequence
mediatek: mt8195: add power-off support
mediatek:
Merge changes I20c73f6e,I9962263c,I177796e3,I6ff6875c,I21fe9d85, ... into integration
* changes:
mediatek: mt8195: add rtc power off sequence
mediatek: mt8195: add power-off support
mediatek: mt8195: Add reboot function for PSCI
mediatek: mt8195: Add gpio driver
mediatek: mt8195: Add SiP service
mediatek: mt8195: Add CPU hotplug and MCDI support
mediatek: mt8195: Add MCDI drivers
mediatek: mt8195: Add SPMC driver
mediatek: mt8195: Initialize delay_timer
mediatek: mt8195: initialize systimer
mediatek: mt8192: move timer driver to common folder
mediatek: mt8195: add sys_cirq support
mediatek: mt8195: initialize GIC
Initialize platform for MediaTek MT8195
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|
| 37ee58d1 | 22-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
build: deprecate Arm sgm775 FVP platform
sgm775 is an old platform and is no longer maintained by Arm and its
fast model FVP_CSS_SGM-775 is no longer available for download.
This platform is now sup
build: deprecate Arm sgm775 FVP platform
sgm775 is an old platform and is no longer maintained by Arm and its
fast model FVP_CSS_SGM-775 is no longer available for download.
This platform is now superseded by Total Compute(tc) platforms.
This platform is now deprecated but the source will be kept for cooling
off period of 2 release cycle before removing it completely.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I8fe1fc3da0c508dba62ed4fc60cbc1642e0f7f2a
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|
| 67e3a890 | 22-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
docs: introduce process for platform deprecation
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifb8a3220f2fc2286fa91614887d17f54178ed002 |
| 174a1cfe | 19-Mar-2021 |
Yidi Lin <yidi.lin@mediatek.com> |
Initialize platform for MediaTek MT8195
- Add basic platform setup
- Add MT8195 documentation at docs/plat/
- Add generic CPU helper functions
- Add basic register address
Change-Id: I7978e2f32e589
Initialize platform for MediaTek MT8195
- Add basic platform setup
- Add MT8195 documentation at docs/plat/
- Add generic CPU helper functions
- Add basic register address
Change-Id: I7978e2f32e58900e5cf93f741ee8eaf8b8e3b842
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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|
| a05b3ad0 | 22-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "my-topic-name" into integration
* changes:
plat: imx8mm: Add in BL2 with FIP
plat: imx8mm: Enable Trusted Boot |
| 76a21174 | 12-Feb-2021 |
Mikael Olsson <mikael.olsson@arm.com> |
Add SiP service to configure Arm Ethos-N NPU
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still
Add SiP service to configure Arm Ethos-N NPU
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still allow the non-secure world to use the NPU, a SiP service has
been added that can delegate non-secure access to the registers needed
to use it.
Only the HW_CONFIG for the Arm Juno platform has been updated to include
the device tree for the NPU and the platform currently only loads the
HW_CONFIG in AArch64 builds.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
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|
| a9e14e20 | 20-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs: marvell: Add information about CZ.NIC Armada 3720 Secure Firmware" into integration |