1/* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <context.h> 13#include <lib/xlat_tables/xlat_tables_defs.h> 14 15 /* 16 * Helper macro to initialise EL3 registers we care about. 17 */ 18 .macro el3_arch_init_common 19 /* --------------------------------------------------------------------- 20 * SCTLR_EL3 has already been initialised - read current value before 21 * modifying. 22 * 23 * SCTLR_EL3.I: Enable the instruction cache. 24 * 25 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 26 * exception is generated if a load or store instruction executed at 27 * EL3 uses the SP as the base address and the SP is not aligned to a 28 * 16-byte boundary. 29 * 30 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 31 * load or store one or more registers have an alignment check that the 32 * address being accessed is aligned to the size of the data element(s) 33 * being accessed. 34 * --------------------------------------------------------------------- 35 */ 36 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 37 mrs x0, sctlr_el3 38 orr x0, x0, x1 39 msr sctlr_el3, x0 40 isb 41 42#ifdef IMAGE_BL31 43 /* --------------------------------------------------------------------- 44 * Initialise the per-cpu cache pointer to the CPU. 45 * This is done early to enable crash reporting to have access to crash 46 * stack. Since crash reporting depends on cpu_data to report the 47 * unhandled exception, not doing so can lead to recursive exceptions 48 * due to a NULL TPIDR_EL3. 49 * --------------------------------------------------------------------- 50 */ 51 bl init_cpu_data_ptr 52#endif /* IMAGE_BL31 */ 53 54 /* --------------------------------------------------------------------- 55 * Initialise SCR_EL3, setting all fields rather than relying on hw. 56 * All fields are architecturally UNKNOWN on reset. The following fields 57 * do not change during the TF lifetime. The remaining fields are set to 58 * zero here but are updated ahead of transitioning to a lower EL in the 59 * function cm_init_context_common(). 60 * 61 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 62 * EL2, EL1 and EL0 are not trapped to EL3. 63 * 64 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 65 * EL2, EL1 and EL0 are not trapped to EL3. 66 * 67 * SCR_EL3.SIF: Set to one to disable instruction fetches from 68 * Non-secure memory. 69 * 70 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 71 * both Security states and both Execution states. 72 * 73 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 74 * to EL3 when executing at any EL. 75 * 76 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, 77 * disable traps to EL3 when accessing key registers or using pointer 78 * authentication instructions from lower ELs. 79 * --------------------------------------------------------------------- 80 */ 81 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ 82 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) 83#if CTX_INCLUDE_PAUTH_REGS 84 /* 85 * If the pointer authentication registers are saved during world 86 * switches, enable pointer authentication everywhere, as it is safe to 87 * do so. 88 */ 89 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 90#endif 91 msr scr_el3, x0 92 93 /* --------------------------------------------------------------------- 94 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 95 * Some fields are architecturally UNKNOWN on reset. 96 * 97 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 98 * Debug exceptions, other than Breakpoint Instruction exceptions, are 99 * disabled from all ELs in Secure state. 100 * 101 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 102 * privileged debug from S-EL1. 103 * 104 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 105 * access to the powerdown debug registers do not trap to EL3. 106 * 107 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 108 * debug registers, other than those registers that are controlled by 109 * MDCR_EL3.TDOSA. 110 * 111 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 112 * accesses to all Performance Monitors registers do not trap to EL3. 113 * 114 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 115 * prohibited in Secure state. This bit is RES0 in versions of the 116 * architecture with FEAT_PMUv3p5 not implemented, setting it to 1 117 * doesn't have any effect on them. 118 * 119 * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 120 * prohibited in EL3. This bit is RES0 in versions of the 121 * architecture with FEAT_PMUv3p7 not implemented, setting it to 1 122 * doesn't have any effect on them. 123 * 124 * MDCR_EL3.SPME: Set to zero so that event counting by the programmable 125 * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 126 * Debug is not implemented this bit does not have any effect on the 127 * counters unless there is support for the implementation defined 128 * authentication interface ExternalSecureNoninvasiveDebugEnabled(). 129 * --------------------------------------------------------------------- 130 */ 131 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 132 MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \ 133 MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \ 134 MDCR_TDA_BIT | MDCR_TPM_BIT)) 135 136 msr mdcr_el3, x0 137 138 /* --------------------------------------------------------------------- 139 * Initialise PMCR_EL0 setting all fields rather than relying 140 * on hw. Some fields are architecturally UNKNOWN on reset. 141 * 142 * PMCR_EL0.LP: Set to one so that event counter overflow, that 143 * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment 144 * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU 145 * is implemented. This bit is RES0 in versions of the architecture 146 * earlier than ARMv8.5, setting it to 1 doesn't have any effect 147 * on them. 148 * 149 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 150 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 151 * that changes PMCCNTR_EL0[63] from 1 to 0. 152 * 153 * PMCR_EL0.DP: Set to one so that the cycle counter, 154 * PMCCNTR_EL0 does not count when event counting is prohibited. 155 * 156 * PMCR_EL0.X: Set to zero to disable export of events. 157 * 158 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 159 * counts on every clock cycle. 160 * --------------------------------------------------------------------- 161 */ 162 mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ 163 PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ 164 ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) 165 166 msr pmcr_el0, x0 167 168 /* --------------------------------------------------------------------- 169 * Enable External Aborts and SError Interrupts now that the exception 170 * vectors have been setup. 171 * --------------------------------------------------------------------- 172 */ 173 msr daifclr, #DAIF_ABT_BIT 174 175 /* --------------------------------------------------------------------- 176 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 177 * All fields are architecturally UNKNOWN on reset. 178 * 179 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, 180 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. 181 * 182 * CPTR_EL3.TTA: Set to zero so that System register accesses to the 183 * trace registers do not trap to EL3. 184 * 185 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 186 * by Advanced SIMD, floating-point or SVE instructions (if implemented) 187 * do not trap to EL3. 188 */ 189 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) 190 msr cptr_el3, x0 191 192 /* 193 * If Data Independent Timing (DIT) functionality is implemented, 194 * always enable DIT in EL3 195 */ 196 mrs x0, id_aa64pfr0_el1 197 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 198 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 199 bne 1f 200 mov x0, #DIT_BIT 201 msr DIT, x0 2021: 203 .endm 204 205/* ----------------------------------------------------------------------------- 206 * This is the super set of actions that need to be performed during a cold boot 207 * or a warm boot in EL3. This code is shared by BL1 and BL31. 208 * 209 * This macro will always perform reset handling, architectural initialisations 210 * and stack setup. The rest of the actions are optional because they might not 211 * be needed, depending on the context in which this macro is called. This is 212 * why this macro is parameterised ; each parameter allows to enable/disable 213 * some actions. 214 * 215 * _init_sctlr: 216 * Whether the macro needs to initialise SCTLR_EL3, including configuring 217 * the endianness of data accesses. 218 * 219 * _warm_boot_mailbox: 220 * Whether the macro needs to detect the type of boot (cold/warm). The 221 * detection is based on the platform entrypoint address : if it is zero 222 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 223 * this macro jumps on the platform entrypoint address. 224 * 225 * _secondary_cold_boot: 226 * Whether the macro needs to identify the CPU that is calling it: primary 227 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 228 * the platform initialisations, while the secondaries will be put in a 229 * platform-specific state in the meantime. 230 * 231 * If the caller knows this macro will only be called by the primary CPU 232 * then this parameter can be defined to 0 to skip this step. 233 * 234 * _init_memory: 235 * Whether the macro needs to initialise the memory. 236 * 237 * _init_c_runtime: 238 * Whether the macro needs to initialise the C runtime environment. 239 * 240 * _exception_vectors: 241 * Address of the exception vectors to program in the VBAR_EL3 register. 242 * 243 * _pie_fixup_size: 244 * Size of memory region to fixup Global Descriptor Table (GDT). 245 * 246 * A non-zero value is expected when firmware needs GDT to be fixed-up. 247 * 248 * ----------------------------------------------------------------------------- 249 */ 250 .macro el3_entrypoint_common \ 251 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 252 _init_memory, _init_c_runtime, _exception_vectors, \ 253 _pie_fixup_size 254 255 .if \_init_sctlr 256 /* ------------------------------------------------------------- 257 * This is the initialisation of SCTLR_EL3 and so must ensure 258 * that all fields are explicitly set rather than relying on hw. 259 * Some fields reset to an IMPLEMENTATION DEFINED value and 260 * others are architecturally UNKNOWN on reset. 261 * 262 * SCTLR.EE: Set the CPU endianness before doing anything that 263 * might involve memory reads or writes. Set to zero to select 264 * Little Endian. 265 * 266 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 267 * force all memory regions that are writeable to be treated as 268 * XN (Execute-never). Set to zero so that this control has no 269 * effect on memory access permissions. 270 * 271 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 272 * 273 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 274 * 275 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 276 * safe behaviour upon exception entry to EL3. 277 * ------------------------------------------------------------- 278 */ 279 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 280 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 281 msr sctlr_el3, x0 282 isb 283 .endif /* _init_sctlr */ 284 285#if DISABLE_MTPMU 286 bl mtpmu_disable 287#endif 288 289 .if \_warm_boot_mailbox 290 /* ------------------------------------------------------------- 291 * This code will be executed for both warm and cold resets. 292 * Now is the time to distinguish between the two. 293 * Query the platform entrypoint address and if it is not zero 294 * then it means it is a warm boot so jump to this address. 295 * ------------------------------------------------------------- 296 */ 297 bl plat_get_my_entrypoint 298 cbz x0, do_cold_boot 299 br x0 300 301 do_cold_boot: 302 .endif /* _warm_boot_mailbox */ 303 304 .if \_pie_fixup_size 305#if ENABLE_PIE 306 /* 307 * ------------------------------------------------------------ 308 * If PIE is enabled fixup the Global descriptor Table only 309 * once during primary core cold boot path. 310 * 311 * Compile time base address, required for fixup, is calculated 312 * using "pie_fixup" label present within first page. 313 * ------------------------------------------------------------ 314 */ 315 pie_fixup: 316 ldr x0, =pie_fixup 317 and x0, x0, #~(PAGE_SIZE_MASK) 318 mov_imm x1, \_pie_fixup_size 319 add x1, x1, x0 320 bl fixup_gdt_reloc 321#endif /* ENABLE_PIE */ 322 .endif /* _pie_fixup_size */ 323 324 /* --------------------------------------------------------------------- 325 * Set the exception vectors. 326 * --------------------------------------------------------------------- 327 */ 328 adr x0, \_exception_vectors 329 msr vbar_el3, x0 330 isb 331 332 /* --------------------------------------------------------------------- 333 * It is a cold boot. 334 * Perform any processor specific actions upon reset e.g. cache, TLB 335 * invalidations etc. 336 * --------------------------------------------------------------------- 337 */ 338 bl reset_handler 339 340 el3_arch_init_common 341 342 .if \_secondary_cold_boot 343 /* ------------------------------------------------------------- 344 * Check if this is a primary or secondary CPU cold boot. 345 * The primary CPU will set up the platform while the 346 * secondaries are placed in a platform-specific state until the 347 * primary CPU performs the necessary actions to bring them out 348 * of that state and allows entry into the OS. 349 * ------------------------------------------------------------- 350 */ 351 bl plat_is_my_cpu_primary 352 cbnz w0, do_primary_cold_boot 353 354 /* This is a cold boot on a secondary CPU */ 355 bl plat_secondary_cold_boot_setup 356 /* plat_secondary_cold_boot_setup() is not supposed to return */ 357 bl el3_panic 358 359 do_primary_cold_boot: 360 .endif /* _secondary_cold_boot */ 361 362 /* --------------------------------------------------------------------- 363 * Initialize memory now. Secondary CPU initialization won't get to this 364 * point. 365 * --------------------------------------------------------------------- 366 */ 367 368 .if \_init_memory 369 bl platform_mem_init 370 .endif /* _init_memory */ 371 372 /* --------------------------------------------------------------------- 373 * Init C runtime environment: 374 * - Zero-initialise the NOBITS sections. There are 2 of them: 375 * - the .bss section; 376 * - the coherent memory section (if any). 377 * - Relocate the data section from ROM to RAM, if required. 378 * --------------------------------------------------------------------- 379 */ 380 .if \_init_c_runtime 381#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE) 382 /* ------------------------------------------------------------- 383 * Invalidate the RW memory used by the BL31 image. This 384 * includes the data and NOBITS sections. This is done to 385 * safeguard against possible corruption of this memory by 386 * dirty cache lines in a system cache as a result of use by 387 * an earlier boot loader stage. 388 * ------------------------------------------------------------- 389 */ 390 adrp x0, __RW_START__ 391 add x0, x0, :lo12:__RW_START__ 392 adrp x1, __RW_END__ 393 add x1, x1, :lo12:__RW_END__ 394 sub x1, x1, x0 395 bl inv_dcache_range 396#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 397 adrp x0, __NOBITS_START__ 398 add x0, x0, :lo12:__NOBITS_START__ 399 adrp x1, __NOBITS_END__ 400 add x1, x1, :lo12:__NOBITS_END__ 401 sub x1, x1, x0 402 bl inv_dcache_range 403#endif 404#endif 405 adrp x0, __BSS_START__ 406 add x0, x0, :lo12:__BSS_START__ 407 408 adrp x1, __BSS_END__ 409 add x1, x1, :lo12:__BSS_END__ 410 sub x1, x1, x0 411 bl zeromem 412 413#if USE_COHERENT_MEM 414 adrp x0, __COHERENT_RAM_START__ 415 add x0, x0, :lo12:__COHERENT_RAM_START__ 416 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 417 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 418 sub x1, x1, x0 419 bl zeromem 420#endif 421 422#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) 423 adrp x0, __DATA_RAM_START__ 424 add x0, x0, :lo12:__DATA_RAM_START__ 425 adrp x1, __DATA_ROM_START__ 426 add x1, x1, :lo12:__DATA_ROM_START__ 427 adrp x2, __DATA_RAM_END__ 428 add x2, x2, :lo12:__DATA_RAM_END__ 429 sub x2, x2, x0 430 bl memcpy16 431#endif 432 .endif /* _init_c_runtime */ 433 434 /* --------------------------------------------------------------------- 435 * Use SP_EL0 for the C runtime stack. 436 * --------------------------------------------------------------------- 437 */ 438 msr spsel, #0 439 440 /* --------------------------------------------------------------------- 441 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 442 * the MMU is enabled. There is no risk of reading stale stack memory 443 * after enabling the MMU as only the primary CPU is running at the 444 * moment. 445 * --------------------------------------------------------------------- 446 */ 447 bl plat_set_my_stack 448 449#if STACK_PROTECTOR_ENABLED 450 .if \_init_c_runtime 451 bl update_stack_protector_canary 452 .endif /* _init_c_runtime */ 453#endif 454 .endm 455 456 .macro apply_at_speculative_wa 457#if ERRATA_SPECULATIVE_AT 458 /* 459 * Explicitly save x30 so as to free up a register and to enable 460 * branching and also, save x29 which will be used in the called 461 * function 462 */ 463 stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 464 bl save_and_update_ptw_el1_sys_regs 465 ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 466#endif 467 .endm 468 469 .macro restore_ptw_el1_sys_regs 470#if ERRATA_SPECULATIVE_AT 471 /* ----------------------------------------------------------- 472 * In case of ERRATA_SPECULATIVE_AT, must follow below order 473 * to ensure that page table walk is not enabled until 474 * restoration of all EL1 system registers. TCR_EL1 register 475 * should be updated at the end which restores previous page 476 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 477 * ensures that CPU does below steps in order. 478 * 479 * 1. Ensure all other system registers are written before 480 * updating SCTLR_EL1 using ISB. 481 * 2. Restore SCTLR_EL1 register. 482 * 3. Ensure SCTLR_EL1 written successfully using ISB. 483 * 4. Restore TCR_EL1 register. 484 * ----------------------------------------------------------- 485 */ 486 isb 487 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] 488 msr sctlr_el1, x28 489 isb 490 msr tcr_el1, x29 491#endif 492 .endm 493 494#endif /* EL3_COMMON_MACROS_S */ 495