1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/io/io_block.h> 15 #include <drivers/io/io_driver.h> 16 #include <drivers/io/io_dummy.h> 17 #include <drivers/io/io_mtd.h> 18 #include <drivers/io/io_storage.h> 19 #include <drivers/mmc.h> 20 #include <drivers/partition/partition.h> 21 #include <drivers/raw_nand.h> 22 #include <drivers/spi_nand.h> 23 #include <drivers/spi_nor.h> 24 #include <drivers/st/io_mmc.h> 25 #include <drivers/st/io_stm32image.h> 26 #include <drivers/st/stm32_fmc2_nand.h> 27 #include <drivers/st/stm32_qspi.h> 28 #include <drivers/st/stm32_sdmmc2.h> 29 #include <lib/mmio.h> 30 #include <lib/utils.h> 31 #include <plat/common/platform.h> 32 33 /* IO devices */ 34 #ifndef AARCH32_SP_OPTEE 35 static const io_dev_connector_t *dummy_dev_con; 36 static uintptr_t dummy_dev_handle; 37 static uintptr_t dummy_dev_spec; 38 #endif 39 40 static uintptr_t image_dev_handle; 41 static uintptr_t storage_dev_handle; 42 43 #if STM32MP_SDMMC || STM32MP_EMMC 44 static struct mmc_device_info mmc_info; 45 static io_block_spec_t gpt_block_spec = { 46 .offset = 0, 47 .length = 34 * MMC_BLOCK_SIZE, /* Size of GPT table */ 48 }; 49 50 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 51 52 static const io_block_dev_spec_t mmc_block_dev_spec = { 53 /* It's used as temp buffer in block driver */ 54 .buffer = { 55 .offset = (size_t)&block_buffer, 56 .length = MMC_BLOCK_SIZE, 57 }, 58 .ops = { 59 .read = mmc_read_blocks, 60 .write = NULL, 61 }, 62 .block_size = MMC_BLOCK_SIZE, 63 }; 64 65 static const io_dev_connector_t *mmc_dev_con; 66 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 67 68 #if STM32MP_SPI_NOR 69 static io_mtd_dev_spec_t spi_nor_dev_spec = { 70 .ops = { 71 .init = spi_nor_init, 72 .read = spi_nor_read, 73 }, 74 }; 75 #endif 76 77 #if STM32MP_RAW_NAND 78 static io_mtd_dev_spec_t nand_dev_spec = { 79 .ops = { 80 .init = nand_raw_init, 81 .read = nand_read, 82 }, 83 }; 84 85 static const io_dev_connector_t *nand_dev_con; 86 #endif 87 88 #if STM32MP_SPI_NAND 89 static io_mtd_dev_spec_t spi_nand_dev_spec = { 90 .ops = { 91 .init = spi_nand_init, 92 .read = nand_read, 93 }, 94 }; 95 #endif 96 97 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 98 static const io_dev_connector_t *spi_dev_con; 99 #endif 100 101 #ifdef AARCH32_SP_OPTEE 102 static const struct stm32image_part_info optee_header_partition_spec = { 103 .name = OPTEE_HEADER_IMAGE_NAME, 104 .binary_type = OPTEE_HEADER_BINARY_TYPE, 105 }; 106 107 static const struct stm32image_part_info optee_core_partition_spec = { 108 .name = OPTEE_CORE_IMAGE_NAME, 109 .binary_type = OPTEE_CORE_BINARY_TYPE, 110 }; 111 112 static const struct stm32image_part_info optee_paged_partition_spec = { 113 .name = OPTEE_PAGED_IMAGE_NAME, 114 .binary_type = OPTEE_PAGED_BINARY_TYPE, 115 }; 116 #else 117 static const io_block_spec_t bl32_block_spec = { 118 .offset = BL32_BASE, 119 .length = STM32MP_BL32_SIZE 120 }; 121 #endif 122 123 static const struct stm32image_part_info bl33_partition_spec = { 124 .name = BL33_IMAGE_NAME, 125 .binary_type = BL33_BINARY_TYPE, 126 }; 127 128 enum { 129 IMG_IDX_BL33, 130 #ifdef AARCH32_SP_OPTEE 131 IMG_IDX_OPTEE_HEADER, 132 IMG_IDX_OPTEE_CORE, 133 IMG_IDX_OPTEE_PAGED, 134 #endif 135 IMG_IDX_NUM 136 }; 137 138 static struct stm32image_device_info stm32image_dev_info_spec __unused = { 139 .lba_size = MMC_BLOCK_SIZE, 140 .part_info[IMG_IDX_BL33] = { 141 .name = BL33_IMAGE_NAME, 142 .binary_type = BL33_BINARY_TYPE, 143 }, 144 #ifdef AARCH32_SP_OPTEE 145 .part_info[IMG_IDX_OPTEE_HEADER] = { 146 .name = OPTEE_HEADER_IMAGE_NAME, 147 .binary_type = OPTEE_HEADER_BINARY_TYPE, 148 }, 149 .part_info[IMG_IDX_OPTEE_CORE] = { 150 .name = OPTEE_CORE_IMAGE_NAME, 151 .binary_type = OPTEE_CORE_BINARY_TYPE, 152 }, 153 .part_info[IMG_IDX_OPTEE_PAGED] = { 154 .name = OPTEE_PAGED_IMAGE_NAME, 155 .binary_type = OPTEE_PAGED_BINARY_TYPE, 156 }, 157 #endif 158 }; 159 160 static io_block_spec_t stm32image_block_spec = { 161 .offset = 0, 162 .length = 0, 163 }; 164 165 static const io_dev_connector_t *stm32image_dev_con __unused; 166 167 #ifndef AARCH32_SP_OPTEE 168 static int open_dummy(const uintptr_t spec); 169 #endif 170 static int open_image(const uintptr_t spec); 171 static int open_storage(const uintptr_t spec); 172 173 struct plat_io_policy { 174 uintptr_t *dev_handle; 175 uintptr_t image_spec; 176 int (*check)(const uintptr_t spec); 177 }; 178 179 static const struct plat_io_policy policies[] = { 180 #ifdef AARCH32_SP_OPTEE 181 [BL32_IMAGE_ID] = { 182 .dev_handle = &image_dev_handle, 183 .image_spec = (uintptr_t)&optee_header_partition_spec, 184 .check = open_image 185 }, 186 [BL32_EXTRA1_IMAGE_ID] = { 187 .dev_handle = &image_dev_handle, 188 .image_spec = (uintptr_t)&optee_core_partition_spec, 189 .check = open_image 190 }, 191 [BL32_EXTRA2_IMAGE_ID] = { 192 .dev_handle = &image_dev_handle, 193 .image_spec = (uintptr_t)&optee_paged_partition_spec, 194 .check = open_image 195 }, 196 #else 197 [BL32_IMAGE_ID] = { 198 .dev_handle = &dummy_dev_handle, 199 .image_spec = (uintptr_t)&bl32_block_spec, 200 .check = open_dummy 201 }, 202 #endif 203 [BL33_IMAGE_ID] = { 204 .dev_handle = &image_dev_handle, 205 .image_spec = (uintptr_t)&bl33_partition_spec, 206 .check = open_image 207 }, 208 #if STM32MP_SDMMC || STM32MP_EMMC 209 [GPT_IMAGE_ID] = { 210 .dev_handle = &storage_dev_handle, 211 .image_spec = (uintptr_t)&gpt_block_spec, 212 .check = open_storage 213 }, 214 #endif 215 [STM32_IMAGE_ID] = { 216 .dev_handle = &storage_dev_handle, 217 .image_spec = (uintptr_t)&stm32image_block_spec, 218 .check = open_storage 219 } 220 }; 221 222 #ifndef AARCH32_SP_OPTEE 223 static int open_dummy(const uintptr_t spec) 224 { 225 return io_dev_init(dummy_dev_handle, 0); 226 } 227 #endif 228 229 static int open_image(const uintptr_t spec) 230 { 231 return io_dev_init(image_dev_handle, 0); 232 } 233 234 static int open_storage(const uintptr_t spec) 235 { 236 return io_dev_init(storage_dev_handle, 0); 237 } 238 239 static void print_boot_device(boot_api_context_t *boot_context) 240 { 241 switch (boot_context->boot_interface_selected) { 242 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 243 INFO("Using SDMMC\n"); 244 break; 245 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 246 INFO("Using EMMC\n"); 247 break; 248 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 249 INFO("Using QSPI NOR\n"); 250 break; 251 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 252 INFO("Using FMC NAND\n"); 253 break; 254 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 255 INFO("Using SPI NAND\n"); 256 break; 257 default: 258 ERROR("Boot interface not found\n"); 259 panic(); 260 break; 261 } 262 263 if (boot_context->boot_interface_instance != 0U) { 264 INFO(" Instance %d\n", boot_context->boot_interface_instance); 265 } 266 } 267 268 #if STM32MP_SDMMC || STM32MP_EMMC 269 static void boot_mmc(enum mmc_device_type mmc_dev_type, 270 uint16_t boot_interface_instance) 271 { 272 int io_result __unused; 273 uint8_t idx; 274 struct stm32image_part_info *part; 275 struct stm32_sdmmc2_params params; 276 const partition_entry_t *entry; 277 278 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 279 280 mmc_info.mmc_dev_type = mmc_dev_type; 281 282 switch (boot_interface_instance) { 283 case 1: 284 params.reg_base = STM32MP_SDMMC1_BASE; 285 break; 286 case 2: 287 params.reg_base = STM32MP_SDMMC2_BASE; 288 break; 289 case 3: 290 params.reg_base = STM32MP_SDMMC3_BASE; 291 break; 292 default: 293 WARN("SDMMC instance not found, using default\n"); 294 if (mmc_dev_type == MMC_IS_SD) { 295 params.reg_base = STM32MP_SDMMC1_BASE; 296 } else { 297 params.reg_base = STM32MP_SDMMC2_BASE; 298 } 299 break; 300 } 301 302 params.device_info = &mmc_info; 303 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 304 ERROR("SDMMC%u init failed\n", boot_interface_instance); 305 panic(); 306 } 307 308 /* Open MMC as a block device to read GPT table */ 309 io_result = register_io_dev_block(&mmc_dev_con); 310 if (io_result != 0) { 311 panic(); 312 } 313 314 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 315 &storage_dev_handle); 316 assert(io_result == 0); 317 318 partition_init(GPT_IMAGE_ID); 319 320 io_result = io_dev_close(storage_dev_handle); 321 assert(io_result == 0); 322 323 stm32image_dev_info_spec.device_size = 324 stm32_sdmmc2_mmc_get_device_size(); 325 326 for (idx = 0U; idx < IMG_IDX_NUM; idx++) { 327 part = &stm32image_dev_info_spec.part_info[idx]; 328 entry = get_partition_entry(part->name); 329 if (entry == NULL) { 330 ERROR("Partition %s not found\n", part->name); 331 panic(); 332 } 333 334 part->part_offset = entry->start; 335 part->bkp_offset = 0U; 336 } 337 338 /* 339 * Re-open MMC with io_mmc, for better perfs compared to 340 * io_block. 341 */ 342 io_result = register_io_dev_mmc(&mmc_dev_con); 343 assert(io_result == 0); 344 345 io_result = io_dev_open(mmc_dev_con, 0, &storage_dev_handle); 346 assert(io_result == 0); 347 348 io_result = register_io_dev_stm32image(&stm32image_dev_con); 349 assert(io_result == 0); 350 351 io_result = io_dev_open(stm32image_dev_con, 352 (uintptr_t)&stm32image_dev_info_spec, 353 &image_dev_handle); 354 assert(io_result == 0); 355 } 356 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 357 358 #if STM32MP_SPI_NOR 359 static void boot_spi_nor(boot_api_context_t *boot_context) 360 { 361 int io_result __unused; 362 uint8_t idx; 363 struct stm32image_part_info *part; 364 365 io_result = stm32_qspi_init(); 366 assert(io_result == 0); 367 368 io_result = register_io_dev_mtd(&spi_dev_con); 369 assert(io_result == 0); 370 371 /* Open connections to device */ 372 io_result = io_dev_open(spi_dev_con, 373 (uintptr_t)&spi_nor_dev_spec, 374 &storage_dev_handle); 375 assert(io_result == 0); 376 377 stm32image_dev_info_spec.device_size = spi_nor_dev_spec.device_size; 378 379 idx = IMG_IDX_BL33; 380 part = &stm32image_dev_info_spec.part_info[idx]; 381 part->part_offset = STM32MP_NOR_BL33_OFFSET; 382 part->bkp_offset = 0U; 383 384 #ifdef AARCH32_SP_OPTEE 385 idx = IMG_IDX_OPTEE_HEADER; 386 part = &stm32image_dev_info_spec.part_info[idx]; 387 part->part_offset = STM32MP_NOR_TEEH_OFFSET; 388 part->bkp_offset = 0U; 389 390 idx = IMG_IDX_OPTEE_PAGED; 391 part = &stm32image_dev_info_spec.part_info[idx]; 392 part->part_offset = STM32MP_NOR_TEED_OFFSET; 393 part->bkp_offset = 0U; 394 395 idx = IMG_IDX_OPTEE_CORE; 396 part = &stm32image_dev_info_spec.part_info[idx]; 397 part->part_offset = STM32MP_NOR_TEEX_OFFSET; 398 part->bkp_offset = 0U; 399 #endif 400 401 io_result = register_io_dev_stm32image(&stm32image_dev_con); 402 assert(io_result == 0); 403 404 io_result = io_dev_open(stm32image_dev_con, 405 (uintptr_t)&stm32image_dev_info_spec, 406 &image_dev_handle); 407 assert(io_result == 0); 408 } 409 #endif /* STM32MP_SPI_NOR */ 410 411 #if STM32MP_RAW_NAND 412 static void boot_fmc2_nand(boot_api_context_t *boot_context) 413 { 414 int io_result __unused; 415 uint8_t idx; 416 struct stm32image_part_info *part; 417 418 io_result = stm32_fmc2_init(); 419 assert(io_result == 0); 420 421 /* Register the IO device on this platform */ 422 io_result = register_io_dev_mtd(&nand_dev_con); 423 assert(io_result == 0); 424 425 /* Open connections to device */ 426 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 427 &storage_dev_handle); 428 assert(io_result == 0); 429 430 stm32image_dev_info_spec.device_size = nand_dev_spec.device_size; 431 432 idx = IMG_IDX_BL33; 433 part = &stm32image_dev_info_spec.part_info[idx]; 434 part->part_offset = STM32MP_NAND_BL33_OFFSET; 435 part->bkp_offset = nand_dev_spec.erase_size; 436 437 #ifdef AARCH32_SP_OPTEE 438 idx = IMG_IDX_OPTEE_HEADER; 439 part = &stm32image_dev_info_spec.part_info[idx]; 440 part->part_offset = STM32MP_NAND_TEEH_OFFSET; 441 part->bkp_offset = nand_dev_spec.erase_size; 442 443 idx = IMG_IDX_OPTEE_PAGED; 444 part = &stm32image_dev_info_spec.part_info[idx]; 445 part->part_offset = STM32MP_NAND_TEED_OFFSET; 446 part->bkp_offset = nand_dev_spec.erase_size; 447 448 idx = IMG_IDX_OPTEE_CORE; 449 part = &stm32image_dev_info_spec.part_info[idx]; 450 part->part_offset = STM32MP_NAND_TEEX_OFFSET; 451 part->bkp_offset = nand_dev_spec.erase_size; 452 #endif 453 454 io_result = register_io_dev_stm32image(&stm32image_dev_con); 455 assert(io_result == 0); 456 457 io_result = io_dev_open(stm32image_dev_con, 458 (uintptr_t)&stm32image_dev_info_spec, 459 &image_dev_handle); 460 assert(io_result == 0); 461 } 462 #endif /* STM32MP_RAW_NAND */ 463 464 #if STM32MP_SPI_NAND 465 static void boot_spi_nand(boot_api_context_t *boot_context) 466 { 467 int io_result __unused; 468 uint8_t idx; 469 struct stm32image_part_info *part; 470 471 io_result = stm32_qspi_init(); 472 assert(io_result == 0); 473 474 io_result = register_io_dev_mtd(&spi_dev_con); 475 assert(io_result == 0); 476 477 /* Open connections to device */ 478 io_result = io_dev_open(spi_dev_con, 479 (uintptr_t)&spi_nand_dev_spec, 480 &storage_dev_handle); 481 assert(io_result == 0); 482 483 stm32image_dev_info_spec.device_size = 484 spi_nand_dev_spec.device_size; 485 486 idx = IMG_IDX_BL33; 487 part = &stm32image_dev_info_spec.part_info[idx]; 488 part->part_offset = STM32MP_NAND_BL33_OFFSET; 489 part->bkp_offset = spi_nand_dev_spec.erase_size; 490 491 #ifdef AARCH32_SP_OPTEE 492 idx = IMG_IDX_OPTEE_HEADER; 493 part = &stm32image_dev_info_spec.part_info[idx]; 494 part->part_offset = STM32MP_NAND_TEEH_OFFSET; 495 part->bkp_offset = spi_nand_dev_spec.erase_size; 496 497 idx = IMG_IDX_OPTEE_PAGED; 498 part = &stm32image_dev_info_spec.part_info[idx]; 499 part->part_offset = STM32MP_NAND_TEED_OFFSET; 500 part->bkp_offset = spi_nand_dev_spec.erase_size; 501 502 idx = IMG_IDX_OPTEE_CORE; 503 part = &stm32image_dev_info_spec.part_info[idx]; 504 part->part_offset = STM32MP_NAND_TEEX_OFFSET; 505 part->bkp_offset = spi_nand_dev_spec.erase_size; 506 #endif 507 508 io_result = register_io_dev_stm32image(&stm32image_dev_con); 509 assert(io_result == 0); 510 511 io_result = io_dev_open(stm32image_dev_con, 512 (uintptr_t)&stm32image_dev_info_spec, 513 &image_dev_handle); 514 assert(io_result == 0); 515 } 516 #endif /* STM32MP_SPI_NAND */ 517 518 void stm32mp_io_setup(void) 519 { 520 int io_result __unused; 521 boot_api_context_t *boot_context = 522 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 523 524 print_boot_device(boot_context); 525 526 if ((boot_context->boot_partition_used_toboot == 1U) || 527 (boot_context->boot_partition_used_toboot == 2U)) { 528 INFO("Boot used partition fsbl%d\n", 529 boot_context->boot_partition_used_toboot); 530 } 531 532 #ifndef AARCH32_SP_OPTEE 533 io_result = register_io_dev_dummy(&dummy_dev_con); 534 assert(io_result == 0); 535 536 io_result = io_dev_open(dummy_dev_con, dummy_dev_spec, 537 &dummy_dev_handle); 538 assert(io_result == 0); 539 #endif 540 541 switch (boot_context->boot_interface_selected) { 542 #if STM32MP_SDMMC 543 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 544 dmbsy(); 545 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 546 break; 547 #endif 548 #if STM32MP_EMMC 549 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 550 dmbsy(); 551 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 552 break; 553 #endif 554 #if STM32MP_SPI_NOR 555 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 556 dmbsy(); 557 boot_spi_nor(boot_context); 558 break; 559 #endif 560 #if STM32MP_RAW_NAND 561 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 562 dmbsy(); 563 boot_fmc2_nand(boot_context); 564 break; 565 #endif 566 #if STM32MP_SPI_NAND 567 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 568 dmbsy(); 569 boot_spi_nand(boot_context); 570 break; 571 #endif 572 573 default: 574 ERROR("Boot interface %d not supported\n", 575 boot_context->boot_interface_selected); 576 break; 577 } 578 } 579 580 /* 581 * Return an IO device handle and specification which can be used to access 582 * an image. Use this to enforce platform load policy. 583 */ 584 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 585 uintptr_t *image_spec) 586 { 587 int rc; 588 const struct plat_io_policy *policy; 589 590 assert(image_id < ARRAY_SIZE(policies)); 591 592 policy = &policies[image_id]; 593 rc = policy->check(policy->image_spec); 594 if (rc == 0) { 595 *image_spec = policy->image_spec; 596 *dev_handle = *(policy->dev_handle); 597 } 598 599 return rc; 600 } 601