1/* 2 * Copyright (c) 2019-2020, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Neoverse V1 Errata #1791573. 26 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_neoverse_v1_1791573_wa 32 /* Check workaround compatibility. */ 33 mov x17, x30 34 bl check_errata_1791573 35 cbz x0, 1f 36 37 /* Set bit 2 in ACTLR2_EL1 */ 38 mrs x1, NEOVERSE_V1_ACTLR2_EL1 39 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 40 msr NEOVERSE_V1_ACTLR2_EL1, x1 41 isb 421: 43 ret x17 44endfunc errata_neoverse_v1_1791573_wa 45 46func check_errata_1791573 47 /* Applies to r0p0 and r1p0. */ 48 mov x1, #0x10 49 b cpu_rev_var_ls 50endfunc check_errata_1791573 51 52 /* --------------------------------------------- 53 * HW will do the cache maintenance while powering down 54 * --------------------------------------------- 55 */ 56func neoverse_v1_core_pwr_dwn 57 /* --------------------------------------------- 58 * Enable CPU power down bit in power control register 59 * --------------------------------------------- 60 */ 61 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 62 orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 63 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 64 isb 65 ret 66endfunc neoverse_v1_core_pwr_dwn 67 68 /* 69 * Errata printing function for Neoverse V1. Must follow AAPCS. 70 */ 71#if REPORT_ERRATA 72func neoverse_v1_errata_report 73 stp x8, x30, [sp, #-16]! 74 75 bl cpu_get_rev_var 76 mov x8, x0 77 78 /* 79 * Report all errata. The revision-variant information is passed to 80 * checking functions of each errata. 81 */ 82 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 83 84 ldp x8, x30, [sp], #16 85 ret 86endfunc neoverse_v1_errata_report 87#endif 88 89func neoverse_v1_reset_func 90 mov x19, x30 91 92 /* Disable speculative loads */ 93 msr SSBS, xzr 94 isb 95 96#if ERRATA_V1_1791573 97 mov x0, x18 98 bl errata_neoverse_v1_1791573_wa 99#endif 100 101 ret x19 102endfunc neoverse_v1_reset_func 103 104 /* --------------------------------------------- 105 * This function provides Neoverse-V1 specific 106 * register information for crash reporting. 107 * It needs to return with x6 pointing to 108 * a list of register names in ascii and 109 * x8 - x15 having values of registers to be 110 * reported. 111 * --------------------------------------------- 112 */ 113.section .rodata.neoverse_v1_regs, "aS" 114neoverse_v1_regs: /* The ascii list of register names to be reported */ 115 .asciz "cpuectlr_el1", "" 116 117func neoverse_v1_cpu_reg_dump 118 adr x6, neoverse_v1_regs 119 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 120 ret 121endfunc neoverse_v1_cpu_reg_dump 122 123declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 124 neoverse_v1_reset_func, \ 125 neoverse_v1_core_pwr_dwn 126