feat(arm): move GPT setup to common BL source

As of now, GPT setup is being handled from BL2 for plat/arm platforms.
However, for platforms having a separate entity to load firmware images,
it is po

feat(arm): move GPT setup to common BL source

As of now, GPT setup is being handled from BL2 for plat/arm platforms.
However, for platforms having a separate entity to load firmware images,
it is possible for BL31 to setup the GPT. In order to address this
concern, move the GPT setup implementation from arm_bl2_setup.c file to
arm_common.c. Additionally, rename the API from arm_bl2_gpt_setup to
arm_gpt_setup to make it boot stage agnostic.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I35d17a179c8746945c69db37fd23d763a7774ddc

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feat(arm): retrieve GPT related data from platform

For RME-enabled platforms, initializing L0 and L1 tables and enabling
GPC checks is necessary. For systems using BL2 to load firmware images,
the G

feat(arm): retrieve GPT related data from platform

For RME-enabled platforms, initializing L0 and L1 tables and enabling
GPC checks is necessary. For systems using BL2 to load firmware images,
the GPT initialization has to be done in BL2 prior to the image load.
The common Arm platform code currently implements this in the
"arm_bl2_plat_gpt_setup" function, relying on the FVP platform's
specifications (PAS definitions, GPCCR_PPS, and GPCCR_PGS).

Different Arm platforms may have distinct PAS definitions, GPCCR_PPS,
GPCCR_PGS, L0/L1 base, and size. To accommodate these variations,
introduce the "plat_arm_get_gpt_info" API. Platforms must implement
this API to provide the necessary data for GPT setup on RME-enabled
platforms. It is essential to note that these additions are relevant to
platforms under the plat/arm hierarchy that will reuse the
"arm_bl2_plat_gpt_setup" function.

As a result of these new additions, migrate data related to the FVP
platform to its source and header files.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I4f4c8894c1cda0adc1f83e7439eb372e923f6147

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refactor(mte): deprecate CTX_INCLUDE_MTE_REGS

Currently CTX_INCLUDE_MTE_REGS is used for dual purpose,
to enable allocation tags register and to context save and restore
them and also to check if mt

refactor(mte): deprecate CTX_INCLUDE_MTE_REGS

Currently CTX_INCLUDE_MTE_REGS is used for dual purpose,
to enable allocation tags register and to context save and restore
them and also to check if mte feature is available.

To make it more meaningful, remove CTX_INCLUDE_MTE_REGS
and introduce FEAT_MTE. This would enable allocation tags register
when FEAT_MTE is enabled and also supported from platform.

Also arch features can be conditionally enabled disabled based on
arch version from `make_helpers/arch_features.mk`

Change-Id: Ibdd2d43874634ad7ddff93c7edad6044ae1631ed
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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docs(fconf): update bindings for multi-RoT CoTs

Update CoT binding documentation to add the signing-key property
as optional in root-certificates and add rot_keys node

Change-Id: I1d1fbc0394275520c

docs(fconf): update bindings for multi-RoT CoTs

Update CoT binding documentation to add the signing-key property
as optional in root-certificates and add rot_keys node

Change-Id: I1d1fbc0394275520cfa43213d5b7006e51990fdd
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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docs: fix errata in RMM-EL3 Communication Interface documentation

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I6d6b7ff084cc731470e873cfdf37beeec0d3635a

Merge changes from topic "od/hf-doc-migration" into integration

* changes:
docs(spm-mm): remove reference to SEL2 SPMC
docs: remove SEL2 SPMC threat model
docs: remove unused SPM related diagr

Merge changes from topic "od/hf-doc-migration" into integration

* changes:
docs(spm-mm): remove reference to SEL2 SPMC
docs: remove SEL2 SPMC threat model
docs: remove unused SPM related diagrams

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docs(ras): update RAS documentation

Add details about RAS error handling philosophies and its implementation
It also updates the tests introduced to verify them.

Signed-off-by: Manish Pandey <manis

docs(ras): update RAS documentation

Add details about RAS error handling philosophies and its implementation
It also updates the tests introduced to verify them.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iedc8c1e713dad05baadd58e5752df36fa00121a7

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fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT

This patch removes RAS_FFH_SUPPORT macro which is the combination of
ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an
inter

fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT

This patch removes RAS_FFH_SUPPORT macro which is the combination of
ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an
internal macro FFH_SUPPORT which gets enabled when platforms wants
to enable lower EL EA handling at EL3. The internal macro FFH_SUPPORT
will be automatically enabled if HANDLE_EA_EL3_FIRST_NS is enabled.
FFH_SUPPORT along with ENABLE_FEAT_RAS will be used in source files
to provide equivalent check which was provided by RAS_FFH_SUPPORT
earlier. In generic code we needed a macro which could abstract both
HANDLE_EA_EL3_FIRST_NS and RAS_FFH_SUPPORT macros that had limitations.
Former was tied up with NS world only while the latter was tied to RAS
feature.

This is to allow Secure/Realm world to have their own FFH macros
in future.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ie5692ccbf462f5dcc3f005a5beea5aa35124ac73

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docs(spm-mm): remove reference to SEL2 SPMC

As the SEL2 SPMC design doc is migrated to Hafnium tree, remove the
reference to this implementation from TF-A's SPM-MM doc.

Signed-off-by: Olivier Depre

docs(spm-mm): remove reference to SEL2 SPMC

As the SEL2 SPMC design doc is migrated to Hafnium tree, remove the
reference to this implementation from TF-A's SPM-MM doc.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I1609c7d1d098420412dffc7b1309cc9c11502f8a

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feat(el3-spmc): add a flag to enable support to load SEL0 SP

Introduce a build flag for enabling the support for loading SEL0 SP in
EL3 SPMC.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>

feat(el3-spmc): add a flag to enable support to load SEL0 SP

Introduce a build flag for enabling the support for loading SEL0 SP in
EL3 SPMC.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I1d63ae4d0d8374a732113565be90d58861506e39

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refactor(el3-runtime): plat_ic_has_interrupt_type returns bool

Rather than returning 0 or 1, the above function returns bool false
or true. No functional change.

Change-Id: Iea904ffc368568208fa8203

refactor(el3-runtime): plat_ic_has_interrupt_type returns bool

Rather than returning 0 or 1, the above function returns bool false
or true. No functional change.

Change-Id: Iea904ffc368568208fa8203e0d2e0cdaa500b1e0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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docs(rme): update tftf build command

Deprecate pack_realm build command for TFTF.
To build Realm payload tests use ENABLE_REALM_PAYLOAD_TESTS=1.
This new command line for TFTF is effective from SHA

docs(rme): update tftf build command

Deprecate pack_realm build command for TFTF.
To build Realm payload tests use ENABLE_REALM_PAYLOAD_TESTS=1.
This new command line for TFTF is effective from SHA 9945bef6b
in tf-a-tests repo.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: Iee9ac9b2b367aac50677fac95631e7e4818cdf3a

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Merge "fix(doc): match boot-order size to implementation" into integration

Merge "feat(rme): save PAuth context when RME is enabled" into integration

feat(rme): save PAuth context when RME is enabled

This patch enables CTX_INCLUDE_PAUTH_REGS for RME builds.
The RMM-EL3 specification is also updated to reflect the changes
and also version of the s

feat(rme): save PAuth context when RME is enabled

This patch enables CTX_INCLUDE_PAUTH_REGS for RME builds.
The RMM-EL3 specification is also updated to reflect the changes
and also version of the same is bumped from 0.1 to 0.2.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I2e96a592d2b75abaee24294240c1727c5ceba420

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Merge "docs: fix rendering for code blocks in SPM" into integration

docs(spm): memory region nodes definition

Update the documentation related with memory region nodes
of SP's FF-A manifest, to relate to changes from patches [1].

[1] https://review.trustedfirmware.

docs(spm): memory region nodes definition

Update the documentation related with memory region nodes
of SP's FF-A manifest, to relate to changes from patches [1].

[1] https://review.trustedfirmware.org/q/topic:%22ja%252Fmem_region_fix%22+(status:open%20OR%20status:merged)

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I16595ec581b0ad9d2c20fca8dab64b6fd9ad001a

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fix(doc): match boot-order size to implementation

Docs had boot-order field as being u32 but code uses uint16_t.
FF-A specification does not specify a required size.

Signed-off-by: Kathleen Capella

fix(doc): match boot-order size to implementation

Docs had boot-order field as being u32 but code uses uint16_t.
FF-A specification does not specify a required size.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: Ia4c3fc66b9e733ea1417d34c2601bce1f81c4d32

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docs(spm): add memory sharing documentation

Add documentation that explains implementation specific
relevant information from the update done to FF-A v1.1
memory sharing in Hafnium.

Change-Id: Ifc3

docs(spm): add memory sharing documentation

Add documentation that explains implementation specific
relevant information from the update done to FF-A v1.1
memory sharing in Hafnium.

Change-Id: Ifc3c6b86c0545d53331207b017b990427ee84f2d
Signed-off-by: J-Alves <joao.alves@arm.com>

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refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firm

refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firmware first
handling(FFH) of RAS errors.
2. Manage the FEAT_RAS extension when switching the worlds.

FFH means that all the EAs from NS are trapped in EL3 first and signaled
to NS world later after the first handling is done in firmware. There is
an alternate way of handling RAS errors viz Kernel First handling(KFH).
Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the
feature is needed for proper handling KFH in as well.

This patch breaks down the RAS_EXTENSION flag into a flag to denote the
CPU architecture `ENABLE_FEAT_RAS` which is used in context management
during world switch and another flag `RAS_FFH_SUPPORT` to pull in
required framework and platform hooks for FFH.

Proper support for KFH will be added in future patches.

BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The
equivalent functionality can be achieved by the following
2 options:
- ENABLE_FEAT_RAS
- RAS_FFH_SUPPORT

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec

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docs(spm): support for handling Group0 interrupts

Please refer the doc update.

Change-Id: Ib79fae1296bc28fa9bd0cd79609d6153bb57519b
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

docs: fix rendering for code blocks in SPM

Two sample build command code blocks are not correctly
rendered by the documentation generator.

Fix that by adding newlines.

Signed-off-by: Nicola Mazzuc

docs: fix rendering for code blocks in SPM

Two sample build command code blocks are not correctly
rendered by the documentation generator.

Fix that by adding newlines.

Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com>
Change-Id: I1bb075ea4fc8e3230307548e40daecf2a79bae8d

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feat(fvp): add Event Log maximum size property in DT

Updated the code to get and set the 'tpm_event_log_max_size' property
in the event_log.dtsi.

In this change, the maximum Event Log buffer size a

feat(fvp): add Event Log maximum size property in DT

Updated the code to get and set the 'tpm_event_log_max_size' property
in the event_log.dtsi.

In this change, the maximum Event Log buffer size allocated by BL1 is
passed to BL2, rather than both relying on the maximum Event Log buffer
size macro.

Change-Id: I7aa6256390872171e362b6f166f3f7335aa6e425
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1

So far we have the ENABLE_AMU build option to include AMU register
handling code for enabling and context switch. There is also an
ENABLE_FEAT_A

refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1

So far we have the ENABLE_AMU build option to include AMU register
handling code for enabling and context switch. There is also an
ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system
register handling. The latter needs some alignment with the new feature
scheme, but it conceptually overlaps with the ENABLE_AMU option.

Since there is no real need for two separate options, unify both into a
new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at
this point, a subsequent patch will make use of the new feature handling
scheme.

Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "docs(spm): add other-s-interrupts-action field to sp manifest" into integration