1Secure Partition Manager 2************************ 3 4.. contents:: 5 6.. toctree:: 7 ffa-manifest-binding 8 9Acronyms 10======== 11 12+--------+--------------------------------------+ 13| CoT | Chain of Trust | 14+--------+--------------------------------------+ 15| DMA | Direct Memory Access | 16+--------+--------------------------------------+ 17| DTB | Device Tree Blob | 18+--------+--------------------------------------+ 19| DTS | Device Tree Source | 20+--------+--------------------------------------+ 21| EC | Execution Context | 22+--------+--------------------------------------+ 23| FIP | Firmware Image Package | 24+--------+--------------------------------------+ 25| FF-A | Firmware Framework for Arm A-profile | 26+--------+--------------------------------------+ 27| IPA | Intermediate Physical Address | 28+--------+--------------------------------------+ 29| JOP | Jump-Oriented Programming | 30+--------+--------------------------------------+ 31| NWd | Normal World | 32+--------+--------------------------------------+ 33| ODM | Original Design Manufacturer | 34+--------+--------------------------------------+ 35| OEM | Original Equipment Manufacturer | 36+--------+--------------------------------------+ 37| PA | Physical Address | 38+--------+--------------------------------------+ 39| PE | Processing Element | 40+--------+--------------------------------------+ 41| PM | Power Management | 42+--------+--------------------------------------+ 43| PVM | Primary VM | 44+--------+--------------------------------------+ 45| ROP | Return-Oriented Programming | 46+--------+--------------------------------------+ 47| SMMU | System Memory Management Unit | 48+--------+--------------------------------------+ 49| SP | Secure Partition | 50+--------+--------------------------------------+ 51| SPD | Secure Payload Dispatcher | 52+--------+--------------------------------------+ 53| SPM | Secure Partition Manager | 54+--------+--------------------------------------+ 55| SPMC | SPM Core | 56+--------+--------------------------------------+ 57| SPMD | SPM Dispatcher | 58+--------+--------------------------------------+ 59| SiP | Silicon Provider | 60+--------+--------------------------------------+ 61| SWd | Secure World | 62+--------+--------------------------------------+ 63| TLV | Tag-Length-Value | 64+--------+--------------------------------------+ 65| TOS | Trusted Operating System | 66+--------+--------------------------------------+ 67| VM | Virtual Machine | 68+--------+--------------------------------------+ 69 70Foreword 71======== 72 73Three implementations of a Secure Partition Manager co-exist in the TF-A 74codebase: 75 76#. S-EL2 SPMC based on the FF-A specification `[1]`_, enabling virtualization in 77 the secure world, managing multiple S-EL1 or S-EL0 partitions. 78#. EL3 SPMC based on the FF-A specification, managing a single S-EL1 partition 79 without virtualization in the secure world. 80#. EL3 SPM based on the MM specification, legacy implementation managing a 81 single S-EL0 partition `[2]`_. 82 83These implementations differ in their respective SW architecture and only one 84can be selected at build time. This document: 85 86- describes the implementation from bullet 1. when the SPMC resides at S-EL2. 87- is not an architecture specification and it might provide assumptions 88 on sections mandated as implementation-defined in the specification. 89- covers the implications to TF-A used as a bootloader, and Hafnium used as a 90 reference code base for an S-EL2/SPMC secure firmware on platforms 91 implementing the FEAT_SEL2 architecture extension. 92 93Terminology 94----------- 95 96- The term Hypervisor refers to the NS-EL2 component managing Virtual Machines 97 (or partitions) in the normal world. 98- The term SPMC refers to the S-EL2 component managing secure partitions in 99 the secure world when the FEAT_SEL2 architecture extension is implemented. 100- Alternatively, SPMC can refer to an S-EL1 component, itself being a secure 101 partition and implementing the FF-A ABI on platforms not implementing the 102 FEAT_SEL2 architecture extension. 103- The term VM refers to a normal world Virtual Machine managed by an Hypervisor. 104- The term SP refers to a secure world "Virtual Machine" managed by an SPMC. 105 106Support for legacy platforms 107---------------------------- 108 109The SPM is split into a dispatcher and a core component (respectively SPMD and 110SPMC) residing at different exception levels. To permit the FF-A specification 111adoption and a smooth migration, the SPMD supports an SPMC residing either at 112S-EL1 or S-EL2: 113 114- The SPMD is located at EL3 and mainly relays the FF-A protocol from NWd 115 (Hypervisor or OS kernel) to the SPMC. 116- The same SPMD component is used for both S-EL1 and S-EL2 SPMC configurations. 117- The SPMC exception level is a build time choice. 118 119TF-A supports both cases: 120 121- S-EL1 SPMC for platforms not supporting the FEAT_SEL2 architecture 122 extension. The SPMD relays the FF-A protocol from EL3 to S-EL1. 123- S-EL2 SPMC for platforms implementing the FEAT_SEL2 architecture 124 extension. The SPMD relays the FF-A protocol from EL3 to S-EL2. 125 126Sample reference stack 127====================== 128 129The following diagram illustrates a possible configuration when the 130FEAT_SEL2 architecture extension is implemented, showing the SPMD 131and SPMC, one or multiple secure partitions, with an optional 132Hypervisor: 133 134.. image:: ../resources/diagrams/ff-a-spm-sel2.png 135 136TF-A build options 137================== 138 139This section explains the TF-A build options involved in building with 140support for an FF-A based SPM where the SPMD is located at EL3 and the 141SPMC located at S-EL1, S-EL2 or EL3: 142 143- **SPD=spmd**: this option selects the SPMD component to relay the FF-A 144 protocol from NWd to SWd back and forth. It is not possible to 145 enable another Secure Payload Dispatcher when this option is chosen. 146- **SPMD_SPM_AT_SEL2**: this option adjusts the SPMC exception 147 level to being at S-EL2. It defaults to enabled (value 1) when 148 SPD=spmd is chosen. 149- **SPMC_AT_EL3**: this option adjusts the SPMC exception level to being 150 at EL3. 151- If neither ``SPMD_SPM_AT_SEL2`` or ``SPMC_AT_EL3`` are enabled the SPMC 152 exception level is set to S-EL1. 153 ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine 154 and exhaustive list of registers is visible at `[4]`_. 155- **SP_LAYOUT_FILE**: this option specifies a text description file 156 providing paths to SP binary images and manifests in DTS format 157 (see `Describing secure partitions`_). It 158 is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple 159 secure partitions are to be loaded by BL2 on behalf of the SPMC. 160 161+---------------+------------------+-------------+-------------------------+ 162| | SPMD_SPM_AT_SEL2 | SPMC_AT_EL3 | CTX_INCLUDE_EL2_REGS(*) | 163+---------------+------------------+-------------+-------------------------+ 164| SPMC at S-EL1 | 0 | 0 | 0 | 165+---------------+------------------+-------------+-------------------------+ 166| SPMC at S-EL2 | 1 (default when | 0 | 1 | 167| | SPD=spmd) | | | 168+---------------+------------------+-------------+-------------------------+ 169| SPMC at EL3 | 0 | 1 | 0 | 170+---------------+------------------+-------------+-------------------------+ 171 172Other combinations of such build options either break the build or are not 173supported. 174 175Notes: 176 177- Only Arm's FVP platform is supported to use with the TF-A reference software 178 stack. 179- When ``SPMD_SPM_AT_SEL2=1``, the reference software stack assumes enablement 180 of FEAT_PAuth, FEAT_BTI and FEAT_MTE architecture extensions. 181- ``(*) CTX_INCLUDE_EL2_REGS``, this flag is |TF-A| internal and informational 182 in this table. When set, it provides the generic support for saving/restoring 183 EL2 registers required when S-EL2 firmware is present. 184- BL32 option is re-purposed to specify the SPMC image. It can specify either 185 the Hafnium binary path (built for the secure world) or the path to a TEE 186 binary implementing FF-A interfaces. 187- BL33 option can specify the TFTF binary or a normal world loader 188 such as U-Boot or the UEFI framework payload. 189 190Sample TF-A build command line when the SPMC is located at S-EL1 191(e.g. when the FEAT_SEL2 architecture extension is not implemented): 192 193.. code:: shell 194 195 make \ 196 CROSS_COMPILE=aarch64-none-elf- \ 197 SPD=spmd \ 198 SPMD_SPM_AT_SEL2=0 \ 199 BL32=<path-to-tee-binary> \ 200 BL33=<path-to-bl33-binary> \ 201 PLAT=fvp \ 202 all fip 203 204Sample TF-A build command line when FEAT_SEL2 architecture extension is 205implemented and the SPMC is located at S-EL2: 206 207.. code:: shell 208 209 make \ 210 CROSS_COMPILE=aarch64-none-elf- \ 211 PLAT=fvp \ 212 SPD=spmd \ 213 ARM_ARCH_MINOR=5 \ 214 BRANCH_PROTECTION=1 \ 215 CTX_INCLUDE_PAUTH_REGS=1 \ 216 CTX_INCLUDE_MTE_REGS=1 \ 217 BL32=<path-to-hafnium-binary> \ 218 BL33=<path-to-bl33-binary> \ 219 SP_LAYOUT_FILE=sp_layout.json \ 220 all fip 221 222Sample TF-A build command line when FEAT_SEL2 architecture extension is 223implemented, the SPMC is located at S-EL2, and enabling secure boot: 224 225.. code:: shell 226 227 make \ 228 CROSS_COMPILE=aarch64-none-elf- \ 229 PLAT=fvp \ 230 SPD=spmd \ 231 ARM_ARCH_MINOR=5 \ 232 BRANCH_PROTECTION=1 \ 233 CTX_INCLUDE_PAUTH_REGS=1 \ 234 CTX_INCLUDE_MTE_REGS=1 \ 235 BL32=<path-to-hafnium-binary> \ 236 BL33=<path-to-bl33-binary> \ 237 SP_LAYOUT_FILE=sp_layout.json \ 238 MBEDTLS_DIR=<path-to-mbedtls-lib> \ 239 TRUSTED_BOARD_BOOT=1 \ 240 COT=dualroot \ 241 ARM_ROTPK_LOCATION=devel_rsa \ 242 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ 243 GENERATE_COT=1 \ 244 all fip 245 246Sample TF-A build command line when the SPMC is located at EL3: 247 248.. code:: shell 249 250 make \ 251 CROSS_COMPILE=aarch64-none-elf- \ 252 SPD=spmd \ 253 SPMD_SPM_AT_SEL2=0 \ 254 SPMC_AT_EL3=1 \ 255 BL32=<path-to-tee-binary> \ 256 BL33=<path-to-bl33-binary> \ 257 PLAT=fvp \ 258 all fip 259 260FVP model invocation 261==================== 262 263The FVP command line needs the following options to exercise the S-EL2 SPMC: 264 265+---------------------------------------------------+------------------------------------+ 266| - cluster0.has_arm_v8-5=1 | Implements FEAT_SEL2, FEAT_PAuth, | 267| - cluster1.has_arm_v8-5=1 | and FEAT_BTI. | 268+---------------------------------------------------+------------------------------------+ 269| - pci.pci_smmuv3.mmu.SMMU_AIDR=2 | Parameters required for the | 270| - pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B | SMMUv3.2 modeling. | 271| - pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 | | 272| - pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 | | 273| - pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 | | 274| - pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 | | 275| - pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 | | 276| - pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 | | 277+---------------------------------------------------+------------------------------------+ 278| - cluster0.has_branch_target_exception=1 | Implements FEAT_BTI. | 279| - cluster1.has_branch_target_exception=1 | | 280+---------------------------------------------------+------------------------------------+ 281| - cluster0.has_pointer_authentication=2 | Implements FEAT_PAuth | 282| - cluster1.has_pointer_authentication=2 | | 283+---------------------------------------------------+------------------------------------+ 284| - cluster0.memory_tagging_support_level=2 | Implements FEAT_MTE2 | 285| - cluster1.memory_tagging_support_level=2 | | 286| - bp.dram_metadata.is_enabled=1 | | 287+---------------------------------------------------+------------------------------------+ 288 289Sample FVP command line invocation: 290 291.. code:: shell 292 293 <path-to-fvp-model>/FVP_Base_RevC-2xAEMvA -C pctl.startup=0.0.0.0 \ 294 -C cluster0.NUM_CORES=4 -C cluster1.NUM_CORES=4 -C bp.secure_memory=1 \ 295 -C bp.secureflashloader.fname=trusted-firmware-a/build/fvp/debug/bl1.bin \ 296 -C bp.flashloader0.fname=trusted-firmware-a/build/fvp/debug/fip.bin \ 297 -C bp.pl011_uart0.out_file=fvp-uart0.log -C bp.pl011_uart1.out_file=fvp-uart1.log \ 298 -C bp.pl011_uart2.out_file=fvp-uart2.log \ 299 -C cluster0.has_arm_v8-5=1 -C cluster1.has_arm_v8-5=1 \ 300 -C cluster0.has_pointer_authentication=2 -C cluster1.has_pointer_authentication=2 \ 301 -C cluster0.has_branch_target_exception=1 -C cluster1.has_branch_target_exception=1 \ 302 -C cluster0.memory_tagging_support_level=2 -C cluster1.memory_tagging_support_level=2 \ 303 -C bp.dram_metadata.is_enabled=1 \ 304 -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B \ 305 -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 \ 306 -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 \ 307 -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 308 309Boot process 310============ 311 312Loading Hafnium and secure partitions in the secure world 313--------------------------------------------------------- 314 315TF-A BL2 is the bootlader for the SPMC and SPs in the secure world. 316 317SPs may be signed by different parties (SiP, OEM/ODM, TOS vendor, etc.). 318Thus they are supplied as distinct signed entities within the FIP flash 319image. The FIP image itself is not signed hence this provides the ability 320to upgrade SPs in the field. 321 322Booting through TF-A 323-------------------- 324 325SP manifests 326~~~~~~~~~~~~ 327 328An SP manifest describes SP attributes as defined in `[1]`_ 329(partition manifest at virtual FF-A instance) in DTS format. It is 330represented as a single file associated with the SP. A sample is 331provided by `[5]`_. A binding document is provided by `[6]`_. 332 333Secure Partition packages 334~~~~~~~~~~~~~~~~~~~~~~~~~ 335 336Secure partitions are bundled as independent package files consisting 337of: 338 339- a header 340- a DTB 341- an image payload 342 343The header starts with a magic value and offset values to SP DTB and 344image payload. Each SP package is loaded independently by BL2 loader 345and verified for authenticity and integrity. 346 347The SP package identified by its UUID (matching FF-A uuid property) is 348inserted as a single entry into the FIP at end of the TF-A build flow 349as shown: 350 351.. code:: shell 352 353 Trusted Boot Firmware BL2: offset=0x1F0, size=0x8AE1, cmdline="--tb-fw" 354 EL3 Runtime Firmware BL31: offset=0x8CD1, size=0x13000, cmdline="--soc-fw" 355 Secure Payload BL32 (Trusted OS): offset=0x1BCD1, size=0x15270, cmdline="--tos-fw" 356 Non-Trusted Firmware BL33: offset=0x30F41, size=0x92E0, cmdline="--nt-fw" 357 HW_CONFIG: offset=0x3A221, size=0x2348, cmdline="--hw-config" 358 TB_FW_CONFIG: offset=0x3C569, size=0x37A, cmdline="--tb-fw-config" 359 SOC_FW_CONFIG: offset=0x3C8E3, size=0x48, cmdline="--soc-fw-config" 360 TOS_FW_CONFIG: offset=0x3C92B, size=0x427, cmdline="--tos-fw-config" 361 NT_FW_CONFIG: offset=0x3CD52, size=0x48, cmdline="--nt-fw-config" 362 B4B5671E-4A90-4FE1-B81F-FB13DAE1DACB: offset=0x3CD9A, size=0xC168, cmdline="--blob" 363 D1582309-F023-47B9-827C-4464F5578FC8: offset=0x48F02, size=0xC168, cmdline="--blob" 364 365.. uml:: ../resources/diagrams/plantuml/fip-secure-partitions.puml 366 367Describing secure partitions 368~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 369 370A json-formatted description file is passed to the build flow specifying paths 371to the SP binary image and associated DTS partition manifest file. The latter 372is processed by the dtc compiler to generate a DTB fed into the SP package. 373Optionally, the partition's json description can contain offsets for both 374the image and partition manifest within the SP package. Both offsets need to be 3754KB aligned, because it is the translation granule supported by Hafnium SPMC. 376These fields can be leveraged to support SPs with S1 translation granules that 377differ from 4KB, and to configure the regions allocated within the SP package, 378as well as to comply with the requirements for the implementation of the boot 379information protocol (see `Passing boot data to the SP`_ for more details). In 380case the offsets are absent in their json node, they default to 0x1000 and 3810x4000 for the manifest offset and image offset respectively. 382This file also specifies the SP owner (as an optional field) identifying the 383signing domain in case of dual root CoT. 384The SP owner can either be the silicon or the platform provider. The 385corresponding "owner" field value can either take the value of "SiP" or "Plat". 386In absence of "owner" field, it defaults to "SiP" owner. 387The UUID of the partition can be specified as a field in the description file or 388if it does not exist there the UUID is extracted from the DTS partition 389manifest. 390 391.. code:: shell 392 393 { 394 "tee1" : { 395 "image": "tee1.bin", 396 "pm": "tee1.dts", 397 "owner": "SiP", 398 "uuid": "1b1820fe-48f7-4175-8999-d51da00b7c9f" 399 }, 400 401 "tee2" : { 402 "image": "tee2.bin", 403 "pm": "tee2.dts", 404 "owner": "Plat" 405 }, 406 407 "tee3" : { 408 "image": { 409 "file": "tee3.bin", 410 "offset":"0x2000" 411 }, 412 "pm": { 413 "file": "tee3.dts", 414 "offset":"0x6000" 415 }, 416 "owner": "Plat" 417 }, 418 } 419 420SPMC manifest 421~~~~~~~~~~~~~ 422 423This manifest contains the SPMC *attribute* node consumed by the SPMD at boot 424time. It implements `[1]`_ (SP manifest at physical FF-A instance) and serves 425two different cases: 426 427- The SPMC resides at S-EL1: the SPMC manifest is used by the SPMD to setup a 428 SP that co-resides with the SPMC and executes at S-EL1 or Secure Supervisor 429 mode. 430- The SPMC resides at S-EL2: the SPMC manifest is used by the SPMD to setup 431 the environment required by the SPMC to run at S-EL2. SPs run at S-EL1 or 432 S-EL0. 433 434.. code:: shell 435 436 attribute { 437 spmc_id = <0x8000>; 438 maj_ver = <0x1>; 439 min_ver = <0x1>; 440 exec_state = <0x0>; 441 load_address = <0x0 0x6000000>; 442 entrypoint = <0x0 0x6000000>; 443 binary_size = <0x60000>; 444 }; 445 446- *spmc_id* defines the endpoint ID value that SPMC can query through 447 ``FFA_ID_GET``. 448- *maj_ver/min_ver*. SPMD checks provided version versus its internal 449 version and aborts if not matching. 450- *exec_state* defines the SPMC execution state (AArch64 or AArch32). 451 Notice Hafnium used as a SPMC only supports AArch64. 452- *load_address* and *binary_size* are mostly used to verify secondary 453 entry points fit into the loaded binary image. 454- *entrypoint* defines the cold boot primary core entry point used by 455 SPMD (currently matches ``BL32_BASE``) to enter the SPMC. 456 457Other nodes in the manifest are consumed by Hafnium in the secure world. 458A sample can be found at `[7]`_: 459 460- The *hypervisor* node describes SPs. *is_ffa_partition* boolean attribute 461 indicates a FF-A compliant SP. The *load_address* field specifies the load 462 address at which BL2 loaded the SP package. 463- *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping. 464 Note the primary core is declared first, then secondary cores are declared 465 in reverse order. 466- The *memory* node provides platform information on the ranges of memory 467 available to the SPMC. 468 469SPMC boot 470~~~~~~~~~ 471 472The SPMC is loaded by BL2 as the BL32 image. 473 474The SPMC manifest is loaded by BL2 as the ``TOS_FW_CONFIG`` image `[9]`_. 475 476BL2 passes the SPMC manifest address to BL31 through a register. 477 478At boot time, the SPMD in BL31 runs from the primary core, initializes the core 479contexts and launches the SPMC (BL32) passing the following information through 480registers: 481 482- X0 holds the ``TOS_FW_CONFIG`` physical address (or SPMC manifest blob). 483- X1 holds the ``HW_CONFIG`` physical address. 484- X4 holds the currently running core linear id. 485 486Loading of SPs 487~~~~~~~~~~~~~~ 488 489At boot time, BL2 loads SPs sequentially in addition to the SPMC as depicted 490below: 491 492.. uml:: ../resources/diagrams/plantuml/bl2-loading-sp.puml 493 494Note this boot flow is an implementation sample on Arm's FVP platform. 495Platforms not using TF-A's *Firmware CONFiguration* framework would adjust to a 496different boot flow. The flow restricts to a maximum of 8 secure partitions. 497 498Secure boot 499~~~~~~~~~~~ 500 501The SP content certificate is inserted as a separate FIP item so that BL2 loads SPMC, 502SPMC manifest, secure partitions and verifies them for authenticity and integrity. 503Refer to TBBR specification `[3]`_. 504 505The multiple-signing domain feature (in current state dual signing domain `[8]`_) allows 506the use of two root keys namely S-ROTPK and NS-ROTPK: 507 508- SPMC (BL32) and SPMC manifest are signed by the SiP using the S-ROTPK. 509- BL33 may be signed by the OEM using NS-ROTPK. 510- An SP may be signed either by SiP (using S-ROTPK) or by OEM (using NS-ROTPK). 511- A maximum of 4 partitions can be signed with the S-ROTPK key and 4 partitions 512 signed with the NS-ROTPK key. 513 514Also refer to `Describing secure partitions`_ and `TF-A build options`_ sections. 515 516Hafnium in the secure world 517=========================== 518 519General considerations 520---------------------- 521 522Build platform for the secure world 523~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 524 525In the Hafnium reference implementation specific code parts are only relevant to 526the secure world. Such portions are isolated in architecture specific files 527and/or enclosed by a ``SECURE_WORLD`` macro. 528 529Secure partitions scheduling 530~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 531 532The FF-A specification `[1]`_ provides two ways to relinquinsh CPU time to 533secure partitions. For this a VM (Hypervisor or OS kernel), or SP invokes one of: 534 535- the FFA_MSG_SEND_DIRECT_REQ interface. 536- the FFA_RUN interface. 537 538Additionally a secure interrupt can pre-empt the normal world execution and give 539CPU cycles by transitioning to EL3 and S-EL2. 540 541Platform topology 542~~~~~~~~~~~~~~~~~ 543 544The *execution-ctx-count* SP manifest field can take the value of one or the 545total number of PEs. The FF-A specification `[1]`_ recommends the 546following SP types: 547 548- Pinned MP SPs: an execution context matches a physical PE. MP SPs must 549 implement the same number of ECs as the number of PEs in the platform. 550- Migratable UP SPs: a single execution context can run and be migrated on any 551 physical PE. Such SP declares a single EC in its SP manifest. An UP SP can 552 receive a direct message request originating from any physical core targeting 553 the single execution context. 554 555Parsing SP partition manifests 556------------------------------ 557 558Hafnium consumes SP manifests as defined in `[1]`_ and `SP manifests`_. 559Note the current implementation may not implement all optional fields. 560 561The SP manifest may contain memory and device regions nodes. In case of 562an S-EL2 SPMC: 563 564- Memory regions are mapped in the SP EL1&0 Stage-2 translation regime at 565 load time (or EL1&0 Stage-1 for an S-EL1 SPMC). A memory region node can 566 specify RX/TX buffer regions in which case it is not necessary for an SP 567 to explicitly invoke the ``FFA_RXTX_MAP`` interface. 568- Device regions are mapped in the SP EL1&0 Stage-2 translation regime (or 569 EL1&0 Stage-1 for an S-EL1 SPMC) as peripherals and possibly allocate 570 additional resources (e.g. interrupts). 571 572For the S-EL2 SPMC, base addresses for memory and device region nodes are IPAs 573provided the SPMC identity maps IPAs to PAs within SP EL1&0 Stage-2 translation 574regime. 575 576Note: in the current implementation both VTTBR_EL2 and VSTTBR_EL2 point to the 577same set of page tables. It is still open whether two sets of page tables shall 578be provided per SP. The memory region node as defined in the specification 579provides a memory security attribute hinting to map either to the secure or 580non-secure EL1&0 Stage-2 table if it exists. 581 582Passing boot data to the SP 583--------------------------- 584 585In `[1]`_ , the section "Boot information protocol" defines a method for passing 586data to the SPs at boot time. It specifies the format for the boot information 587descriptor and boot information header structures, which describe the data to be 588exchanged between SPMC and SP. 589The specification also defines the types of data that can be passed. 590The aggregate of both the boot info structures and the data itself is designated 591the boot information blob, and is passed to a Partition as a contiguous memory 592region. 593 594Currently, the SPM implementation supports the FDT type which is used to pass the 595partition's DTB manifest. 596 597The region for the boot information blob is allocated through the SP package. 598 599.. image:: ../resources/diagrams/partition-package.png 600 601To adjust the space allocated for the boot information blob, the json description 602of the SP (see section `Describing secure partitions`_) shall be updated to contain 603the manifest offset. If no offset is provided the manifest offset defaults to 0x1000, 604which is the page size in the Hafnium SPMC. 605 606The configuration of the boot protocol is done in the SPs manifest. As defined by 607the specification, the manifest field 'gp-register-num' configures the GP register 608which shall be used to pass the address to the partitions boot information blob when 609booting the partition. 610In addition, the Hafnium SPMC implementation requires the boot information arguments 611to be listed in a designated DT node: 612 613.. code:: shell 614 615 boot-info { 616 compatible = "arm,ffa-manifest-boot-info"; 617 ffa_manifest; 618 }; 619 620The whole secure partition package image (see `Secure Partition packages`_) is 621mapped to the SP secure EL1&0 Stage-2 translation regime. As such, the SP can 622retrieve the address for the boot information blob in the designated GP register, 623process the boot information header and descriptors, access its own manifest 624DTB blob and extract its partition manifest properties. 625 626SP Boot order 627------------- 628 629SP manifests provide an optional boot order attribute meant to resolve 630dependencies such as an SP providing a service required to properly boot 631another SP. SPMC boots the SPs in accordance to the boot order attribute, 632lowest to the highest value. If the boot order attribute is absent from the FF-A 633manifest, the SP is treated as if it had the highest boot order value 634(i.e. lowest booting priority). 635 636It is possible for an SP to call into another SP through a direct request 637provided the latter SP has already been booted. 638 639Boot phases 640----------- 641 642Primary core boot-up 643~~~~~~~~~~~~~~~~~~~~ 644 645Upon boot-up, BL31 hands over to the SPMC (BL32) on the primary boot physical 646core. The SPMC performs its platform initializations and registers the SPMC 647secondary physical core entry point physical address by the use of the 648`FFA_SECONDARY_EP_REGISTER`_ interface (SMC invocation from the SPMC to the SPMD 649at secure physical FF-A instance). 650 651The SPMC then creates secure partitions based on SP packages and manifests. Each 652secure partition is launched in sequence (`SP Boot order`_) on their "primary" 653execution context. If the primary boot physical core linear id is N, an MP SP is 654started using EC[N] on PE[N] (see `Platform topology`_). If the partition is a 655UP SP, it is started using its unique EC0 on PE[N]. 656 657The SP primary EC (or the EC used when the partition is booted as described 658above): 659 660- Performs the overall SP boot time initialization, and in case of a MP SP, 661 prepares the SP environment for other execution contexts. 662- In the case of a MP SP, it invokes the FFA_SECONDARY_EP_REGISTER at secure 663 virtual FF-A instance (SMC invocation from SP to SPMC) to provide the IPA 664 entry point for other execution contexts. 665- Exits through ``FFA_MSG_WAIT`` to indicate successful initialization or 666 ``FFA_ERROR`` in case of failure. 667 668Secondary cores boot-up 669~~~~~~~~~~~~~~~~~~~~~~~ 670 671Once the system is started and NWd brought up, a secondary physical core is 672woken up by the ``PSCI_CPU_ON`` service invocation. The TF-A SPD hook mechanism 673calls into the SPMD on the newly woken up physical core. Then the SPMC is 674entered at the secondary physical core entry point. 675 676In the current implementation, the first SP is resumed on the coresponding EC 677(the virtual CPU which matches the physical core). The implication is that the 678first SP must be a MP SP. 679 680In a linux based system, once secure and normal worlds are booted but prior to 681a NWd FF-A driver has been loaded: 682 683- The first SP has initialized all its ECs in response to primary core boot up 684 (at system initialization) and secondary core boot up (as a result of linux 685 invoking PSCI_CPU_ON for all secondary cores). 686- Other SPs have their first execution context initialized as a result of secure 687 world initialization on the primary boot core. Other ECs for those SPs have to 688 be run first through ffa_run to complete their initialization (which results 689 in the EC completing with FFA_MSG_WAIT). 690 691Refer to `Power management`_ for further details. 692 693Notifications 694------------- 695 696The FF-A v1.1 specification `[1]`_ defines notifications as an asynchronous 697communication mechanism with non-blocking semantics. It allows for one FF-A 698endpoint to signal another for service provision, without hindering its current 699progress. 700 701Hafnium currently supports 64 notifications. The IDs of each notification define 702a position in a 64-bit bitmap. 703 704The signaling of notifications can interchangeably happen between NWd and SWd 705FF-A endpoints. 706 707The SPMC is in charge of managing notifications from SPs to SPs, from SPs to 708VMs, and from VMs to SPs. An hypervisor component would only manage 709notifications from VMs to VMs. Given the SPMC has no visibility of the endpoints 710deployed in NWd, the Hypervisor or OS kernel must invoke the interface 711FFA_NOTIFICATION_BITMAP_CREATE to allocate the notifications bitmap per FF-A 712endpoint in the NWd that supports it. 713 714A sender can signal notifications once the receiver has provided it with 715permissions. Permissions are provided by invoking the interface 716FFA_NOTIFICATION_BIND. 717 718Notifications are signaled by invoking FFA_NOTIFICATION_SET. Henceforth 719they are considered to be in a pending sate. The receiver can retrieve its 720pending notifications invoking FFA_NOTIFICATION_GET, which, from that moment, 721are considered to be handled. 722 723Per the FF-A v1.1 spec, each FF-A endpoint must be associated with a scheduler 724that is in charge of donating CPU cycles for notifications handling. The 725FF-A driver calls FFA_NOTIFICATION_INFO_GET to retrieve the information about 726which FF-A endpoints have pending notifications. The receiver scheduler is 727called and informed by the FF-A driver, and it should allocate CPU cycles to the 728receiver. 729 730There are two types of notifications supported: 731 732- Global, which are targeted to a FF-A endpoint and can be handled within any of 733 its execution contexts, as determined by the scheduler of the system. 734- Per-vCPU, which are targeted to a FF-A endpoint and to be handled within a 735 a specific execution context, as determined by the sender. 736 737The type of a notification is set when invoking FFA_NOTIFICATION_BIND to give 738permissions to the sender. 739 740Notification signaling resorts to two interrupts: 741 742- Schedule Receiver Interrupt: non-secure physical interrupt to be handled by 743 the FF-A driver within the receiver scheduler. At initialization the SPMC 744 donates a SGI ID chosen from the secure SGI IDs range and configures it as 745 non-secure. The SPMC triggers this SGI on the currently running core when 746 there are pending notifications, and the respective receivers need CPU cycles 747 to handle them. 748- Notifications Pending Interrupt: virtual interrupt to be handled by the 749 receiver of the notification. Set when there are pending notifications for the 750 given secure partition. The NPI is pended when the NWd relinquishes CPU cycles 751 to an SP. 752 753The notifications receipt support is enabled in the partition FF-A manifest. 754 755Mandatory interfaces 756-------------------- 757 758The following interfaces are exposed to SPs: 759 760- ``FFA_VERSION`` 761- ``FFA_FEATURES`` 762- ``FFA_RX_RELEASE`` 763- ``FFA_RXTX_MAP`` 764- ``FFA_RXTX_UNMAP`` 765- ``FFA_PARTITION_INFO_GET`` 766- ``FFA_ID_GET`` 767- ``FFA_MSG_WAIT`` 768- ``FFA_MSG_SEND_DIRECT_REQ`` 769- ``FFA_MSG_SEND_DIRECT_RESP`` 770- ``FFA_MEM_DONATE`` 771- ``FFA_MEM_LEND`` 772- ``FFA_MEM_SHARE`` 773- ``FFA_MEM_RETRIEVE_REQ`` 774- ``FFA_MEM_RETRIEVE_RESP`` 775- ``FFA_MEM_RELINQUISH`` 776- ``FFA_MEM_FRAG_RX`` 777- ``FFA_MEM_FRAG_TX`` 778- ``FFA_MEM_RECLAIM`` 779- ``FFA_RUN`` 780 781As part of the FF-A v1.1 support, the following interfaces were added: 782 783 - ``FFA_NOTIFICATION_BITMAP_CREATE`` 784 - ``FFA_NOTIFICATION_BITMAP_DESTROY`` 785 - ``FFA_NOTIFICATION_BIND`` 786 - ``FFA_NOTIFICATION_UNBIND`` 787 - ``FFA_NOTIFICATION_SET`` 788 - ``FFA_NOTIFICATION_GET`` 789 - ``FFA_NOTIFICATION_INFO_GET`` 790 - ``FFA_SPM_ID_GET`` 791 - ``FFA_SECONDARY_EP_REGISTER`` 792 - ``FFA_MEM_PERM_GET`` 793 - ``FFA_MEM_PERM_SET`` 794 - ``FFA_MSG_SEND2`` 795 - ``FFA_RX_ACQUIRE`` 796 797FFA_VERSION 798~~~~~~~~~~~ 799 800``FFA_VERSION`` requires a *requested_version* parameter from the caller. 801The returned value depends on the caller: 802 803- Hypervisor or OS kernel in NS-EL1/EL2: the SPMD returns the SPMC version 804 specified in the SPMC manifest. 805- SP: the SPMC returns its own implemented version. 806- SPMC at S-EL1/S-EL2: the SPMD returns its own implemented version. 807 808FFA_FEATURES 809~~~~~~~~~~~~ 810 811FF-A features supported by the SPMC may be discovered by secure partitions at 812boot (that is prior to NWd is booted) or run-time. 813 814The SPMC calling FFA_FEATURES at secure physical FF-A instance always get 815FFA_SUCCESS from the SPMD. 816 817The request made by an Hypervisor or OS kernel is forwarded to the SPMC and 818the response relayed back to the NWd. 819 820FFA_RXTX_MAP/FFA_RXTX_UNMAP 821~~~~~~~~~~~~~~~~~~~~~~~~~~~ 822 823When invoked from a secure partition FFA_RXTX_MAP maps the provided send and 824receive buffers described by their IPAs to the SP EL1&0 Stage-2 translation 825regime as secure buffers in the MMU descriptors. 826 827When invoked from the Hypervisor or OS kernel, the buffers are mapped into the 828SPMC EL2 Stage-1 translation regime and marked as NS buffers in the MMU 829descriptors. The provided addresses may be owned by a VM in the normal world, 830which is expected to receive messages from the secure world. The SPMC will in 831this case allocate internal state structures to facilitate RX buffer access 832synchronization (through FFA_RX_ACQUIRE interface), and to permit SPs to send 833messages. 834 835The FFA_RXTX_UNMAP unmaps the RX/TX pair from the translation regime of the 836caller, either it being the Hypervisor or OS kernel, as well as a secure 837partition. 838 839FFA_PARTITION_INFO_GET 840~~~~~~~~~~~~~~~~~~~~~~ 841 842Partition info get call can originate: 843 844- from SP to SPMC 845- from Hypervisor or OS kernel to SPMC. The request is relayed by the SPMD. 846 847FFA_ID_GET 848~~~~~~~~~~ 849 850The FF-A id space is split into a non-secure space and secure space: 851 852- FF-A ID with bit 15 clear relates to VMs. 853- FF-A ID with bit 15 set related to SPs. 854- FF-A IDs 0, 0xffff, 0x8000 are assigned respectively to the Hypervisor, SPMD 855 and SPMC. 856 857The SPMD returns: 858 859- The default zero value on invocation from the Hypervisor. 860- The ``spmc_id`` value specified in the SPMC manifest on invocation from 861 the SPMC (see `SPMC manifest`_) 862 863This convention helps the SPMC to determine the origin and destination worlds in 864an FF-A ABI invocation. In particular the SPMC shall filter unauthorized 865transactions in its world switch routine. It must not be permitted for a VM to 866use a secure FF-A ID as origin world by spoofing: 867 868- A VM-to-SP direct request/response shall set the origin world to be non-secure 869 (FF-A ID bit 15 clear) and destination world to be secure (FF-A ID bit 15 870 set). 871- Similarly, an SP-to-SP direct request/response shall set the FF-A ID bit 15 872 for both origin and destination IDs. 873 874An incoming direct message request arriving at SPMD from NWd is forwarded to 875SPMC without a specific check. The SPMC is resumed through eret and "knows" the 876message is coming from normal world in this specific code path. Thus the origin 877endpoint ID must be checked by SPMC for being a normal world ID. 878 879An SP sending a direct message request must have bit 15 set in its origin 880endpoint ID and this can be checked by the SPMC when the SP invokes the ABI. 881 882The SPMC shall reject the direct message if the claimed world in origin endpoint 883ID is not consistent: 884 885- It is either forwarded by SPMD and thus origin endpoint ID must be a "normal 886 world ID", 887- or initiated by an SP and thus origin endpoint ID must be a "secure world ID". 888 889 890FFA_MSG_SEND_DIRECT_REQ/FFA_MSG_SEND_DIRECT_RESP 891~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 892 893This is a mandatory interface for secure partitions consisting in direct request 894and responses with the following rules: 895 896- An SP can send a direct request to another SP. 897- An SP can receive a direct request from another SP. 898- An SP can send a direct response to another SP. 899- An SP cannot send a direct request to an Hypervisor or OS kernel. 900- An Hypervisor or OS kernel can send a direct request to an SP. 901- An SP can send a direct response to an Hypervisor or OS kernel. 902 903FFA_NOTIFICATION_BITMAP_CREATE/FFA_NOTIFICATION_BITMAP_DESTROY 904~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 905 906The secure partitions notifications bitmap are statically allocated by the SPMC. 907Hence, this interface is not to be issued by secure partitions. 908 909At initialization, the SPMC is not aware of VMs/partitions deployed in the 910normal world. Hence, the Hypervisor or OS kernel must use both ABIs for SPMC 911to be prepared to handle notifications for the provided VM ID. 912 913FFA_NOTIFICATION_BIND/FFA_NOTIFICATION_UNBIND 914~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 915 916Pair of interfaces to manage permissions to signal notifications. Prior to 917handling notifications, an FF-A endpoint must allow a given sender to signal a 918bitmap of notifications. 919 920If the receiver doesn't have notification support enabled in its FF-A manifest, 921it won't be able to bind notifications, hence forbidding it to receive any 922notifications. 923 924FFA_NOTIFICATION_SET/FFA_NOTIFICATION_GET 925~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 926 927FFA_NOTIFICATION_GET retrieves all pending global notifications and 928per-vCPU notifications targeted to the current vCPU. 929 930Hafnium maintains a global count of pending notifications which gets incremented 931and decremented when handling FFA_NOTIFICATION_SET and FFA_NOTIFICATION_GET 932respectively. A delayed SRI is triggered if the counter is non-zero when the 933SPMC returns to normal world. 934 935FFA_NOTIFICATION_INFO_GET 936~~~~~~~~~~~~~~~~~~~~~~~~~ 937 938Hafnium maintains a global count of pending notifications whose information 939has been retrieved by this interface. The count is incremented and decremented 940when handling FFA_NOTIFICATION_INFO_GET and FFA_NOTIFICATION_GET respectively. 941It also tracks notifications whose information has been retrieved individually, 942such that it avoids duplicating returned information for subsequent calls to 943FFA_NOTIFICATION_INFO_GET. For each notification, this state information is 944reset when receiver called FFA_NOTIFICATION_GET to retrieve them. 945 946FFA_SPM_ID_GET 947~~~~~~~~~~~~~~ 948 949Returns the FF-A ID allocated to an SPM component which can be one of SPMD 950or SPMC. 951 952At initialization, the SPMC queries the SPMD for the SPMC ID, using the 953FFA_ID_GET interface, and records it. The SPMC can also query the SPMD ID using 954the FFA_SPM_ID_GET interface at the secure physical FF-A instance. 955 956Secure partitions call this interface at the virtual FF-A instance, to which 957the SPMC returns the priorly retrieved SPMC ID. 958 959The Hypervisor or OS kernel can issue the FFA_SPM_ID_GET call handled by the 960SPMD, which returns the SPMC ID. 961 962FFA_SECONDARY_EP_REGISTER 963~~~~~~~~~~~~~~~~~~~~~~~~~ 964 965When the SPMC boots, all secure partitions are initialized on their primary 966Execution Context. 967 968The FFA_SECONDARY_EP_REGISTER interface is to be used by a secure partition 969from its first execution context, to provide the entry point address for 970secondary execution contexts. 971 972A secondary EC is first resumed either upon invocation of PSCI_CPU_ON from 973the NWd or by invocation of FFA_RUN. 974 975FFA_RX_ACQUIRE/FFA_RX_RELEASE 976~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 977 978The RX buffers can be used to pass information to an FF-A endpoint in the 979following scenarios: 980 981 - When it was targetted by a FFA_MSG_SEND2 invokation from another endpoint. 982 - Return the result of calling ``FFA_PARTITION_INFO_GET``. 983 - In a memory share operation, as part of the ``FFA_MEM_RETRIEVE_RESP``, 984 with the memory descriptor of the shared memory. 985 986If a normal world VM is expected to exchange messages with secure world, 987its RX/TX buffer addresses are forwarded to the SPMC via FFA_RXTX_MAP ABI, 988and are from this moment owned by the SPMC. 989The hypervisor must call the FFA_RX_ACQUIRE interface before attempting 990to use the RX buffer, in any of the aforementioned scenarios. A successful 991call to FFA_RX_ACQUIRE transfers ownership of RX buffer to hypervisor, such 992that it can be safely used. 993 994The FFA_RX_RELEASE interface is used after the FF-A endpoint is done with 995processing the data received in its RX buffer. If the RX buffer has been 996acquired by the hypervisor, the FFA_RX_RELEASE call must be forwarded to 997the SPMC to reestablish SPMC's RX ownership. 998 999An attempt from an SP to send a message to a normal world VM whose RX buffer 1000was acquired by the hypervisor fails with error code FFA_BUSY, to preserve 1001the RX buffer integrity. 1002The operation could then be conducted after FFA_RX_RELEASE. 1003 1004FFA_MSG_SEND2 1005~~~~~~~~~~~~~ 1006 1007Hafnium copies a message from the sender TX buffer into receiver's RX buffer. 1008For messages from SPs to VMs, operation is only possible if the SPMC owns 1009the receiver's RX buffer. 1010 1011Both receiver and sender need to enable support for indirect messaging, 1012in their respective partition manifest. The discovery of support 1013of such feature can be done via FFA_PARTITION_INFO_GET. 1014 1015On a successful message send, Hafnium pends an RX buffer full framework 1016notification for the receiver, to inform it about a message in the RX buffer. 1017 1018The handling of framework notifications is similar to that of 1019global notifications. Binding of these is not necessary, as these are 1020reserved to be used by the hypervisor or SPMC. 1021 1022SPMC-SPMD direct requests/responses 1023----------------------------------- 1024 1025Implementation-defined FF-A IDs are allocated to the SPMC and SPMD. 1026Using those IDs in source/destination fields of a direct request/response 1027permits SPMD to SPMC communication and either way. 1028 1029- SPMC to SPMD direct request/response uses SMC conduit. 1030- SPMD to SPMC direct request/response uses ERET conduit. 1031 1032This is used in particular to convey power management messages. 1033 1034PE MMU configuration 1035-------------------- 1036 1037With secure virtualization enabled (``HCR_EL2.VM = 1``) and for S-EL1 1038partitions, two IPA spaces (secure and non-secure) are output from the 1039secure EL1&0 Stage-1 translation. 1040The EL1&0 Stage-2 translation hardware is fed by: 1041 1042- A secure IPA when the SP EL1&0 Stage-1 MMU is disabled. 1043- One of secure or non-secure IPA when the secure EL1&0 Stage-1 MMU is enabled. 1044 1045``VTCR_EL2`` and ``VSTCR_EL2`` provide configuration bits for controlling the 1046NS/S IPA translations. The following controls are set up: 1047``VSTCR_EL2.SW = 0`` , ``VSTCR_EL2.SA = 0``, ``VTCR_EL2.NSW = 0``, 1048``VTCR_EL2.NSA = 1``: 1049 1050- Stage-2 translations for the NS IPA space access the NS PA space. 1051- Stage-2 translation table walks for the NS IPA space are to the secure PA space. 1052 1053Secure and non-secure IPA regions (rooted to by ``VTTBR_EL2`` and ``VSTTBR_EL2``) 1054use the same set of Stage-2 page tables within a SP. 1055 1056The ``VTCR_EL2/VSTCR_EL2/VTTBR_EL2/VSTTBR_EL2`` virtual address space 1057configuration is made part of a vCPU context. 1058 1059For S-EL0 partitions with VHE enabled, a single secure EL2&0 Stage-1 translation 1060regime is used for both Hafnium and the partition. 1061 1062Schedule modes and SP Call chains 1063--------------------------------- 1064 1065An SP execution context is said to be in SPMC scheduled mode if CPU cycles are 1066allocated to it by SPMC. Correspondingly, an SP execution context is said to be 1067in Normal world scheduled mode if CPU cycles are allocated by the normal world. 1068 1069A call chain represents all SPs in a sequence of invocations of a direct message 1070request. When execution on a PE is in the secure state, only a single call chain 1071that runs in the Normal World scheduled mode can exist. FF-A v1.1 spec allows 1072any number of call chains to run in the SPMC scheduled mode but the Hafnium 1073SPMC restricts the number of call chains in SPMC scheduled mode to only one for 1074keeping the implementation simple. 1075 1076Partition runtime models 1077------------------------ 1078 1079The runtime model of an endpoint describes the transitions permitted for an 1080execution context between various states. These are the four partition runtime 1081models supported (refer to `[1]`_ section 7): 1082 1083 - RTM_FFA_RUN: runtime model presented to an execution context that is 1084 allocated CPU cycles through FFA_RUN interface. 1085 - RTM_FFA_DIR_REQ: runtime model presented to an execution context that is 1086 allocated CPU cycles through FFA_MSG_SEND_DIRECT_REQ interface. 1087 - RTM_SEC_INTERRUPT: runtime model presented to an execution context that is 1088 allocated CPU cycles by SPMC to handle a secure interrupt. 1089 - RTM_SP_INIT: runtime model presented to an execution context that is 1090 allocated CPU cycles by SPMC to initialize its state. 1091 1092If an endpoint execution context attempts to make an invalid transition or a 1093valid transition that could lead to a loop in the call chain, SPMC denies the 1094transition with the help of above runtime models. 1095 1096Interrupt management 1097-------------------- 1098 1099GIC ownership 1100~~~~~~~~~~~~~ 1101 1102The SPMC owns the GIC configuration. Secure and non-secure interrupts are 1103trapped at S-EL2. The SPMC manages interrupt resources and allocates interrupt 1104IDs based on SP manifests. The SPMC acknowledges physical interrupts and injects 1105virtual interrupts by setting the use of vIRQ/vFIQ bits before resuming a SP. 1106 1107Abbreviations: 1108 1109 - NS-Int: A non-secure physical interrupt. It requires a switch to the normal 1110 world to be handled if it triggers while execution is in secure world. 1111 - Other S-Int: A secure physical interrupt targeted to an SP different from 1112 the one that is currently running. 1113 - Self S-Int: A secure physical interrupt targeted to the SP that is currently 1114 running. 1115 1116Non-secure interrupt handling 1117~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1118 1119This section documents the actions supported in SPMC in response to a non-secure 1120interrupt as per the guidance provided by FF-A v1.1 EAC0 specification. 1121An SP specifies one of the following actions in its partition manifest: 1122 1123 - Non-secure interrupt is signaled. 1124 - Non-secure interrupt is signaled after a managed exit. 1125 - Non-secure interrupt is queued. 1126 1127An SP execution context in a call chain could specify a less permissive action 1128than subsequent SP execution contexts in the same call chain. The less 1129permissive action takes precedence over the more permissive actions specified 1130by the subsequent execution contexts. Please refer to FF-A v1.1 EAC0 section 11318.3.1 for further explanation. 1132 1133Secure interrupt handling 1134~~~~~~~~~~~~~~~~~~~~~~~~~ 1135 1136This section documents the support implemented for secure interrupt handling in 1137SPMC as per the guidance provided by FF-A v1.1 EAC0 specification. 1138The following assumptions are made about the system configuration: 1139 1140 - In the current implementation, S-EL1 SPs are expected to use the para 1141 virtualized ABIs for interrupt management rather than accessing the virtual 1142 GIC interface. 1143 - Unless explicitly stated otherwise, this support is applicable only for 1144 S-EL1 SPs managed by SPMC. 1145 - Secure interrupts are configured as G1S or G0 interrupts. 1146 - All physical interrupts are routed to SPMC when running a secure partition 1147 execution context. 1148 - All endpoints with multiple execution contexts have their contexts pinned 1149 to corresponding CPUs. Hence, a secure virtual interrupt cannot be signaled 1150 to a target vCPU that is currently running or blocked on a different 1151 physical CPU. 1152 1153A physical secure interrupt could trigger while CPU is executing in normal world 1154or secure world. 1155The action of SPMC for a secure interrupt depends on: the state of the target 1156execution context of the SP that is responsible for handling the interrupt; 1157whether the interrupt triggered while execution was in normal world or secure 1158world. 1159 1160Secure interrupt signaling mechanisms 1161~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1162 1163Signaling refers to the mechanisms used by SPMC to indicate to the SP execution 1164context that it has a pending virtual interrupt and to further run the SP 1165execution context, such that it can handle the virtual interrupt. SPMC uses 1166either the FFA_INTERRUPT interface with ERET conduit or vIRQ signal for signaling 1167to S-EL1 SPs. When normal world execution is preempted by a secure interrupt, 1168the SPMD uses the FFA_INTERRUPT ABI with ERET conduit to signal interrupt to SPMC 1169running in S-EL2. 1170 1171+-----------+---------+---------------+---------------------------------------+ 1172| SP State | Conduit | Interface and | Description | 1173| | | parameters | | 1174+-----------+---------+---------------+---------------------------------------+ 1175| WAITING | ERET, | FFA_INTERRUPT,| SPMC signals to SP the ID of pending | 1176| | vIRQ | Interrupt ID | interrupt. It pends vIRQ signal and | 1177| | | | resumes execution context of SP | 1178| | | | through ERET. | 1179+-----------+---------+---------------+---------------------------------------+ 1180| BLOCKED | ERET, | FFA_INTERRUPT | SPMC signals to SP that an interrupt | 1181| | vIRQ | | is pending. It pends vIRQ signal and | 1182| | | | resumes execution context of SP | 1183| | | | through ERET. | 1184+-----------+---------+---------------+---------------------------------------+ 1185| PREEMPTED | vIRQ | NA | SPMC pends the vIRQ signal but does | 1186| | | | not resume execution context of SP. | 1187+-----------+---------+---------------+---------------------------------------+ 1188| RUNNING | ERET, | NA | SPMC pends the vIRQ signal and resumes| 1189| | vIRQ | | execution context of SP through ERET. | 1190+-----------+---------+---------------+---------------------------------------+ 1191 1192Secure interrupt completion mechanisms 1193~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1194 1195A SP signals secure interrupt handling completion to the SPMC through the 1196following mechanisms: 1197 1198 - ``FFA_MSG_WAIT`` ABI if it was in WAITING state. 1199 - ``FFA_RUN`` ABI if its was in BLOCKED state. 1200 1201This is a remnant of SPMC implementation based on the FF-A v1.0 specification. 1202In the current implementation, S-EL1 SPs use the para-virtualized HVC interface 1203implemented by SPMC to perform priority drop and interrupt deactivation (SPMC 1204configures EOImode = 0, i.e. priority drop and deactivation are done together). 1205The SPMC performs checks to deny the state transition upon invocation of 1206either FFA_MSG_WAIT or FFA_RUN interface if the SP didn't perform the 1207deactivation of the secure virtual interrupt. 1208 1209If the current SP execution context was preempted by a secure interrupt to be 1210handled by execution context of target SP, SPMC resumes current SP after signal 1211completion by target SP execution context. 1212 1213Actions for a secure interrupt triggered while execution is in normal world 1214~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1215 1216+-------------------+----------+-----------------------------------------------+ 1217| State of target | Action | Description | 1218| execution context | | | 1219+-------------------+----------+-----------------------------------------------+ 1220| WAITING | Signaled | This starts a new call chain in SPMC scheduled| 1221| | | mode. | 1222+-------------------+----------+-----------------------------------------------+ 1223| PREEMPTED | Queued | The target execution must have been preempted | 1224| | | by a non-secure interrupt. SPMC queues the | 1225| | | secure virtual interrupt now. It is signaled | 1226| | | when the target execution context next enters | 1227| | | the RUNNING state. | 1228+-------------------+----------+-----------------------------------------------+ 1229| BLOCKED, RUNNING | NA | The target execution context is blocked or | 1230| | | running on a different CPU. This is not | 1231| | | supported by current SPMC implementation and | 1232| | | execution hits panic. | 1233+-------------------+----------+-----------------------------------------------+ 1234 1235If normal world execution was preempted by a secure interrupt, SPMC uses 1236FFA_NORMAL_WORLD_RESUME ABI to indicate completion of secure interrupt handling 1237and further returns execution to normal world. 1238 1239The following figure describes interrupt handling flow when a secure interrupt 1240triggers while execution is in normal world: 1241 1242.. image:: ../resources/diagrams/ffa-secure-interrupt-handling-nwd.png 1243 1244A brief description of the events: 1245 1246 - 1) Secure interrupt triggers while normal world is running. 1247 - 2) FIQ gets trapped to EL3. 1248 - 3) SPMD signals secure interrupt to SPMC at S-EL2 using FFA_INTERRUPT ABI. 1249 - 4) SPMC identifies target vCPU of SP and injects virtual interrupt (pends 1250 vIRQ). 1251 - 5) Assuming SP1 vCPU is in WAITING state, SPMC signals virtual interrupt 1252 using FFA_INTERRUPT with interrupt id as an argument and resumes the SP1 1253 vCPU using ERET in SPMC scheduled mode. 1254 - 6) Execution traps to vIRQ handler in SP1 provided that the virtual 1255 interrupt is not masked i.e., PSTATE.I = 0 1256 - 7) SP1 queries for the pending virtual interrupt id using a paravirtualized 1257 HVC call. SPMC clears the pending virtual interrupt state management 1258 and returns the pending virtual interrupt id. 1259 - 8) SP1 services the virtual interrupt and invokes the paravirtualized 1260 de-activation HVC call. SPMC de-activates the physical interrupt, 1261 clears the fields tracking the secure interrupt and resumes SP1 vCPU. 1262 - 9) SP1 performs secure interrupt completion through FFA_MSG_WAIT ABI. 1263 - 10) SPMC returns control to EL3 using FFA_NORMAL_WORLD_RESUME. 1264 - 11) EL3 resumes normal world execution. 1265 1266Actions for a secure interrupt triggered while execution is in secure world 1267~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1268 1269+-------------------+----------+------------------------------------------------+ 1270| State of target | Action | Description | 1271| execution context | | | 1272+-------------------+----------+------------------------------------------------+ 1273| WAITING | Signaled | This starts a new call chain in SPMC scheduled | 1274| | | mode. | 1275+-------------------+----------+------------------------------------------------+ 1276| PREEMPTED by Self | Signaled | The target execution context reenters the | 1277| S-Int | | RUNNING state to handle the secure virtual | 1278| | | interrupt. | 1279+-------------------+----------+------------------------------------------------+ 1280| PREEMPTED by | Queued | SPMC queues the secure virtual interrupt now. | 1281| NS-Int | | It is signaled when the target execution | 1282| | | context next enters the RUNNING state. | 1283+-------------------+----------+------------------------------------------------+ 1284| BLOCKED | Signaled | Both preempted and target execution contexts | 1285| | | must have been part of the Normal world | 1286| | | scheduled call chain. Refer scenario 1 of | 1287| | | Table 8.4 in the FF-A v1.1 EAC0 spec. | 1288+-------------------+----------+------------------------------------------------+ 1289| RUNNING | NA | The target execution context is running on a | 1290| | | different CPU. This scenario is not supported | 1291| | | by current SPMC implementation and execution | 1292| | | hits panic. | 1293+-------------------+----------+------------------------------------------------+ 1294 1295The following figure describes interrupt handling flow when a secure interrupt 1296triggers while execution is in secure world. We assume OS kernel sends a direct 1297request message to SP1. Further, SP1 sends a direct request message to SP2. SP1 1298enters BLOCKED state and SPMC resumes SP2. 1299 1300.. image:: ../resources/diagrams/ffa-secure-interrupt-handling-swd.png 1301 1302A brief description of the events: 1303 1304 - 1) Secure interrupt triggers while SP2 is running. 1305 - 2) SP2 gets preempted and execution traps to SPMC as IRQ. 1306 - 3) SPMC finds the target vCPU of secure partition responsible for handling 1307 this secure interrupt. In this scenario, it is SP1. 1308 - 4) SPMC pends vIRQ for SP1 and signals through FFA_INTERRUPT interface. 1309 SPMC further resumes SP1 through ERET conduit. Note that SP1 remains in 1310 Normal world schedule mode. 1311 - 6) Execution traps to vIRQ handler in SP1 provided that the virtual 1312 interrupt is not masked i.e., PSTATE.I = 0 1313 - 7) SP1 queries for the pending virtual interrupt id using a paravirtualized 1314 HVC call. SPMC clears the pending virtual interrupt state management 1315 and returns the pending virtual interrupt id. 1316 - 8) SP1 services the virtual interrupt and invokes the paravirtualized 1317 de-activation HVC call. SPMC de-activates the physical interrupt and 1318 clears the fields tracking the secure interrupt and resumes SP1 vCPU. 1319 - 9) Since SP1 direct request completed with FFA_INTERRUPT, it resumes the 1320 direct request to SP2 by invoking FFA_RUN. 1321 - 9) SPMC resumes the pre-empted vCPU of SP2. 1322 1323Power management 1324---------------- 1325 1326In platforms with or without secure virtualization: 1327 1328- The NWd owns the platform PM policy. 1329- The Hypervisor or OS kernel is the component initiating PSCI service calls. 1330- The EL3 PSCI library is in charge of the PM coordination and control 1331 (eventually writing to platform registers). 1332- While coordinating PM events, the PSCI library calls backs into the Secure 1333 Payload Dispatcher for events the latter has statically registered to. 1334 1335When using the SPMD as a Secure Payload Dispatcher: 1336 1337- A power management event is relayed through the SPD hook to the SPMC. 1338- In the current implementation only cpu on (svc_on_finish) and cpu off 1339 (svc_off) hooks are registered. 1340- The behavior for the cpu on event is described in `Secondary cores boot-up`_. 1341 The SPMC is entered through its secondary physical core entry point. 1342- The cpu off event occurs when the NWd calls PSCI_CPU_OFF. The PM event is 1343 signaled to the SPMC through a power management framework message. 1344 It consists in a SPMD-to-SPMC direct request/response (`SPMC-SPMD direct 1345 requests/responses`_) conveying the event details and SPMC response. 1346 The SPMD performs a synchronous entry into the SPMC. The SPMC is entered and 1347 updates its internal state to reflect the physical core is being turned off. 1348 In the current implementation no SP is resumed as a consequence. This behavior 1349 ensures a minimal support for CPU hotplug e.g. when initiated by the NWd linux 1350 userspace. 1351 1352Arm architecture extensions for security hardening 1353================================================== 1354 1355Hafnium supports the following architecture extensions for security hardening: 1356 1357- Pointer authentication (FEAT_PAuth): the extension permits detection of forged 1358 pointers used by ROP type of attacks through the signing of the pointer 1359 value. Hafnium is built with the compiler branch protection option to permit 1360 generation of a pointer authentication code for return addresses (pointer 1361 authentication for instructions). The APIA key is used while Hafnium runs. 1362 A random key is generated at boot time and restored upon entry into Hafnium 1363 at run-time. APIA and other keys (APIB, APDA, APDB, APGA) are saved/restored 1364 in vCPU contexts permitting to enable pointer authentication in VMs/SPs. 1365- Branch Target Identification (FEAT_BTI): the extension permits detection of 1366 unexpected indirect branches used by JOP type of attacks. Hafnium is built 1367 with the compiler branch protection option, inserting land pads at function 1368 prologues that are reached by indirect branch instructions (BR/BLR). 1369 Hafnium code pages are marked as guarded in the EL2 Stage-1 MMU descriptors 1370 such that an indirect branch must always target a landpad. A fault is 1371 triggered otherwise. VMs/SPs can (independently) mark their code pages as 1372 guarded in the EL1&0 Stage-1 translation regime. 1373- Memory Tagging Extension (FEAT_MTE): the option permits detection of out of 1374 bound memory array accesses or re-use of an already freed memory region. 1375 Hafnium enables the compiler option permitting to leverage MTE stack tagging 1376 applied to core stacks. Core stacks are marked as normal tagged memory in the 1377 EL2 Stage-1 translation regime. A synchronous data abort is generated upon tag 1378 check failure on load/stores. A random seed is generated at boot time and 1379 restored upon entry into Hafnium. MTE system registers are saved/restored in 1380 vCPU contexts permitting MTE usage from VMs/SPs. 1381 1382SMMUv3 support in Hafnium 1383========================= 1384 1385An SMMU is analogous to an MMU in a CPU. It performs address translations for 1386Direct Memory Access (DMA) requests from system I/O devices. 1387The responsibilities of an SMMU include: 1388 1389- Translation: Incoming DMA requests are translated from bus address space to 1390 system physical address space using translation tables compliant to 1391 Armv8/Armv7 VMSA descriptor format. 1392- Protection: An I/O device can be prohibited from read, write access to a 1393 memory region or allowed. 1394- Isolation: Traffic from each individial device can be independently managed. 1395 The devices are differentiated from each other using unique translation 1396 tables. 1397 1398The following diagram illustrates a typical SMMU IP integrated in a SoC with 1399several I/O devices along with Interconnect and Memory system. 1400 1401.. image:: ../resources/diagrams/MMU-600.png 1402 1403SMMU has several versions including SMMUv1, SMMUv2 and SMMUv3. Hafnium provides 1404support for SMMUv3 driver in both normal and secure world. A brief introduction 1405of SMMUv3 functionality and the corresponding software support in Hafnium is 1406provided here. 1407 1408SMMUv3 features 1409--------------- 1410 1411- SMMUv3 provides Stage1, Stage2 translation as well as nested (Stage1 + Stage2) 1412 translation support. It can either bypass or abort incoming translations as 1413 well. 1414- Traffic (memory transactions) from each upstream I/O peripheral device, 1415 referred to as Stream, can be independently managed using a combination of 1416 several memory based configuration structures. This allows the SMMUv3 to 1417 support a large number of streams with each stream assigned to a unique 1418 translation context. 1419- Support for Armv8.1 VMSA where the SMMU shares the translation tables with 1420 a Processing Element. AArch32(LPAE) and AArch64 translation table format 1421 are supported by SMMUv3. 1422- SMMUv3 offers non-secure stream support with secure stream support being 1423 optional. Logically, SMMUv3 behaves as if there is an indepdendent SMMU 1424 instance for secure and non-secure stream support. 1425- It also supports sub-streams to differentiate traffic from a virtualized 1426 peripheral associated with a VM/SP. 1427- Additionally, SMMUv3.2 provides support for PEs implementing Armv8.4-A 1428 extensions. Consequently, SPM depends on Secure EL2 support in SMMUv3.2 1429 for providing Secure Stage2 translation support to upstream peripheral 1430 devices. 1431 1432SMMUv3 Programming Interfaces 1433----------------------------- 1434 1435SMMUv3 has three software interfaces that are used by the Hafnium driver to 1436configure the behaviour of SMMUv3 and manage the streams. 1437 1438- Memory based data strutures that provide unique translation context for 1439 each stream. 1440- Memory based circular buffers for command queue and event queue. 1441- A large number of SMMU configuration registers that are memory mapped during 1442 boot time by Hafnium driver. Except a few registers, all configuration 1443 registers have independent secure and non-secure versions to configure the 1444 behaviour of SMMUv3 for translation of secure and non-secure streams 1445 respectively. 1446 1447Peripheral device manifest 1448-------------------------- 1449 1450Currently, SMMUv3 driver in Hafnium only supports dependent peripheral devices. 1451These devices are dependent on PE endpoint to initiate and receive memory 1452management transactions on their behalf. The acccess to the MMIO regions of 1453any such device is assigned to the endpoint during boot. Moreover, SMMUv3 driver 1454uses the same stage 2 translations for the device as those used by partition 1455manager on behalf of the PE endpoint. This ensures that the peripheral device 1456has the same visibility of the physical address space as the endpoint. The 1457device node of the corresponding partition manifest (refer to `[1]`_ section 3.2 1458) must specify these additional properties for each peripheral device in the 1459system : 1460 1461- smmu-id: This field helps to identify the SMMU instance that this device is 1462 upstream of. 1463- stream-ids: List of stream IDs assigned to this device. 1464 1465.. code:: shell 1466 1467 smmuv3-testengine { 1468 base-address = <0x00000000 0x2bfe0000>; 1469 pages-count = <32>; 1470 attributes = <0x3>; 1471 smmu-id = <0>; 1472 stream-ids = <0x0 0x1>; 1473 interrupts = <0x2 0x3>, <0x4 0x5>; 1474 exclusive-access; 1475 }; 1476 1477SMMUv3 driver limitations 1478------------------------- 1479 1480The primary design goal for the Hafnium SMMU driver is to support secure 1481streams. 1482 1483- Currently, the driver only supports Stage2 translations. No support for 1484 Stage1 or nested translations. 1485- Supports only AArch64 translation format. 1486- No support for features such as PCI Express (PASIDs, ATS, PRI), MSI, RAS, 1487 Fault handling, Performance Monitor Extensions, Event Handling, MPAM. 1488- No support for independent peripheral devices. 1489 1490S-EL0 Partition support 1491======================= 1492The SPMC (Hafnium) has limited capability to run S-EL0 FF-A partitions using 1493FEAT_VHE (mandatory with ARMv8.1 in non-secure state, and in secure world 1494with ARMv8.4 and FEAT_SEL2). 1495 1496S-EL0 partitions are useful for simple partitions that don't require full 1497Trusted OS functionality. It is also useful to reduce jitter and cycle 1498stealing from normal world since they are more lightweight than VMs. 1499 1500S-EL0 partitions are presented, loaded and initialized the same as S-EL1 VMs by 1501the SPMC. They are differentiated primarily by the 'exception-level' property 1502and the 'execution-ctx-count' property in the SP manifest. They are host apps 1503under the single EL2&0 Stage-1 translation regime controlled by the SPMC and 1504call into the SPMC through SVCs as opposed to HVCs and SMCs. These partitions 1505can use FF-A defined services (FFA_MEM_PERM_*) to update or change permissions 1506for memory regions. 1507 1508S-EL0 partitions are required by the FF-A specification to be UP endpoints, 1509capable of migrating, and the SPMC enforces this requirement. The SPMC allows 1510a S-EL0 partition to accept a direct message from secure world and normal world, 1511and generate direct responses to them. 1512All S-EL0 partitions must use AArch64. AArch32 S-EL0 partitions are not supported. 1513 1514Memory sharing, indirect messaging, and notifications functionality with S-EL0 1515partitions is supported. 1516 1517Interrupt handling is not supported with S-EL0 partitions and is work in 1518progress. 1519 1520References 1521========== 1522 1523.. _[1]: 1524 1525[1] `Arm Firmware Framework for Arm A-profile <https://developer.arm.com/docs/den0077/latest>`__ 1526 1527.. _[2]: 1528 1529[2] :ref:`Secure Partition Manager using MM interface<Secure Partition Manager (MM)>` 1530 1531.. _[3]: 1532 1533[3] `Trusted Boot Board Requirements 1534Client <https://developer.arm.com/documentation/den0006/d/>`__ 1535 1536.. _[4]: 1537 1538[4] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/el3_runtime/aarch64/context.S#n45 1539 1540.. _[5]: 1541 1542[5] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/spm/cactus/plat/arm/fvp/fdts/cactus.dts 1543 1544.. _[6]: 1545 1546[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html 1547 1548.. _[7]: 1549 1550[7] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts 1551 1552.. _[8]: 1553 1554[8] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/CFQFGU6H2D5GZYMUYGTGUSXIU3OYZP6U/ 1555 1556.. _[9]: 1557 1558[9] https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#dynamic-configuration-during-cold-boot 1559 1560-------------- 1561 1562*Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.* 1563
