1Secure Partition Manager 2************************ 3 4.. contents:: 5 6.. toctree:: 7 ffa-manifest-binding 8 9Acronyms 10======== 11 12+--------+--------------------------------------+ 13| CoT | Chain of Trust | 14+--------+--------------------------------------+ 15| DMA | Direct Memory Access | 16+--------+--------------------------------------+ 17| DTB | Device Tree Blob | 18+--------+--------------------------------------+ 19| DTS | Device Tree Source | 20+--------+--------------------------------------+ 21| EC | Execution Context | 22+--------+--------------------------------------+ 23| FIP | Firmware Image Package | 24+--------+--------------------------------------+ 25| FF-A | Firmware Framework for Arm A-profile | 26+--------+--------------------------------------+ 27| IPA | Intermediate Physical Address | 28+--------+--------------------------------------+ 29| JOP | Jump-Oriented Programming | 30+--------+--------------------------------------+ 31| NWd | Normal World | 32+--------+--------------------------------------+ 33| ODM | Original Design Manufacturer | 34+--------+--------------------------------------+ 35| OEM | Original Equipment Manufacturer | 36+--------+--------------------------------------+ 37| PA | Physical Address | 38+--------+--------------------------------------+ 39| PE | Processing Element | 40+--------+--------------------------------------+ 41| PM | Power Management | 42+--------+--------------------------------------+ 43| PVM | Primary VM | 44+--------+--------------------------------------+ 45| ROP | Return-Oriented Programming | 46+--------+--------------------------------------+ 47| SMMU | System Memory Management Unit | 48+--------+--------------------------------------+ 49| SP | Secure Partition | 50+--------+--------------------------------------+ 51| SPD | Secure Payload Dispatcher | 52+--------+--------------------------------------+ 53| SPM | Secure Partition Manager | 54+--------+--------------------------------------+ 55| SPMC | SPM Core | 56+--------+--------------------------------------+ 57| SPMD | SPM Dispatcher | 58+--------+--------------------------------------+ 59| SiP | Silicon Provider | 60+--------+--------------------------------------+ 61| SWd | Secure World | 62+--------+--------------------------------------+ 63| TLV | Tag-Length-Value | 64+--------+--------------------------------------+ 65| TOS | Trusted Operating System | 66+--------+--------------------------------------+ 67| VM | Virtual Machine | 68+--------+--------------------------------------+ 69 70Foreword 71======== 72 73Three implementations of a Secure Partition Manager co-exist in the TF-A 74codebase: 75 76#. S-EL2 SPMC based on the FF-A specification `[1]`_, enabling virtualization in 77 the secure world, managing multiple S-EL1 or S-EL0 partitions. 78#. EL3 SPMC based on the FF-A specification, managing a single S-EL1 partition 79 without virtualization in the secure world. 80#. EL3 SPM based on the MM specification, legacy implementation managing a 81 single S-EL0 partition `[2]`_. 82 83These implementations differ in their respective SW architecture and only one 84can be selected at build time. This document: 85 86- describes the implementation from bullet 1. when the SPMC resides at S-EL2. 87- is not an architecture specification and it might provide assumptions 88 on sections mandated as implementation-defined in the specification. 89- covers the implications to TF-A used as a bootloader, and Hafnium used as a 90 reference code base for an S-EL2/SPMC secure firmware on platforms 91 implementing the FEAT_SEL2 architecture extension. 92 93Terminology 94----------- 95 96- The term Hypervisor refers to the NS-EL2 component managing Virtual Machines 97 (or partitions) in the normal world. 98- The term SPMC refers to the S-EL2 component managing secure partitions in 99 the secure world when the FEAT_SEL2 architecture extension is implemented. 100- Alternatively, SPMC can refer to an S-EL1 component, itself being a secure 101 partition and implementing the FF-A ABI on platforms not implementing the 102 FEAT_SEL2 architecture extension. 103- The term VM refers to a normal world Virtual Machine managed by an Hypervisor. 104- The term SP refers to a secure world "Virtual Machine" managed by an SPMC. 105 106Support for legacy platforms 107---------------------------- 108 109The SPM is split into a dispatcher and a core component (respectively SPMD and 110SPMC) residing at different exception levels. To permit the FF-A specification 111adoption and a smooth migration, the SPMD supports an SPMC residing either at 112S-EL1 or S-EL2: 113 114- The SPMD is located at EL3 and mainly relays the FF-A protocol from NWd 115 (Hypervisor or OS kernel) to the SPMC. 116- The same SPMD component is used for both S-EL1 and S-EL2 SPMC configurations. 117- The SPMC exception level is a build time choice. 118 119TF-A supports both cases: 120 121- S-EL1 SPMC for platforms not supporting the FEAT_SEL2 architecture 122 extension. The SPMD relays the FF-A protocol from EL3 to S-EL1. 123- S-EL2 SPMC for platforms implementing the FEAT_SEL2 architecture 124 extension. The SPMD relays the FF-A protocol from EL3 to S-EL2. 125 126Sample reference stack 127====================== 128 129The following diagram illustrates a possible configuration when the 130FEAT_SEL2 architecture extension is implemented, showing the SPMD 131and SPMC, one or multiple secure partitions, with an optional 132Hypervisor: 133 134.. image:: ../resources/diagrams/ff-a-spm-sel2.png 135 136TF-A build options 137================== 138 139This section explains the TF-A build options involved in building with 140support for an FF-A based SPM where the SPMD is located at EL3 and the 141SPMC located at S-EL1, S-EL2 or EL3: 142 143- **SPD=spmd**: this option selects the SPMD component to relay the FF-A 144 protocol from NWd to SWd back and forth. It is not possible to 145 enable another Secure Payload Dispatcher when this option is chosen. 146- **SPMD_SPM_AT_SEL2**: this option adjusts the SPMC exception 147 level to being at S-EL2. It defaults to enabled (value 1) when 148 SPD=spmd is chosen. 149- **SPMC_AT_EL3**: this option adjusts the SPMC exception level to being 150 at EL3. 151- If neither ``SPMD_SPM_AT_SEL2`` or ``SPMC_AT_EL3`` are enabled the SPMC 152 exception level is set to S-EL1. 153 ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine 154 and exhaustive list of registers is visible at `[4]`_. 155- **SP_LAYOUT_FILE**: this option specifies a text description file 156 providing paths to SP binary images and manifests in DTS format 157 (see `Describing secure partitions`_). It 158 is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple 159 secure partitions are to be loaded by BL2 on behalf of the SPMC. 160 161+---------------+------------------+-------------+-------------------------+ 162| | SPMD_SPM_AT_SEL2 | SPMC_AT_EL3 | CTX_INCLUDE_EL2_REGS(*) | 163+---------------+------------------+-------------+-------------------------+ 164| SPMC at S-EL1 | 0 | 0 | 0 | 165+---------------+------------------+-------------+-------------------------+ 166| SPMC at S-EL2 | 1 (default when | 0 | 1 | 167| | SPD=spmd) | | | 168+---------------+------------------+-------------+-------------------------+ 169| SPMC at EL3 | 0 | 1 | 0 | 170+---------------+------------------+-------------+-------------------------+ 171 172Other combinations of such build options either break the build or are not 173supported. 174 175Notes: 176 177- Only Arm's FVP platform is supported to use with the TF-A reference software 178 stack. 179- When ``SPMD_SPM_AT_SEL2=1``, the reference software stack assumes enablement 180 of FEAT_PAuth, FEAT_BTI and FEAT_MTE architecture extensions. 181- ``(*) CTX_INCLUDE_EL2_REGS``, this flag is |TF-A| internal and informational 182 in this table. When set, it provides the generic support for saving/restoring 183 EL2 registers required when S-EL2 firmware is present. 184- BL32 option is re-purposed to specify the SPMC image. It can specify either 185 the Hafnium binary path (built for the secure world) or the path to a TEE 186 binary implementing FF-A interfaces. 187- BL33 option can specify the TFTF binary or a normal world loader 188 such as U-Boot or the UEFI framework payload. 189 190Sample TF-A build command line when the SPMC is located at S-EL1 191(e.g. when the FEAT_SEL2 architecture extension is not implemented): 192 193.. code:: shell 194 195 make \ 196 CROSS_COMPILE=aarch64-none-elf- \ 197 SPD=spmd \ 198 SPMD_SPM_AT_SEL2=0 \ 199 BL32=<path-to-tee-binary> \ 200 BL33=<path-to-bl33-binary> \ 201 PLAT=fvp \ 202 all fip 203 204Sample TF-A build command line when FEAT_SEL2 architecture extension is 205implemented and the SPMC is located at S-EL2: 206.. code:: shell 207 208 make \ 209 CROSS_COMPILE=aarch64-none-elf- \ 210 PLAT=fvp \ 211 SPD=spmd \ 212 ARM_ARCH_MINOR=5 \ 213 BRANCH_PROTECTION=1 \ 214 CTX_INCLUDE_PAUTH_REGS=1 \ 215 CTX_INCLUDE_MTE_REGS=1 \ 216 BL32=<path-to-hafnium-binary> \ 217 BL33=<path-to-bl33-binary> \ 218 SP_LAYOUT_FILE=sp_layout.json \ 219 all fip 220 221Sample TF-A build command line when FEAT_SEL2 architecture extension is 222implemented, the SPMC is located at S-EL2, and enabling secure boot: 223.. code:: shell 224 225 make \ 226 CROSS_COMPILE=aarch64-none-elf- \ 227 PLAT=fvp \ 228 SPD=spmd \ 229 ARM_ARCH_MINOR=5 \ 230 BRANCH_PROTECTION=1 \ 231 CTX_INCLUDE_PAUTH_REGS=1 \ 232 CTX_INCLUDE_MTE_REGS=1 \ 233 BL32=<path-to-hafnium-binary> \ 234 BL33=<path-to-bl33-binary> \ 235 SP_LAYOUT_FILE=sp_layout.json \ 236 MBEDTLS_DIR=<path-to-mbedtls-lib> \ 237 TRUSTED_BOARD_BOOT=1 \ 238 COT=dualroot \ 239 ARM_ROTPK_LOCATION=devel_rsa \ 240 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ 241 GENERATE_COT=1 \ 242 all fip 243 244Sample TF-A build command line when the SPMC is located at EL3: 245 246.. code:: shell 247 248 make \ 249 CROSS_COMPILE=aarch64-none-elf- \ 250 SPD=spmd \ 251 SPMD_SPM_AT_SEL2=0 \ 252 SPMC_AT_EL3=1 \ 253 BL32=<path-to-tee-binary> \ 254 BL33=<path-to-bl33-binary> \ 255 PLAT=fvp \ 256 all fip 257 258FVP model invocation 259==================== 260 261The FVP command line needs the following options to exercise the S-EL2 SPMC: 262 263+---------------------------------------------------+------------------------------------+ 264| - cluster0.has_arm_v8-5=1 | Implements FEAT_SEL2, FEAT_PAuth, | 265| - cluster1.has_arm_v8-5=1 | and FEAT_BTI. | 266+---------------------------------------------------+------------------------------------+ 267| - pci.pci_smmuv3.mmu.SMMU_AIDR=2 | Parameters required for the | 268| - pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B | SMMUv3.2 modeling. | 269| - pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 | | 270| - pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 | | 271| - pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 | | 272| - pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 | | 273| - pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 | | 274| - pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 | | 275+---------------------------------------------------+------------------------------------+ 276| - cluster0.has_branch_target_exception=1 | Implements FEAT_BTI. | 277| - cluster1.has_branch_target_exception=1 | | 278+---------------------------------------------------+------------------------------------+ 279| - cluster0.has_pointer_authentication=2 | Implements FEAT_PAuth | 280| - cluster1.has_pointer_authentication=2 | | 281+---------------------------------------------------+------------------------------------+ 282| - cluster0.memory_tagging_support_level=2 | Implements FEAT_MTE2 | 283| - cluster1.memory_tagging_support_level=2 | | 284| - bp.dram_metadata.is_enabled=1 | | 285+---------------------------------------------------+------------------------------------+ 286 287Sample FVP command line invocation: 288 289.. code:: shell 290 291 <path-to-fvp-model>/FVP_Base_RevC-2xAEMvA -C pctl.startup=0.0.0.0 \ 292 -C cluster0.NUM_CORES=4 -C cluster1.NUM_CORES=4 -C bp.secure_memory=1 \ 293 -C bp.secureflashloader.fname=trusted-firmware-a/build/fvp/debug/bl1.bin \ 294 -C bp.flashloader0.fname=trusted-firmware-a/build/fvp/debug/fip.bin \ 295 -C bp.pl011_uart0.out_file=fvp-uart0.log -C bp.pl011_uart1.out_file=fvp-uart1.log \ 296 -C bp.pl011_uart2.out_file=fvp-uart2.log \ 297 -C cluster0.has_arm_v8-5=1 -C cluster1.has_arm_v8-5=1 \ 298 -C cluster0.has_pointer_authentication=2 -C cluster1.has_pointer_authentication=2 \ 299 -C cluster0.has_branch_target_exception=1 -C cluster1.has_branch_target_exception=1 \ 300 -C cluster0.memory_tagging_support_level=2 -C cluster1.memory_tagging_support_level=2 \ 301 -C bp.dram_metadata.is_enabled=1 \ 302 -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B \ 303 -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 \ 304 -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 \ 305 -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 306 307Boot process 308============ 309 310Loading Hafnium and secure partitions in the secure world 311--------------------------------------------------------- 312 313TF-A BL2 is the bootlader for the SPMC and SPs in the secure world. 314 315SPs may be signed by different parties (SiP, OEM/ODM, TOS vendor, etc.). 316Thus they are supplied as distinct signed entities within the FIP flash 317image. The FIP image itself is not signed hence this provides the ability 318to upgrade SPs in the field. 319 320Booting through TF-A 321-------------------- 322 323SP manifests 324~~~~~~~~~~~~ 325 326An SP manifest describes SP attributes as defined in `[1]`_ 327(partition manifest at virtual FF-A instance) in DTS format. It is 328represented as a single file associated with the SP. A sample is 329provided by `[5]`_. A binding document is provided by `[6]`_. 330 331Secure Partition packages 332~~~~~~~~~~~~~~~~~~~~~~~~~ 333 334Secure partitions are bundled as independent package files consisting 335of: 336 337- a header 338- a DTB 339- an image payload 340 341The header starts with a magic value and offset values to SP DTB and 342image payload. Each SP package is loaded independently by BL2 loader 343and verified for authenticity and integrity. 344 345The SP package identified by its UUID (matching FF-A uuid property) is 346inserted as a single entry into the FIP at end of the TF-A build flow 347as shown: 348 349.. code:: shell 350 351 Trusted Boot Firmware BL2: offset=0x1F0, size=0x8AE1, cmdline="--tb-fw" 352 EL3 Runtime Firmware BL31: offset=0x8CD1, size=0x13000, cmdline="--soc-fw" 353 Secure Payload BL32 (Trusted OS): offset=0x1BCD1, size=0x15270, cmdline="--tos-fw" 354 Non-Trusted Firmware BL33: offset=0x30F41, size=0x92E0, cmdline="--nt-fw" 355 HW_CONFIG: offset=0x3A221, size=0x2348, cmdline="--hw-config" 356 TB_FW_CONFIG: offset=0x3C569, size=0x37A, cmdline="--tb-fw-config" 357 SOC_FW_CONFIG: offset=0x3C8E3, size=0x48, cmdline="--soc-fw-config" 358 TOS_FW_CONFIG: offset=0x3C92B, size=0x427, cmdline="--tos-fw-config" 359 NT_FW_CONFIG: offset=0x3CD52, size=0x48, cmdline="--nt-fw-config" 360 B4B5671E-4A90-4FE1-B81F-FB13DAE1DACB: offset=0x3CD9A, size=0xC168, cmdline="--blob" 361 D1582309-F023-47B9-827C-4464F5578FC8: offset=0x48F02, size=0xC168, cmdline="--blob" 362 363.. uml:: ../resources/diagrams/plantuml/fip-secure-partitions.puml 364 365Describing secure partitions 366~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 367 368A json-formatted description file is passed to the build flow specifying paths 369to the SP binary image and associated DTS partition manifest file. The latter 370is processed by the dtc compiler to generate a DTB fed into the SP package. 371Optionally, the partition's json description can contain offsets for both 372the image and partition manifest within the SP package. Both offsets need to be 3734KB aligned, because it is the translation granule supported by Hafnium SPMC. 374These fields can be leveraged to support SPs with S1 translation granules that 375differ from 4KB, and to configure the regions allocated within the SP package, 376as well as to comply with the requirements for the implementation of the boot 377information protocol (see `Passing boot data to the SP`_ for more details). In 378case the offsets are absent in their json node, they default to 0x1000 and 3790x4000 for the manifest offset and image offset respectively. 380This file also specifies the SP owner (as an optional field) identifying the 381signing domain in case of dual root CoT. 382The SP owner can either be the silicon or the platform provider. The 383corresponding "owner" field value can either take the value of "SiP" or "Plat". 384In absence of "owner" field, it defaults to "SiP" owner. 385The UUID of the partition can be specified as a field in the description file or 386if it does not exist there the UUID is extracted from the DTS partition 387manifest. 388 389.. code:: shell 390 391 { 392 "tee1" : { 393 "image": "tee1.bin", 394 "pm": "tee1.dts", 395 "owner": "SiP", 396 "uuid": "1b1820fe-48f7-4175-8999-d51da00b7c9f" 397 }, 398 399 "tee2" : { 400 "image": "tee2.bin", 401 "pm": "tee2.dts", 402 "owner": "Plat" 403 }, 404 405 "tee3" : { 406 "image": { 407 "file": "tee3.bin", 408 "offset":"0x2000" 409 }, 410 "pm": { 411 "file": "tee3.dts", 412 "offset":"0x6000" 413 }, 414 "owner": "Plat" 415 }, 416 } 417 418SPMC manifest 419~~~~~~~~~~~~~ 420 421This manifest contains the SPMC *attribute* node consumed by the SPMD at boot 422time. It implements `[1]`_ (SP manifest at physical FF-A instance) and serves 423two different cases: 424 425- The SPMC resides at S-EL1: the SPMC manifest is used by the SPMD to setup a 426 SP that co-resides with the SPMC and executes at S-EL1 or Secure Supervisor 427 mode. 428- The SPMC resides at S-EL2: the SPMC manifest is used by the SPMD to setup 429 the environment required by the SPMC to run at S-EL2. SPs run at S-EL1 or 430 S-EL0. 431 432.. code:: shell 433 434 attribute { 435 spmc_id = <0x8000>; 436 maj_ver = <0x1>; 437 min_ver = <0x1>; 438 exec_state = <0x0>; 439 load_address = <0x0 0x6000000>; 440 entrypoint = <0x0 0x6000000>; 441 binary_size = <0x60000>; 442 }; 443 444- *spmc_id* defines the endpoint ID value that SPMC can query through 445 ``FFA_ID_GET``. 446- *maj_ver/min_ver*. SPMD checks provided version versus its internal 447 version and aborts if not matching. 448- *exec_state* defines the SPMC execution state (AArch64 or AArch32). 449 Notice Hafnium used as a SPMC only supports AArch64. 450- *load_address* and *binary_size* are mostly used to verify secondary 451 entry points fit into the loaded binary image. 452- *entrypoint* defines the cold boot primary core entry point used by 453 SPMD (currently matches ``BL32_BASE``) to enter the SPMC. 454 455Other nodes in the manifest are consumed by Hafnium in the secure world. 456A sample can be found at `[7]`_: 457 458- The *hypervisor* node describes SPs. *is_ffa_partition* boolean attribute 459 indicates a FF-A compliant SP. The *load_address* field specifies the load 460 address at which BL2 loaded the SP package. 461- *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping. 462 Note the primary core is declared first, then secondary cores are declared 463 in reverse order. 464- The *memory* nodes provide platform information on the ranges of memory 465 available for use by SPs at runtime. These ranges relate to either 466 secure or non-secure memory, depending on the *device_type* field. 467 If the field specifies "memory" the range is secure, else if it specifies 468 "ns-memory" the memory is non-secure. The system integrator must exclude 469 the memory used by other components that are not SPs, such as the monitor, 470 or the SPMC itself, the OS Kernel/Hypervisor, or other NWd VMs. The SPMC 471 limits the SP's address space such that they do not access memory outside 472 of those ranges. 473 474SPMC boot 475~~~~~~~~~ 476 477The SPMC is loaded by BL2 as the BL32 image. 478 479The SPMC manifest is loaded by BL2 as the ``TOS_FW_CONFIG`` image `[9]`_. 480 481BL2 passes the SPMC manifest address to BL31 through a register. 482 483At boot time, the SPMD in BL31 runs from the primary core, initializes the core 484contexts and launches the SPMC (BL32) passing the following information through 485registers: 486 487- X0 holds the ``TOS_FW_CONFIG`` physical address (or SPMC manifest blob). 488- X1 holds the ``HW_CONFIG`` physical address. 489- X4 holds the currently running core linear id. 490 491Loading of SPs 492~~~~~~~~~~~~~~ 493 494At boot time, BL2 loads SPs sequentially in addition to the SPMC as depicted 495below: 496 497.. uml:: ../resources/diagrams/plantuml/bl2-loading-sp.puml 498 499Note this boot flow is an implementation sample on Arm's FVP platform. 500Platforms not using TF-A's *Firmware CONFiguration* framework would adjust to a 501different boot flow. The flow restricts to a maximum of 8 secure partitions. 502 503Secure boot 504~~~~~~~~~~~ 505 506The SP content certificate is inserted as a separate FIP item so that BL2 loads SPMC, 507SPMC manifest, secure partitions and verifies them for authenticity and integrity. 508Refer to TBBR specification `[3]`_. 509 510The multiple-signing domain feature (in current state dual signing domain `[8]`_) allows 511the use of two root keys namely S-ROTPK and NS-ROTPK: 512 513- SPMC (BL32) and SPMC manifest are signed by the SiP using the S-ROTPK. 514- BL33 may be signed by the OEM using NS-ROTPK. 515- An SP may be signed either by SiP (using S-ROTPK) or by OEM (using NS-ROTPK). 516- A maximum of 4 partitions can be signed with the S-ROTPK key and 4 partitions 517 signed with the NS-ROTPK key. 518 519Also refer to `Describing secure partitions`_ and `TF-A build options`_ sections. 520 521Hafnium in the secure world 522=========================== 523 524General considerations 525---------------------- 526 527Build platform for the secure world 528~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 529 530In the Hafnium reference implementation specific code parts are only relevant to 531the secure world. Such portions are isolated in architecture specific files 532and/or enclosed by a ``SECURE_WORLD`` macro. 533 534Secure partitions scheduling 535~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 536 537The FF-A specification `[1]`_ provides two ways to relinquinsh CPU time to 538secure partitions. For this a VM (Hypervisor or OS kernel), or SP invokes one of: 539 540- the FFA_MSG_SEND_DIRECT_REQ interface. 541- the FFA_RUN interface. 542 543Additionally a secure interrupt can pre-empt the normal world execution and give 544CPU cycles by transitioning to EL3 and S-EL2. 545 546Platform topology 547~~~~~~~~~~~~~~~~~ 548 549The *execution-ctx-count* SP manifest field can take the value of one or the 550total number of PEs. The FF-A specification `[1]`_ recommends the 551following SP types: 552 553- Pinned MP SPs: an execution context matches a physical PE. MP SPs must 554 implement the same number of ECs as the number of PEs in the platform. 555- Migratable UP SPs: a single execution context can run and be migrated on any 556 physical PE. Such SP declares a single EC in its SP manifest. An UP SP can 557 receive a direct message request originating from any physical core targeting 558 the single execution context. 559 560Parsing SP partition manifests 561------------------------------ 562 563Hafnium consumes SP manifests as defined in `[1]`_ and `SP manifests`_. 564Note the current implementation may not implement all optional fields. 565 566The SP manifest may contain memory and device regions nodes. In case of 567an S-EL2 SPMC: 568 569- Memory regions are mapped in the SP EL1&0 Stage-2 translation regime at 570 load time (or EL1&0 Stage-1 for an S-EL1 SPMC). A memory region node can 571 specify RX/TX buffer regions in which case it is not necessary for an SP 572 to explicitly invoke the ``FFA_RXTX_MAP`` interface. The memory referred 573 shall be contained within the memory ranges defined in SPMC manifest. The 574 NS bit in the attributes field should be consistent with the security 575 state of the range that it relates to. I.e. non-secure memory shall be 576 part of a non-secure memory range, and secure memory shall be contained 577 in a secure memory range of a given platform. 578- Device regions are mapped in the SP EL1&0 Stage-2 translation regime (or 579 EL1&0 Stage-1 for an S-EL1 SPMC) as peripherals and possibly allocate 580 additional resources (e.g. interrupts). 581 582For the S-EL2 SPMC, base addresses for memory and device region nodes are IPAs 583provided the SPMC identity maps IPAs to PAs within SP EL1&0 Stage-2 translation 584regime. 585 586Note: in the current implementation both VTTBR_EL2 and VSTTBR_EL2 point to the 587same set of page tables. It is still open whether two sets of page tables shall 588be provided per SP. The memory region node as defined in the specification 589provides a memory security attribute hinting to map either to the secure or 590non-secure EL1&0 Stage-2 table if it exists. 591 592Passing boot data to the SP 593--------------------------- 594 595In `[1]`_ , the section "Boot information protocol" defines a method for passing 596data to the SPs at boot time. It specifies the format for the boot information 597descriptor and boot information header structures, which describe the data to be 598exchanged between SPMC and SP. 599The specification also defines the types of data that can be passed. 600The aggregate of both the boot info structures and the data itself is designated 601the boot information blob, and is passed to a Partition as a contiguous memory 602region. 603 604Currently, the SPM implementation supports the FDT type which is used to pass the 605partition's DTB manifest. 606 607The region for the boot information blob is allocated through the SP package. 608 609.. image:: ../resources/diagrams/partition-package.png 610 611To adjust the space allocated for the boot information blob, the json description 612of the SP (see section `Describing secure partitions`_) shall be updated to contain 613the manifest offset. If no offset is provided the manifest offset defaults to 0x1000, 614which is the page size in the Hafnium SPMC. 615 616The configuration of the boot protocol is done in the SPs manifest. As defined by 617the specification, the manifest field 'gp-register-num' configures the GP register 618which shall be used to pass the address to the partitions boot information blob when 619booting the partition. 620In addition, the Hafnium SPMC implementation requires the boot information arguments 621to be listed in a designated DT node: 622 623.. code:: shell 624 625 boot-info { 626 compatible = "arm,ffa-manifest-boot-info"; 627 ffa_manifest; 628 }; 629 630The whole secure partition package image (see `Secure Partition packages`_) is 631mapped to the SP secure EL1&0 Stage-2 translation regime. As such, the SP can 632retrieve the address for the boot information blob in the designated GP register, 633process the boot information header and descriptors, access its own manifest 634DTB blob and extract its partition manifest properties. 635 636SP Boot order 637------------- 638 639SP manifests provide an optional boot order attribute meant to resolve 640dependencies such as an SP providing a service required to properly boot 641another SP. SPMC boots the SPs in accordance to the boot order attribute, 642lowest to the highest value. If the boot order attribute is absent from the FF-A 643manifest, the SP is treated as if it had the highest boot order value 644(i.e. lowest booting priority). 645 646It is possible for an SP to call into another SP through a direct request 647provided the latter SP has already been booted. 648 649Boot phases 650----------- 651 652Primary core boot-up 653~~~~~~~~~~~~~~~~~~~~ 654 655Upon boot-up, BL31 hands over to the SPMC (BL32) on the primary boot physical 656core. The SPMC performs its platform initializations and registers the SPMC 657secondary physical core entry point physical address by the use of the 658`FFA_SECONDARY_EP_REGISTER`_ interface (SMC invocation from the SPMC to the SPMD 659at secure physical FF-A instance). 660 661The SPMC then creates secure partitions based on SP packages and manifests. Each 662secure partition is launched in sequence (`SP Boot order`_) on their "primary" 663execution context. If the primary boot physical core linear id is N, an MP SP is 664started using EC[N] on PE[N] (see `Platform topology`_). If the partition is a 665UP SP, it is started using its unique EC0 on PE[N]. 666 667The SP primary EC (or the EC used when the partition is booted as described 668above): 669 670- Performs the overall SP boot time initialization, and in case of a MP SP, 671 prepares the SP environment for other execution contexts. 672- In the case of a MP SP, it invokes the FFA_SECONDARY_EP_REGISTER at secure 673 virtual FF-A instance (SMC invocation from SP to SPMC) to provide the IPA 674 entry point for other execution contexts. 675- Exits through ``FFA_MSG_WAIT`` to indicate successful initialization or 676 ``FFA_ERROR`` in case of failure. 677 678Secondary cores boot-up 679~~~~~~~~~~~~~~~~~~~~~~~ 680 681Once the system is started and NWd brought up, a secondary physical core is 682woken up by the ``PSCI_CPU_ON`` service invocation. The TF-A SPD hook mechanism 683calls into the SPMD on the newly woken up physical core. Then the SPMC is 684entered at the secondary physical core entry point. 685 686In the current implementation, the first SP is resumed on the coresponding EC 687(the virtual CPU which matches the physical core). The implication is that the 688first SP must be a MP SP. 689 690In a linux based system, once secure and normal worlds are booted but prior to 691a NWd FF-A driver has been loaded: 692 693- The first SP has initialized all its ECs in response to primary core boot up 694 (at system initialization) and secondary core boot up (as a result of linux 695 invoking PSCI_CPU_ON for all secondary cores). 696- Other SPs have their first execution context initialized as a result of secure 697 world initialization on the primary boot core. Other ECs for those SPs have to 698 be run first through ffa_run to complete their initialization (which results 699 in the EC completing with FFA_MSG_WAIT). 700 701Refer to `Power management`_ for further details. 702 703Notifications 704------------- 705 706The FF-A v1.1 specification `[1]`_ defines notifications as an asynchronous 707communication mechanism with non-blocking semantics. It allows for one FF-A 708endpoint to signal another for service provision, without hindering its current 709progress. 710 711Hafnium currently supports 64 notifications. The IDs of each notification define 712a position in a 64-bit bitmap. 713 714The signaling of notifications can interchangeably happen between NWd and SWd 715FF-A endpoints. 716 717The SPMC is in charge of managing notifications from SPs to SPs, from SPs to 718VMs, and from VMs to SPs. An hypervisor component would only manage 719notifications from VMs to VMs. Given the SPMC has no visibility of the endpoints 720deployed in NWd, the Hypervisor or OS kernel must invoke the interface 721FFA_NOTIFICATION_BITMAP_CREATE to allocate the notifications bitmap per FF-A 722endpoint in the NWd that supports it. 723 724A sender can signal notifications once the receiver has provided it with 725permissions. Permissions are provided by invoking the interface 726FFA_NOTIFICATION_BIND. 727 728Notifications are signaled by invoking FFA_NOTIFICATION_SET. Henceforth 729they are considered to be in a pending sate. The receiver can retrieve its 730pending notifications invoking FFA_NOTIFICATION_GET, which, from that moment, 731are considered to be handled. 732 733Per the FF-A v1.1 spec, each FF-A endpoint must be associated with a scheduler 734that is in charge of donating CPU cycles for notifications handling. The 735FF-A driver calls FFA_NOTIFICATION_INFO_GET to retrieve the information about 736which FF-A endpoints have pending notifications. The receiver scheduler is 737called and informed by the FF-A driver, and it should allocate CPU cycles to the 738receiver. 739 740There are two types of notifications supported: 741 742- Global, which are targeted to a FF-A endpoint and can be handled within any of 743 its execution contexts, as determined by the scheduler of the system. 744- Per-vCPU, which are targeted to a FF-A endpoint and to be handled within a 745 a specific execution context, as determined by the sender. 746 747The type of a notification is set when invoking FFA_NOTIFICATION_BIND to give 748permissions to the sender. 749 750Notification signaling resorts to two interrupts: 751 752- Schedule Receiver Interrupt: non-secure physical interrupt to be handled by 753 the FF-A driver within the receiver scheduler. At initialization the SPMC 754 donates a SGI ID chosen from the secure SGI IDs range and configures it as 755 non-secure. The SPMC triggers this SGI on the currently running core when 756 there are pending notifications, and the respective receivers need CPU cycles 757 to handle them. 758- Notifications Pending Interrupt: virtual interrupt to be handled by the 759 receiver of the notification. Set when there are pending notifications for the 760 given secure partition. The NPI is pended when the NWd relinquishes CPU cycles 761 to an SP. 762 763The notifications receipt support is enabled in the partition FF-A manifest. 764 765Mandatory interfaces 766-------------------- 767 768The following interfaces are exposed to SPs: 769 770- ``FFA_VERSION`` 771- ``FFA_FEATURES`` 772- ``FFA_RX_RELEASE`` 773- ``FFA_RXTX_MAP`` 774- ``FFA_RXTX_UNMAP`` 775- ``FFA_PARTITION_INFO_GET`` 776- ``FFA_ID_GET`` 777- ``FFA_MSG_WAIT`` 778- ``FFA_MSG_SEND_DIRECT_REQ`` 779- ``FFA_MSG_SEND_DIRECT_RESP`` 780- ``FFA_MEM_DONATE`` 781- ``FFA_MEM_LEND`` 782- ``FFA_MEM_SHARE`` 783- ``FFA_MEM_RETRIEVE_REQ`` 784- ``FFA_MEM_RETRIEVE_RESP`` 785- ``FFA_MEM_RELINQUISH`` 786- ``FFA_MEM_FRAG_RX`` 787- ``FFA_MEM_FRAG_TX`` 788- ``FFA_MEM_RECLAIM`` 789- ``FFA_RUN`` 790 791As part of the FF-A v1.1 support, the following interfaces were added: 792 793 - ``FFA_NOTIFICATION_BITMAP_CREATE`` 794 - ``FFA_NOTIFICATION_BITMAP_DESTROY`` 795 - ``FFA_NOTIFICATION_BIND`` 796 - ``FFA_NOTIFICATION_UNBIND`` 797 - ``FFA_NOTIFICATION_SET`` 798 - ``FFA_NOTIFICATION_GET`` 799 - ``FFA_NOTIFICATION_INFO_GET`` 800 - ``FFA_SPM_ID_GET`` 801 - ``FFA_SECONDARY_EP_REGISTER`` 802 - ``FFA_MEM_PERM_GET`` 803 - ``FFA_MEM_PERM_SET`` 804 - ``FFA_MSG_SEND2`` 805 - ``FFA_RX_ACQUIRE`` 806 807FFA_VERSION 808~~~~~~~~~~~ 809 810``FFA_VERSION`` requires a *requested_version* parameter from the caller. 811The returned value depends on the caller: 812 813- Hypervisor or OS kernel in NS-EL1/EL2: the SPMD returns the SPMC version 814 specified in the SPMC manifest. 815- SP: the SPMC returns its own implemented version. 816- SPMC at S-EL1/S-EL2: the SPMD returns its own implemented version. 817 818FFA_FEATURES 819~~~~~~~~~~~~ 820 821FF-A features supported by the SPMC may be discovered by secure partitions at 822boot (that is prior to NWd is booted) or run-time. 823 824The SPMC calling FFA_FEATURES at secure physical FF-A instance always get 825FFA_SUCCESS from the SPMD. 826 827The request made by an Hypervisor or OS kernel is forwarded to the SPMC and 828the response relayed back to the NWd. 829 830FFA_RXTX_MAP/FFA_RXTX_UNMAP 831~~~~~~~~~~~~~~~~~~~~~~~~~~~ 832 833When invoked from a secure partition FFA_RXTX_MAP maps the provided send and 834receive buffers described by their IPAs to the SP EL1&0 Stage-2 translation 835regime as secure buffers in the MMU descriptors. 836 837When invoked from the Hypervisor or OS kernel, the buffers are mapped into the 838SPMC EL2 Stage-1 translation regime and marked as NS buffers in the MMU 839descriptors. The provided addresses may be owned by a VM in the normal world, 840which is expected to receive messages from the secure world. The SPMC will in 841this case allocate internal state structures to facilitate RX buffer access 842synchronization (through FFA_RX_ACQUIRE interface), and to permit SPs to send 843messages. 844 845The FFA_RXTX_UNMAP unmaps the RX/TX pair from the translation regime of the 846caller, either it being the Hypervisor or OS kernel, as well as a secure 847partition. 848 849FFA_PARTITION_INFO_GET 850~~~~~~~~~~~~~~~~~~~~~~ 851 852Partition info get call can originate: 853 854- from SP to SPMC 855- from Hypervisor or OS kernel to SPMC. The request is relayed by the SPMD. 856 857FFA_ID_GET 858~~~~~~~~~~ 859 860The FF-A id space is split into a non-secure space and secure space: 861 862- FF-A ID with bit 15 clear relates to VMs. 863- FF-A ID with bit 15 set related to SPs. 864- FF-A IDs 0, 0xffff, 0x8000 are assigned respectively to the Hypervisor, SPMD 865 and SPMC. 866 867The SPMD returns: 868 869- The default zero value on invocation from the Hypervisor. 870- The ``spmc_id`` value specified in the SPMC manifest on invocation from 871 the SPMC (see `SPMC manifest`_) 872 873This convention helps the SPMC to determine the origin and destination worlds in 874an FF-A ABI invocation. In particular the SPMC shall filter unauthorized 875transactions in its world switch routine. It must not be permitted for a VM to 876use a secure FF-A ID as origin world by spoofing: 877 878- A VM-to-SP direct request/response shall set the origin world to be non-secure 879 (FF-A ID bit 15 clear) and destination world to be secure (FF-A ID bit 15 880 set). 881- Similarly, an SP-to-SP direct request/response shall set the FF-A ID bit 15 882 for both origin and destination IDs. 883 884An incoming direct message request arriving at SPMD from NWd is forwarded to 885SPMC without a specific check. The SPMC is resumed through eret and "knows" the 886message is coming from normal world in this specific code path. Thus the origin 887endpoint ID must be checked by SPMC for being a normal world ID. 888 889An SP sending a direct message request must have bit 15 set in its origin 890endpoint ID and this can be checked by the SPMC when the SP invokes the ABI. 891 892The SPMC shall reject the direct message if the claimed world in origin endpoint 893ID is not consistent: 894 895- It is either forwarded by SPMD and thus origin endpoint ID must be a "normal 896 world ID", 897- or initiated by an SP and thus origin endpoint ID must be a "secure world ID". 898 899 900FFA_MSG_SEND_DIRECT_REQ/FFA_MSG_SEND_DIRECT_RESP 901~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 902 903This is a mandatory interface for secure partitions consisting in direct request 904and responses with the following rules: 905 906- An SP can send a direct request to another SP. 907- An SP can receive a direct request from another SP. 908- An SP can send a direct response to another SP. 909- An SP cannot send a direct request to an Hypervisor or OS kernel. 910- An Hypervisor or OS kernel can send a direct request to an SP. 911- An SP can send a direct response to an Hypervisor or OS kernel. 912 913FFA_NOTIFICATION_BITMAP_CREATE/FFA_NOTIFICATION_BITMAP_DESTROY 914~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 915 916The secure partitions notifications bitmap are statically allocated by the SPMC. 917Hence, this interface is not to be issued by secure partitions. 918 919At initialization, the SPMC is not aware of VMs/partitions deployed in the 920normal world. Hence, the Hypervisor or OS kernel must use both ABIs for SPMC 921to be prepared to handle notifications for the provided VM ID. 922 923FFA_NOTIFICATION_BIND/FFA_NOTIFICATION_UNBIND 924~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 925 926Pair of interfaces to manage permissions to signal notifications. Prior to 927handling notifications, an FF-A endpoint must allow a given sender to signal a 928bitmap of notifications. 929 930If the receiver doesn't have notification support enabled in its FF-A manifest, 931it won't be able to bind notifications, hence forbidding it to receive any 932notifications. 933 934FFA_NOTIFICATION_SET/FFA_NOTIFICATION_GET 935~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 936 937FFA_NOTIFICATION_GET retrieves all pending global notifications and 938per-vCPU notifications targeted to the current vCPU. 939 940Hafnium maintains a global count of pending notifications which gets incremented 941and decremented when handling FFA_NOTIFICATION_SET and FFA_NOTIFICATION_GET 942respectively. A delayed SRI is triggered if the counter is non-zero when the 943SPMC returns to normal world. 944 945FFA_NOTIFICATION_INFO_GET 946~~~~~~~~~~~~~~~~~~~~~~~~~ 947 948Hafnium maintains a global count of pending notifications whose information 949has been retrieved by this interface. The count is incremented and decremented 950when handling FFA_NOTIFICATION_INFO_GET and FFA_NOTIFICATION_GET respectively. 951It also tracks notifications whose information has been retrieved individually, 952such that it avoids duplicating returned information for subsequent calls to 953FFA_NOTIFICATION_INFO_GET. For each notification, this state information is 954reset when receiver called FFA_NOTIFICATION_GET to retrieve them. 955 956FFA_SPM_ID_GET 957~~~~~~~~~~~~~~ 958 959Returns the FF-A ID allocated to an SPM component which can be one of SPMD 960or SPMC. 961 962At initialization, the SPMC queries the SPMD for the SPMC ID, using the 963FFA_ID_GET interface, and records it. The SPMC can also query the SPMD ID using 964the FFA_SPM_ID_GET interface at the secure physical FF-A instance. 965 966Secure partitions call this interface at the virtual FF-A instance, to which 967the SPMC returns the priorly retrieved SPMC ID. 968 969The Hypervisor or OS kernel can issue the FFA_SPM_ID_GET call handled by the 970SPMD, which returns the SPMC ID. 971 972FFA_SECONDARY_EP_REGISTER 973~~~~~~~~~~~~~~~~~~~~~~~~~ 974 975When the SPMC boots, all secure partitions are initialized on their primary 976Execution Context. 977 978The FFA_SECONDARY_EP_REGISTER interface is to be used by a secure partition 979from its first execution context, to provide the entry point address for 980secondary execution contexts. 981 982A secondary EC is first resumed either upon invocation of PSCI_CPU_ON from 983the NWd or by invocation of FFA_RUN. 984 985FFA_RX_ACQUIRE/FFA_RX_RELEASE 986~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 987 988The RX buffers can be used to pass information to an FF-A endpoint in the 989following scenarios: 990 991 - When it was targetted by a FFA_MSG_SEND2 invokation from another endpoint. 992 - Return the result of calling ``FFA_PARTITION_INFO_GET``. 993 - In a memory share operation, as part of the ``FFA_MEM_RETRIEVE_RESP``, 994 with the memory descriptor of the shared memory. 995 996If a normal world VM is expected to exchange messages with secure world, 997its RX/TX buffer addresses are forwarded to the SPMC via FFA_RXTX_MAP ABI, 998and are from this moment owned by the SPMC. 999The hypervisor must call the FFA_RX_ACQUIRE interface before attempting 1000to use the RX buffer, in any of the aforementioned scenarios. A successful 1001call to FFA_RX_ACQUIRE transfers ownership of RX buffer to hypervisor, such 1002that it can be safely used. 1003 1004The FFA_RX_RELEASE interface is used after the FF-A endpoint is done with 1005processing the data received in its RX buffer. If the RX buffer has been 1006acquired by the hypervisor, the FFA_RX_RELEASE call must be forwarded to 1007the SPMC to reestablish SPMC's RX ownership. 1008 1009An attempt from an SP to send a message to a normal world VM whose RX buffer 1010was acquired by the hypervisor fails with error code FFA_BUSY, to preserve 1011the RX buffer integrity. 1012The operation could then be conducted after FFA_RX_RELEASE. 1013 1014FFA_MSG_SEND2 1015~~~~~~~~~~~~~ 1016 1017Hafnium copies a message from the sender TX buffer into receiver's RX buffer. 1018For messages from SPs to VMs, operation is only possible if the SPMC owns 1019the receiver's RX buffer. 1020 1021Both receiver and sender need to enable support for indirect messaging, 1022in their respective partition manifest. The discovery of support 1023of such feature can be done via FFA_PARTITION_INFO_GET. 1024 1025On a successful message send, Hafnium pends an RX buffer full framework 1026notification for the receiver, to inform it about a message in the RX buffer. 1027 1028The handling of framework notifications is similar to that of 1029global notifications. Binding of these is not necessary, as these are 1030reserved to be used by the hypervisor or SPMC. 1031 1032SPMC-SPMD direct requests/responses 1033----------------------------------- 1034 1035Implementation-defined FF-A IDs are allocated to the SPMC and SPMD. 1036Using those IDs in source/destination fields of a direct request/response 1037permits SPMD to SPMC communication and either way. 1038 1039- SPMC to SPMD direct request/response uses SMC conduit. 1040- SPMD to SPMC direct request/response uses ERET conduit. 1041 1042This is used in particular to convey power management messages. 1043 1044Memory Sharing 1045-------------- 1046 1047Hafnium implements the following memory sharing interfaces: 1048 1049 - ``FFA_MEM_SHARE`` - for shared access between lender and borrower. 1050 - ``FFA_MEM_LEND`` - borrower to obtain exclusive access, though lender 1051 retains ownership of the memory. 1052 - ``FFA_MEM_DONATE`` - lender permanently relinquishes ownership of memory 1053 to the borrower. 1054 1055The ``FFA_MEM_RETRIEVE_REQ`` interface is for the borrower to request the 1056memory to be mapped into its address space: for S-EL1 partitions the SPM updates 1057their stage 2 translation regime; for S-EL0 partitions the SPM updates their 1058stage 1 translation regime. On a successful call, the SPMC responds back with 1059``FFA_MEM_RETRIEVE_RESP``. 1060 1061The ``FFA_MEM_RELINQUISH`` interface is for when the borrower is done with using 1062a memory region. 1063 1064The ``FFA_MEM_RECLAIM`` interface is for the owner of the memory to reestablish 1065its ownership and exclusive access to the memory shared. 1066 1067The memory transaction descriptors are transmitted via RX/TX buffers. In 1068situations where the size of the memory transaction descriptor exceeds the 1069size of the RX/TX buffers, Hafnium provides support for fragmented transmission 1070of the full transaction descriptor. The ``FFA_MEM_FRAG_RX`` and ``FFA_MEM_FRAG_TX`` 1071interfaces are for receiving and transmitting the next fragment, respectively. 1072 1073If lender and borrower(s) are SPs, all memory sharing operations are supported. 1074 1075Hafnium also supports memory sharing operations between the normal world and the 1076secure world. If there is an SP involved, the SPMC allocates data to track the 1077state of the operation. 1078 1079The SPMC is also the designated allocator for the memory handle. The hypervisor 1080or OS kernel has the possibility to rely on the SPMC to maintain the state 1081of the operation, thus saving memory. 1082A lender SP can only donate NS memory to a borrower from the normal world. 1083 1084The SPMC supports the hypervisor retrieve request, as defined by the FF-A 1085v1.1 EAC0 specification, in section 16.4.3. The intent is to aid with operations 1086that the hypervisor must do for a VM retriever. For example, when handling 1087an FFA_MEM_RECLAIM, if the hypervisor relies on SPMC to keep the state 1088of the operation, the hypervisor retrieve request can be used to obtain 1089that state information, do the necessary validations, and update stage 2 1090memory translation. 1091 1092Hafnium also supports memory lend and share targetting multiple borrowers. 1093This is the case for a lender SP to multiple SPs, and for a lender VM to 1094multiple endpoints (from both secure world and normal world). If there is 1095at least one borrower VM, the hypervisor is in charge of managing its 1096stage 2 translation on a successful memory retrieve. 1097The semantics of ``FFA_MEM_DONATE`` implies ownership transmission, 1098which should target only one partition. 1099 1100The memory share interfaces are backwards compatible with memory transaction 1101descriptors from FF-A v1.0. These get translated to FF-A v1.1 descriptors for 1102Hafnium's internal processing of the operation. If the FF-A version of a 1103borrower is v1.0, Hafnium provides FF-A v1.0 compliant memory transaction 1104descriptors on memory retrieve response. 1105 1106PE MMU configuration 1107-------------------- 1108 1109With secure virtualization enabled (``HCR_EL2.VM = 1``) and for S-EL1 1110partitions, two IPA spaces (secure and non-secure) are output from the 1111secure EL1&0 Stage-1 translation. 1112The EL1&0 Stage-2 translation hardware is fed by: 1113 1114- A secure IPA when the SP EL1&0 Stage-1 MMU is disabled. 1115- One of secure or non-secure IPA when the secure EL1&0 Stage-1 MMU is enabled. 1116 1117``VTCR_EL2`` and ``VSTCR_EL2`` provide configuration bits for controlling the 1118NS/S IPA translations. The following controls are set up: 1119``VSTCR_EL2.SW = 0`` , ``VSTCR_EL2.SA = 0``, ``VTCR_EL2.NSW = 0``, 1120``VTCR_EL2.NSA = 1``: 1121 1122- Stage-2 translations for the NS IPA space access the NS PA space. 1123- Stage-2 translation table walks for the NS IPA space are to the secure PA space. 1124 1125Secure and non-secure IPA regions (rooted to by ``VTTBR_EL2`` and ``VSTTBR_EL2``) 1126use the same set of Stage-2 page tables within a SP. 1127 1128The ``VTCR_EL2/VSTCR_EL2/VTTBR_EL2/VSTTBR_EL2`` virtual address space 1129configuration is made part of a vCPU context. 1130 1131For S-EL0 partitions with VHE enabled, a single secure EL2&0 Stage-1 translation 1132regime is used for both Hafnium and the partition. 1133 1134Schedule modes and SP Call chains 1135--------------------------------- 1136 1137An SP execution context is said to be in SPMC scheduled mode if CPU cycles are 1138allocated to it by SPMC. Correspondingly, an SP execution context is said to be 1139in Normal world scheduled mode if CPU cycles are allocated by the normal world. 1140 1141A call chain represents all SPs in a sequence of invocations of a direct message 1142request. When execution on a PE is in the secure state, only a single call chain 1143that runs in the Normal World scheduled mode can exist. FF-A v1.1 spec allows 1144any number of call chains to run in the SPMC scheduled mode but the Hafnium 1145SPMC restricts the number of call chains in SPMC scheduled mode to only one for 1146keeping the implementation simple. 1147 1148Partition runtime models 1149------------------------ 1150 1151The runtime model of an endpoint describes the transitions permitted for an 1152execution context between various states. These are the four partition runtime 1153models supported (refer to `[1]`_ section 7): 1154 1155 - RTM_FFA_RUN: runtime model presented to an execution context that is 1156 allocated CPU cycles through FFA_RUN interface. 1157 - RTM_FFA_DIR_REQ: runtime model presented to an execution context that is 1158 allocated CPU cycles through FFA_MSG_SEND_DIRECT_REQ interface. 1159 - RTM_SEC_INTERRUPT: runtime model presented to an execution context that is 1160 allocated CPU cycles by SPMC to handle a secure interrupt. 1161 - RTM_SP_INIT: runtime model presented to an execution context that is 1162 allocated CPU cycles by SPMC to initialize its state. 1163 1164If an endpoint execution context attempts to make an invalid transition or a 1165valid transition that could lead to a loop in the call chain, SPMC denies the 1166transition with the help of above runtime models. 1167 1168Interrupt management 1169-------------------- 1170 1171GIC ownership 1172~~~~~~~~~~~~~ 1173 1174The SPMC owns the GIC configuration. Secure and non-secure interrupts are 1175trapped at S-EL2. The SPMC manages interrupt resources and allocates interrupt 1176IDs based on SP manifests. The SPMC acknowledges physical interrupts and injects 1177virtual interrupts by setting the use of vIRQ/vFIQ bits before resuming a SP. 1178 1179Abbreviations: 1180 1181 - NS-Int: A non-secure physical interrupt. It requires a switch to the normal 1182 world to be handled if it triggers while execution is in secure world. 1183 - Other S-Int: A secure physical interrupt targeted to an SP different from 1184 the one that is currently running. 1185 - Self S-Int: A secure physical interrupt targeted to the SP that is currently 1186 running. 1187 1188Non-secure interrupt handling 1189~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1190 1191This section documents the actions supported in SPMC in response to a non-secure 1192interrupt as per the guidance provided by FF-A v1.1 EAC0 specification. 1193An SP specifies one of the following actions in its partition manifest: 1194 1195 - Non-secure interrupt is signaled. 1196 - Non-secure interrupt is signaled after a managed exit. 1197 - Non-secure interrupt is queued. 1198 1199An SP execution context in a call chain could specify a less permissive action 1200than subsequent SP execution contexts in the same call chain. The less 1201permissive action takes precedence over the more permissive actions specified 1202by the subsequent execution contexts. Please refer to FF-A v1.1 EAC0 section 12038.3.1 for further explanation. 1204 1205Secure interrupt handling 1206~~~~~~~~~~~~~~~~~~~~~~~~~ 1207 1208This section documents the support implemented for secure interrupt handling in 1209SPMC as per the guidance provided by FF-A v1.1 EAC0 specification. 1210The following assumptions are made about the system configuration: 1211 1212 - In the current implementation, S-EL1 SPs are expected to use the para 1213 virtualized ABIs for interrupt management rather than accessing the virtual 1214 GIC interface. 1215 - Unless explicitly stated otherwise, this support is applicable only for 1216 S-EL1 SPs managed by SPMC. 1217 - Secure interrupts are configured as G1S or G0 interrupts. 1218 - All physical interrupts are routed to SPMC when running a secure partition 1219 execution context. 1220 - All endpoints with multiple execution contexts have their contexts pinned 1221 to corresponding CPUs. Hence, a secure virtual interrupt cannot be signaled 1222 to a target vCPU that is currently running or blocked on a different 1223 physical CPU. 1224 1225A physical secure interrupt could trigger while CPU is executing in normal world 1226or secure world. 1227The action of SPMC for a secure interrupt depends on: the state of the target 1228execution context of the SP that is responsible for handling the interrupt; 1229whether the interrupt triggered while execution was in normal world or secure 1230world. 1231 1232Secure interrupt signaling mechanisms 1233~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1234 1235Signaling refers to the mechanisms used by SPMC to indicate to the SP execution 1236context that it has a pending virtual interrupt and to further run the SP 1237execution context, such that it can handle the virtual interrupt. SPMC uses 1238either the FFA_INTERRUPT interface with ERET conduit or vIRQ signal for signaling 1239to S-EL1 SPs. When normal world execution is preempted by a secure interrupt, 1240the SPMD uses the FFA_INTERRUPT ABI with ERET conduit to signal interrupt to SPMC 1241running in S-EL2. 1242 1243+-----------+---------+---------------+---------------------------------------+ 1244| SP State | Conduit | Interface and | Description | 1245| | | parameters | | 1246+-----------+---------+---------------+---------------------------------------+ 1247| WAITING | ERET, | FFA_INTERRUPT,| SPMC signals to SP the ID of pending | 1248| | vIRQ | Interrupt ID | interrupt. It pends vIRQ signal and | 1249| | | | resumes execution context of SP | 1250| | | | through ERET. | 1251+-----------+---------+---------------+---------------------------------------+ 1252| BLOCKED | ERET, | FFA_INTERRUPT | SPMC signals to SP that an interrupt | 1253| | vIRQ | | is pending. It pends vIRQ signal and | 1254| | | | resumes execution context of SP | 1255| | | | through ERET. | 1256+-----------+---------+---------------+---------------------------------------+ 1257| PREEMPTED | vIRQ | NA | SPMC pends the vIRQ signal but does | 1258| | | | not resume execution context of SP. | 1259+-----------+---------+---------------+---------------------------------------+ 1260| RUNNING | ERET, | NA | SPMC pends the vIRQ signal and resumes| 1261| | vIRQ | | execution context of SP through ERET. | 1262+-----------+---------+---------------+---------------------------------------+ 1263 1264Secure interrupt completion mechanisms 1265~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1266 1267A SP signals secure interrupt handling completion to the SPMC through the 1268following mechanisms: 1269 1270 - ``FFA_MSG_WAIT`` ABI if it was in WAITING state. 1271 - ``FFA_RUN`` ABI if its was in BLOCKED state. 1272 1273This is a remnant of SPMC implementation based on the FF-A v1.0 specification. 1274In the current implementation, S-EL1 SPs use the para-virtualized HVC interface 1275implemented by SPMC to perform priority drop and interrupt deactivation (SPMC 1276configures EOImode = 0, i.e. priority drop and deactivation are done together). 1277The SPMC performs checks to deny the state transition upon invocation of 1278either FFA_MSG_WAIT or FFA_RUN interface if the SP didn't perform the 1279deactivation of the secure virtual interrupt. 1280 1281If the current SP execution context was preempted by a secure interrupt to be 1282handled by execution context of target SP, SPMC resumes current SP after signal 1283completion by target SP execution context. 1284 1285Actions for a secure interrupt triggered while execution is in normal world 1286~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1287 1288+-------------------+----------+-----------------------------------------------+ 1289| State of target | Action | Description | 1290| execution context | | | 1291+-------------------+----------+-----------------------------------------------+ 1292| WAITING | Signaled | This starts a new call chain in SPMC scheduled| 1293| | | mode. | 1294+-------------------+----------+-----------------------------------------------+ 1295| PREEMPTED | Queued | The target execution must have been preempted | 1296| | | by a non-secure interrupt. SPMC queues the | 1297| | | secure virtual interrupt now. It is signaled | 1298| | | when the target execution context next enters | 1299| | | the RUNNING state. | 1300+-------------------+----------+-----------------------------------------------+ 1301| BLOCKED, RUNNING | NA | The target execution context is blocked or | 1302| | | running on a different CPU. This is not | 1303| | | supported by current SPMC implementation and | 1304| | | execution hits panic. | 1305+-------------------+----------+-----------------------------------------------+ 1306 1307If normal world execution was preempted by a secure interrupt, SPMC uses 1308FFA_NORMAL_WORLD_RESUME ABI to indicate completion of secure interrupt handling 1309and further returns execution to normal world. 1310 1311The following figure describes interrupt handling flow when a secure interrupt 1312triggers while execution is in normal world: 1313 1314.. image:: ../resources/diagrams/ffa-secure-interrupt-handling-nwd.png 1315 1316A brief description of the events: 1317 1318 - 1) Secure interrupt triggers while normal world is running. 1319 - 2) FIQ gets trapped to EL3. 1320 - 3) SPMD signals secure interrupt to SPMC at S-EL2 using FFA_INTERRUPT ABI. 1321 - 4) SPMC identifies target vCPU of SP and injects virtual interrupt (pends 1322 vIRQ). 1323 - 5) Assuming SP1 vCPU is in WAITING state, SPMC signals virtual interrupt 1324 using FFA_INTERRUPT with interrupt id as an argument and resumes the SP1 1325 vCPU using ERET in SPMC scheduled mode. 1326 - 6) Execution traps to vIRQ handler in SP1 provided that the virtual 1327 interrupt is not masked i.e., PSTATE.I = 0 1328 - 7) SP1 queries for the pending virtual interrupt id using a paravirtualized 1329 HVC call. SPMC clears the pending virtual interrupt state management 1330 and returns the pending virtual interrupt id. 1331 - 8) SP1 services the virtual interrupt and invokes the paravirtualized 1332 de-activation HVC call. SPMC de-activates the physical interrupt, 1333 clears the fields tracking the secure interrupt and resumes SP1 vCPU. 1334 - 9) SP1 performs secure interrupt completion through FFA_MSG_WAIT ABI. 1335 - 10) SPMC returns control to EL3 using FFA_NORMAL_WORLD_RESUME. 1336 - 11) EL3 resumes normal world execution. 1337 1338Actions for a secure interrupt triggered while execution is in secure world 1339~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1340 1341+-------------------+----------+------------------------------------------------+ 1342| State of target | Action | Description | 1343| execution context | | | 1344+-------------------+----------+------------------------------------------------+ 1345| WAITING | Signaled | This starts a new call chain in SPMC scheduled | 1346| | | mode. | 1347+-------------------+----------+------------------------------------------------+ 1348| PREEMPTED by Self | Signaled | The target execution context reenters the | 1349| S-Int | | RUNNING state to handle the secure virtual | 1350| | | interrupt. | 1351+-------------------+----------+------------------------------------------------+ 1352| PREEMPTED by | Queued | SPMC queues the secure virtual interrupt now. | 1353| NS-Int | | It is signaled when the target execution | 1354| | | context next enters the RUNNING state. | 1355+-------------------+----------+------------------------------------------------+ 1356| BLOCKED | Signaled | Both preempted and target execution contexts | 1357| | | must have been part of the Normal world | 1358| | | scheduled call chain. Refer scenario 1 of | 1359| | | Table 8.4 in the FF-A v1.1 EAC0 spec. | 1360+-------------------+----------+------------------------------------------------+ 1361| RUNNING | NA | The target execution context is running on a | 1362| | | different CPU. This scenario is not supported | 1363| | | by current SPMC implementation and execution | 1364| | | hits panic. | 1365+-------------------+----------+------------------------------------------------+ 1366 1367The following figure describes interrupt handling flow when a secure interrupt 1368triggers while execution is in secure world. We assume OS kernel sends a direct 1369request message to SP1. Further, SP1 sends a direct request message to SP2. SP1 1370enters BLOCKED state and SPMC resumes SP2. 1371 1372.. image:: ../resources/diagrams/ffa-secure-interrupt-handling-swd.png 1373 1374A brief description of the events: 1375 1376 - 1) Secure interrupt triggers while SP2 is running. 1377 - 2) SP2 gets preempted and execution traps to SPMC as IRQ. 1378 - 3) SPMC finds the target vCPU of secure partition responsible for handling 1379 this secure interrupt. In this scenario, it is SP1. 1380 - 4) SPMC pends vIRQ for SP1 and signals through FFA_INTERRUPT interface. 1381 SPMC further resumes SP1 through ERET conduit. Note that SP1 remains in 1382 Normal world schedule mode. 1383 - 6) Execution traps to vIRQ handler in SP1 provided that the virtual 1384 interrupt is not masked i.e., PSTATE.I = 0 1385 - 7) SP1 queries for the pending virtual interrupt id using a paravirtualized 1386 HVC call. SPMC clears the pending virtual interrupt state management 1387 and returns the pending virtual interrupt id. 1388 - 8) SP1 services the virtual interrupt and invokes the paravirtualized 1389 de-activation HVC call. SPMC de-activates the physical interrupt and 1390 clears the fields tracking the secure interrupt and resumes SP1 vCPU. 1391 - 9) Since SP1 direct request completed with FFA_INTERRUPT, it resumes the 1392 direct request to SP2 by invoking FFA_RUN. 1393 - 9) SPMC resumes the pre-empted vCPU of SP2. 1394 1395EL3 interrupt handling 1396~~~~~~~~~~~~~~~~~~~~~~ 1397 1398In GICv3 based systems, EL3 interrupts are configured as Group0 secure 1399interrupts. Execution traps to SPMC when a Group0 interrupt triggers while an 1400SP is running. Further, SPMC running at S-EL2 uses FFA_EL3_INTR_HANDLE ABI to 1401request EL3 platform firmware to handle a pending Group0 interrupt. 1402Similarly, SPMD registers a handler with interrupt management framework to 1403delegate handling of Group0 interrupt to the platform if the interrupt triggers 1404in normal world. 1405 1406 - Platform hook 1407 1408 - plat_spmd_handle_group0_interrupt 1409 1410 SPMD provides platform hook to handle Group0 secure interrupts. In the 1411 current design, SPMD expects the platform not to delegate handling to the 1412 NWd (such as through SDEI) while processing Group0 interrupts. 1413 1414Power management 1415---------------- 1416 1417In platforms with or without secure virtualization: 1418 1419- The NWd owns the platform PM policy. 1420- The Hypervisor or OS kernel is the component initiating PSCI service calls. 1421- The EL3 PSCI library is in charge of the PM coordination and control 1422 (eventually writing to platform registers). 1423- While coordinating PM events, the PSCI library calls backs into the Secure 1424 Payload Dispatcher for events the latter has statically registered to. 1425 1426When using the SPMD as a Secure Payload Dispatcher: 1427 1428- A power management event is relayed through the SPD hook to the SPMC. 1429- In the current implementation only cpu on (svc_on_finish) and cpu off 1430 (svc_off) hooks are registered. 1431- The behavior for the cpu on event is described in `Secondary cores boot-up`_. 1432 The SPMC is entered through its secondary physical core entry point. 1433- The cpu off event occurs when the NWd calls PSCI_CPU_OFF. The PM event is 1434 signaled to the SPMC through a power management framework message. 1435 It consists in a SPMD-to-SPMC direct request/response (`SPMC-SPMD direct 1436 requests/responses`_) conveying the event details and SPMC response. 1437 The SPMD performs a synchronous entry into the SPMC. The SPMC is entered and 1438 updates its internal state to reflect the physical core is being turned off. 1439 In the current implementation no SP is resumed as a consequence. This behavior 1440 ensures a minimal support for CPU hotplug e.g. when initiated by the NWd linux 1441 userspace. 1442 1443Arm architecture extensions for security hardening 1444================================================== 1445 1446Hafnium supports the following architecture extensions for security hardening: 1447 1448- Pointer authentication (FEAT_PAuth): the extension permits detection of forged 1449 pointers used by ROP type of attacks through the signing of the pointer 1450 value. Hafnium is built with the compiler branch protection option to permit 1451 generation of a pointer authentication code for return addresses (pointer 1452 authentication for instructions). The APIA key is used while Hafnium runs. 1453 A random key is generated at boot time and restored upon entry into Hafnium 1454 at run-time. APIA and other keys (APIB, APDA, APDB, APGA) are saved/restored 1455 in vCPU contexts permitting to enable pointer authentication in VMs/SPs. 1456- Branch Target Identification (FEAT_BTI): the extension permits detection of 1457 unexpected indirect branches used by JOP type of attacks. Hafnium is built 1458 with the compiler branch protection option, inserting land pads at function 1459 prologues that are reached by indirect branch instructions (BR/BLR). 1460 Hafnium code pages are marked as guarded in the EL2 Stage-1 MMU descriptors 1461 such that an indirect branch must always target a landpad. A fault is 1462 triggered otherwise. VMs/SPs can (independently) mark their code pages as 1463 guarded in the EL1&0 Stage-1 translation regime. 1464- Memory Tagging Extension (FEAT_MTE): the option permits detection of out of 1465 bound memory array accesses or re-use of an already freed memory region. 1466 Hafnium enables the compiler option permitting to leverage MTE stack tagging 1467 applied to core stacks. Core stacks are marked as normal tagged memory in the 1468 EL2 Stage-1 translation regime. A synchronous data abort is generated upon tag 1469 check failure on load/stores. A random seed is generated at boot time and 1470 restored upon entry into Hafnium. MTE system registers are saved/restored in 1471 vCPU contexts permitting MTE usage from VMs/SPs. 1472 1473SMMUv3 support in Hafnium 1474========================= 1475 1476An SMMU is analogous to an MMU in a CPU. It performs address translations for 1477Direct Memory Access (DMA) requests from system I/O devices. 1478The responsibilities of an SMMU include: 1479 1480- Translation: Incoming DMA requests are translated from bus address space to 1481 system physical address space using translation tables compliant to 1482 Armv8/Armv7 VMSA descriptor format. 1483- Protection: An I/O device can be prohibited from read, write access to a 1484 memory region or allowed. 1485- Isolation: Traffic from each individial device can be independently managed. 1486 The devices are differentiated from each other using unique translation 1487 tables. 1488 1489The following diagram illustrates a typical SMMU IP integrated in a SoC with 1490several I/O devices along with Interconnect and Memory system. 1491 1492.. image:: ../resources/diagrams/MMU-600.png 1493 1494SMMU has several versions including SMMUv1, SMMUv2 and SMMUv3. Hafnium provides 1495support for SMMUv3 driver in both normal and secure world. A brief introduction 1496of SMMUv3 functionality and the corresponding software support in Hafnium is 1497provided here. 1498 1499SMMUv3 features 1500--------------- 1501 1502- SMMUv3 provides Stage1, Stage2 translation as well as nested (Stage1 + Stage2) 1503 translation support. It can either bypass or abort incoming translations as 1504 well. 1505- Traffic (memory transactions) from each upstream I/O peripheral device, 1506 referred to as Stream, can be independently managed using a combination of 1507 several memory based configuration structures. This allows the SMMUv3 to 1508 support a large number of streams with each stream assigned to a unique 1509 translation context. 1510- Support for Armv8.1 VMSA where the SMMU shares the translation tables with 1511 a Processing Element. AArch32(LPAE) and AArch64 translation table format 1512 are supported by SMMUv3. 1513- SMMUv3 offers non-secure stream support with secure stream support being 1514 optional. Logically, SMMUv3 behaves as if there is an indepdendent SMMU 1515 instance for secure and non-secure stream support. 1516- It also supports sub-streams to differentiate traffic from a virtualized 1517 peripheral associated with a VM/SP. 1518- Additionally, SMMUv3.2 provides support for PEs implementing Armv8.4-A 1519 extensions. Consequently, SPM depends on Secure EL2 support in SMMUv3.2 1520 for providing Secure Stage2 translation support to upstream peripheral 1521 devices. 1522 1523SMMUv3 Programming Interfaces 1524----------------------------- 1525 1526SMMUv3 has three software interfaces that are used by the Hafnium driver to 1527configure the behaviour of SMMUv3 and manage the streams. 1528 1529- Memory based data strutures that provide unique translation context for 1530 each stream. 1531- Memory based circular buffers for command queue and event queue. 1532- A large number of SMMU configuration registers that are memory mapped during 1533 boot time by Hafnium driver. Except a few registers, all configuration 1534 registers have independent secure and non-secure versions to configure the 1535 behaviour of SMMUv3 for translation of secure and non-secure streams 1536 respectively. 1537 1538Peripheral device manifest 1539-------------------------- 1540 1541Currently, SMMUv3 driver in Hafnium only supports dependent peripheral devices. 1542These devices are dependent on PE endpoint to initiate and receive memory 1543management transactions on their behalf. The acccess to the MMIO regions of 1544any such device is assigned to the endpoint during boot. Moreover, SMMUv3 driver 1545uses the same stage 2 translations for the device as those used by partition 1546manager on behalf of the PE endpoint. This ensures that the peripheral device 1547has the same visibility of the physical address space as the endpoint. The 1548device node of the corresponding partition manifest (refer to `[1]`_ section 3.2 1549) must specify these additional properties for each peripheral device in the 1550system : 1551 1552- smmu-id: This field helps to identify the SMMU instance that this device is 1553 upstream of. 1554- stream-ids: List of stream IDs assigned to this device. 1555 1556.. code:: shell 1557 1558 smmuv3-testengine { 1559 base-address = <0x00000000 0x2bfe0000>; 1560 pages-count = <32>; 1561 attributes = <0x3>; 1562 smmu-id = <0>; 1563 stream-ids = <0x0 0x1>; 1564 interrupts = <0x2 0x3>, <0x4 0x5>; 1565 exclusive-access; 1566 }; 1567 1568SMMUv3 driver limitations 1569------------------------- 1570 1571The primary design goal for the Hafnium SMMU driver is to support secure 1572streams. 1573 1574- Currently, the driver only supports Stage2 translations. No support for 1575 Stage1 or nested translations. 1576- Supports only AArch64 translation format. 1577- No support for features such as PCI Express (PASIDs, ATS, PRI), MSI, RAS, 1578 Fault handling, Performance Monitor Extensions, Event Handling, MPAM. 1579- No support for independent peripheral devices. 1580 1581S-EL0 Partition support 1582======================= 1583The SPMC (Hafnium) has limited capability to run S-EL0 FF-A partitions using 1584FEAT_VHE (mandatory with ARMv8.1 in non-secure state, and in secure world 1585with ARMv8.4 and FEAT_SEL2). 1586 1587S-EL0 partitions are useful for simple partitions that don't require full 1588Trusted OS functionality. It is also useful to reduce jitter and cycle 1589stealing from normal world since they are more lightweight than VMs. 1590 1591S-EL0 partitions are presented, loaded and initialized the same as S-EL1 VMs by 1592the SPMC. They are differentiated primarily by the 'exception-level' property 1593and the 'execution-ctx-count' property in the SP manifest. They are host apps 1594under the single EL2&0 Stage-1 translation regime controlled by the SPMC and 1595call into the SPMC through SVCs as opposed to HVCs and SMCs. These partitions 1596can use FF-A defined services (FFA_MEM_PERM_*) to update or change permissions 1597for memory regions. 1598 1599S-EL0 partitions are required by the FF-A specification to be UP endpoints, 1600capable of migrating, and the SPMC enforces this requirement. The SPMC allows 1601a S-EL0 partition to accept a direct message from secure world and normal world, 1602and generate direct responses to them. 1603All S-EL0 partitions must use AArch64. AArch32 S-EL0 partitions are not supported. 1604 1605Memory sharing, indirect messaging, and notifications functionality with S-EL0 1606partitions is supported. 1607 1608Interrupt handling is not supported with S-EL0 partitions and is work in 1609progress. 1610 1611References 1612========== 1613 1614.. _[1]: 1615 1616[1] `Arm Firmware Framework for Arm A-profile <https://developer.arm.com/docs/den0077/latest>`__ 1617 1618.. _[2]: 1619 1620[2] :ref:`Secure Partition Manager using MM interface<Secure Partition Manager (MM)>` 1621 1622.. _[3]: 1623 1624[3] `Trusted Boot Board Requirements 1625Client <https://developer.arm.com/documentation/den0006/d/>`__ 1626 1627.. _[4]: 1628 1629[4] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/el3_runtime/aarch64/context.S#n45 1630 1631.. _[5]: 1632 1633[5] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/spm/cactus/plat/arm/fvp/fdts/cactus.dts 1634 1635.. _[6]: 1636 1637[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html 1638 1639.. _[7]: 1640 1641[7] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts 1642 1643.. _[8]: 1644 1645[8] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/CFQFGU6H2D5GZYMUYGTGUSXIU3OYZP6U/ 1646 1647.. _[9]: 1648 1649[9] https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#dynamic-configuration-during-cold-boot 1650 1651-------------- 1652 1653*Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.* 1654
