1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/partition/partition.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <lib/gpt_rme/gpt_rme.h> 22 #ifdef SPD_opteed 23 #include <lib/optee_utils.h> 24 #endif 25 #include <lib/utils.h> 26 #include <plat/arm/common/plat_arm.h> 27 #include <plat/common/platform.h> 28 29 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 30 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 31 32 /* Base address of fw_config received from BL1 */ 33 static uintptr_t config_base; 34 35 /* 36 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 37 * for `meminfo_t` data structure and fw_configs passed from BL1. 38 */ 39 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 40 41 /* Weak definitions may be overridden in specific ARM standard platform */ 42 #pragma weak bl2_early_platform_setup2 43 #pragma weak bl2_platform_setup 44 #pragma weak bl2_plat_arch_setup 45 #pragma weak bl2_plat_sec_mem_layout 46 47 #if ENABLE_RME 48 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 49 bl2_tzram_layout.total_base, \ 50 bl2_tzram_layout.total_size, \ 51 MT_MEMORY | MT_RW | MT_ROOT) 52 #else 53 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 54 bl2_tzram_layout.total_base, \ 55 bl2_tzram_layout.total_size, \ 56 MT_MEMORY | MT_RW | MT_SECURE) 57 #endif /* ENABLE_RME */ 58 59 #pragma weak arm_bl2_plat_handle_post_image_load 60 61 /******************************************************************************* 62 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 63 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 64 * Copy it to a safe location before its reclaimed by later BL2 functionality. 65 ******************************************************************************/ 66 void arm_bl2_early_platform_setup(uintptr_t fw_config, 67 struct meminfo *mem_layout) 68 { 69 int __maybe_unused ret; 70 71 /* Initialize the console to provide early debug support */ 72 arm_console_boot_init(); 73 74 /* Setup the BL2 memory layout */ 75 bl2_tzram_layout = *mem_layout; 76 77 config_base = fw_config; 78 79 /* Initialise the IO layer and register platform IO devices */ 80 plat_arm_io_setup(); 81 82 /* Load partition table */ 83 #if ARM_GPT_SUPPORT 84 ret = gpt_partition_init(); 85 if (ret != 0) { 86 ERROR("GPT partition initialisation failed!\n"); 87 panic(); 88 } 89 90 #endif /* ARM_GPT_SUPPORT */ 91 } 92 93 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 94 { 95 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 96 97 generic_delay_timer_init(); 98 } 99 100 /* 101 * Perform BL2 preload setup. Currently we initialise the dynamic 102 * configuration here. 103 */ 104 void bl2_plat_preload_setup(void) 105 { 106 arm_bl2_dyn_cfg_init(); 107 108 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 109 /* Always use the FIP from bank 0 */ 110 arm_set_fip_addr(0U); 111 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 112 } 113 114 /* 115 * Perform ARM standard platform setup. 116 */ 117 void arm_bl2_platform_setup(void) 118 { 119 #if !ENABLE_RME 120 /* Initialize the secure environment */ 121 plat_arm_security_setup(); 122 #endif 123 124 #if defined(PLAT_ARM_MEM_PROT_ADDR) 125 arm_nor_psci_do_static_mem_protect(); 126 #endif 127 } 128 129 void bl2_platform_setup(void) 130 { 131 arm_bl2_platform_setup(); 132 } 133 134 #if ENABLE_RME 135 static void arm_bl2_gpt_setup(void) 136 { 137 /* 138 * It is to be noted that any Arm platform that reuses arm_bl2_gpt_setup 139 * must implement plat_arm_get_gpt_info within its platform code 140 */ 141 const arm_gpt_info_t *arm_gpt_info = 142 plat_arm_get_gpt_info(); 143 144 if (arm_gpt_info == NULL) { 145 ERROR("arm_gpt_info not initialized!!\n"); 146 panic(); 147 } 148 149 /* Initialize entire protected space to GPT_GPI_ANY. */ 150 if (gpt_init_l0_tables(arm_gpt_info->pps, arm_gpt_info->l0_base, 151 arm_gpt_info->l0_size) < 0) { 152 ERROR("gpt_init_l0_tables() failed!\n"); 153 panic(); 154 } 155 156 /* Carve out defined PAS ranges. */ 157 if (gpt_init_pas_l1_tables(arm_gpt_info->pgs, 158 arm_gpt_info->l1_base, 159 arm_gpt_info->l1_size, 160 arm_gpt_info->pas_region_base, 161 arm_gpt_info->pas_region_count) < 0) { 162 ERROR("gpt_init_pas_l1_tables() failed!\n"); 163 panic(); 164 } 165 166 INFO("Enabling Granule Protection Checks\n"); 167 if (gpt_enable() < 0) { 168 ERROR("gpt_enable() failed!\n"); 169 panic(); 170 } 171 } 172 #endif /* ENABLE_RME */ 173 174 /******************************************************************************* 175 * Perform the very early platform specific architectural setup here. 176 * When RME is enabled the secure environment is initialised before 177 * initialising and enabling Granule Protection. 178 * This function initialises the MMU in a quick and dirty way. 179 ******************************************************************************/ 180 void arm_bl2_plat_arch_setup(void) 181 { 182 #if USE_COHERENT_MEM 183 /* Ensure ARM platforms don't use coherent memory in BL2. */ 184 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 185 #endif 186 187 const mmap_region_t bl_regions[] = { 188 MAP_BL2_TOTAL, 189 ARM_MAP_BL_RO, 190 #if USE_ROMLIB 191 ARM_MAP_ROMLIB_CODE, 192 ARM_MAP_ROMLIB_DATA, 193 #endif 194 ARM_MAP_BL_CONFIG_REGION, 195 #if ENABLE_RME 196 ARM_MAP_L0_GPT_REGION, 197 #endif 198 {0} 199 }; 200 201 #if ENABLE_RME 202 /* Initialise the secure environment */ 203 plat_arm_security_setup(); 204 #endif 205 setup_page_tables(bl_regions, plat_arm_get_mmap()); 206 207 #ifdef __aarch64__ 208 #if ENABLE_RME 209 /* BL2 runs in EL3 when RME enabled. */ 210 assert(get_armv9_2_feat_rme_support() != 0U); 211 enable_mmu_el3(0); 212 213 /* Initialise and enable granule protection after MMU. */ 214 arm_bl2_gpt_setup(); 215 #else 216 enable_mmu_el1(0); 217 #endif 218 #else 219 enable_mmu_svc_mon(0); 220 #endif 221 222 arm_setup_romlib(); 223 } 224 225 void bl2_plat_arch_setup(void) 226 { 227 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 228 229 arm_bl2_plat_arch_setup(); 230 231 /* Fill the properties struct with the info from the config dtb */ 232 fconf_populate("FW_CONFIG", config_base); 233 234 /* TB_FW_CONFIG was also loaded by BL1 */ 235 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 236 assert(tb_fw_config_info != NULL); 237 238 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 239 } 240 241 int arm_bl2_handle_post_image_load(unsigned int image_id) 242 { 243 int err = 0; 244 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 245 #ifdef SPD_opteed 246 bl_mem_params_node_t *pager_mem_params = NULL; 247 bl_mem_params_node_t *paged_mem_params = NULL; 248 #endif 249 assert(bl_mem_params != NULL); 250 251 switch (image_id) { 252 #ifdef __aarch64__ 253 case BL32_IMAGE_ID: 254 #ifdef SPD_opteed 255 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 256 assert(pager_mem_params); 257 258 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 259 assert(paged_mem_params); 260 261 err = parse_optee_header(&bl_mem_params->ep_info, 262 &pager_mem_params->image_info, 263 &paged_mem_params->image_info); 264 if (err != 0) { 265 WARN("OPTEE header parse error.\n"); 266 } 267 #endif 268 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 269 break; 270 #endif 271 272 case BL33_IMAGE_ID: 273 /* BL33 expects to receive the primary CPU MPID (through r0) */ 274 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 275 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 276 break; 277 278 #ifdef SCP_BL2_BASE 279 case SCP_BL2_IMAGE_ID: 280 /* The subsequent handling of SCP_BL2 is platform specific */ 281 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 282 if (err) { 283 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 284 } 285 break; 286 #endif 287 default: 288 /* Do nothing in default case */ 289 break; 290 } 291 292 return err; 293 } 294 295 /******************************************************************************* 296 * This function can be used by the platforms to update/use image 297 * information for given `image_id`. 298 ******************************************************************************/ 299 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 300 { 301 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 302 /* For Secure Partitions we don't need post processing */ 303 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 304 (image_id < MAX_NUMBER_IDS)) { 305 return 0; 306 } 307 #endif 308 return arm_bl2_handle_post_image_load(image_id); 309 } 310