core: benchmark: drop reference on freed memory

Add missing reset of the benchmark buffer mobj reference when
it is freed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by:

core: benchmark: drop reference on freed memory

Add missing reset of the benchmark buffer mobj reference when
it is freed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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synquacer: rng-pta: Add rng info invoke command

Add rng info invoke command to provide information like rng data-rate
and quality/entropy of output rng data.

Signed-off-by: Sumit Garg <sumit.garg@l

synquacer: rng-pta: Add rng info invoke command

Add rng info invoke command to provide information like rng data-rate
and quality/entropy of output rng data.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: syscall_storage_obj_rename(): fix handling of .rename() return status

Any error returned by fops->rename() should be reflected by
syscall_storage_obj_rename(). There is no reason why errors ot

core: syscall_storage_obj_rename(): fix handling of .rename() return status

Any error returned by fops->rename() should be reflected by
syscall_storage_obj_rename(). There is no reason why errors other than
TEE_ERROR_GENERIC should be ignored.

Fixes the following test case: create two persistent objects (o1 and o2),
close o1, rename o2 to the name of o1. TEE_RenamePersistentObject() should
return TEE_ERROR_ACCESS_CONFLICT, but TEE_SUCCESS is returned instead.

Fixes: https://github.com/OP-TEE/optee_os/issues/2707
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Chao Liu <chao.liu@amlogic.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: psci: switch secondary boot cpu offline

Secondary boot core can be switched OFF from a functional view by
being reset. To get the core back on line, it shall be woken through
catching secu

stm32mp1: psci: switch secondary boot cpu offline

Secondary boot core can be switched OFF from a functional view by
being reset. To get the core back on line, it shall be woken through
catching secure SGI0 interrupt then proceeding to same sequence as
when getting the core online from a cold reset.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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stm32mp1: stm32mp_bkpreg() returns the backup register address

Rename bckreg_address() into stm32mp_bkpreg()to get the address of the
32bit backup register specified by ID defined in boot_api.h.

Si

stm32mp1: stm32mp_bkpreg() returns the backup register address

Rename bckreg_address() into stm32mp_bkpreg()to get the address of the
32bit backup register specified by ID defined in boot_api.h.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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stm32mp1: psci: implement affinity_info

This change implements PSCI_AFFINITY_INFO for platform stm32mp1.
The cores state are saved in a local array and accessed with SMP
locking protection. Note the

stm32mp1: psci: implement affinity_info

This change implements PSCI_AFFINITY_INFO for platform stm32mp1.
The cores state are saved in a local array and accessed with SMP
locking protection. Note these do not lock/unlock if executed with
the MMU disabled.

CPU shall call stm32mp_register_online_cpu() when online in the
secure world. GIC CPU interface initialization is used to register
online primary and secondary boot cores.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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stm32mp1: internal change for GIC support

This change exports GIC CPU interfaces base address to the platform.

This change is needed by a later change where the platform needs
to specific GIC suppo

stm32mp1: internal change for GIC support

This change exports GIC CPU interfaces base address to the platform.

This change is needed by a later change where the platform needs
to specific GIC support not available through the GIC driver.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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stm32mp1: RCC support

RCC if the SoC interface for clocks, reset and some low power features.
The drivers is very specific to the platform stm32mp1 hence located
next to the platform specific source

stm32mp1: RCC support

RCC if the SoC interface for clocks, reset and some low power features.
The drivers is very specific to the platform stm32mp1 hence located
next to the platform specific source files.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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stm32mp1: move PSCI in pm/psci.c

Source file pm/psci.c will soon hold several PSCI functions and sequences.
Move now the existing PSCI_CPU_ON support to pm/psci.c.

Signed-off-by: Etienne Carriere <

stm32mp1: move PSCI in pm/psci.c

Source file pm/psci.c will soon hold several PSCI functions and sequences.
Move now the existing PSCI_CPU_ON support to pm/psci.c.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: move io_pa_va support out of serial drivers

io_pa_or_va() is generic enough to be useful for non serial driver
matters. Move it to core_mem_prot.h.

Signed-off-by: Etienne Carriere <etienne.ca

core: move io_pa_va support out of serial drivers

io_pa_or_va() is generic enough to be useful for non serial driver
matters. Move it to core_mem_prot.h.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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stm32_uart: timeout to escape waiting loops

Add a timeout in output console waiting loops. This is useful if
the secure world relies on a non-secure UART that may be suspended
or disabled from the n

stm32_uart: timeout to escape waiting loops

Add a timeout in output console waiting loops. This is useful if
the secure world relies on a non-secure UART that may be suspended
or disabled from the non-secure world.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: timeout detection support

Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.

timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided micr

core: timeout detection support

Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.

timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided microsecond delay value from current time.

timeout_elapsed(reference) return true/false whether the reference
timeout is elapsed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Introduce CFG_USER_TA_TARGETS to select user mode architecture(s)

This change introduces CFG_USER_TA_TARGETS to allow the configuration
directives to select the architectures for which userspace TA

Introduce CFG_USER_TA_TARGETS to select user mode architecture(s)

This change introduces CFG_USER_TA_TARGETS to allow the configuration
directives to select the architectures for which userspace TA and TA
libraries shall be built. The only use case for the moment is to be able
to build only 32 or 64-bit libraries and TAs when the platform would
otherwise support both 32 and 64-bit. See the example below.

If CFG_USER_TA_TARGETS is undefined or empty, all the architectures
supported by the platform are built.

If CFG_USER_TA_TARGETS contains an unsupported value, the build will
report an error.

Examples:

$ make PLATFORM=hikey CFG_ARM64_core=y
# Builds both 32 and 64-bit userspace
$ make PLATFORM=hikey CFG_ARM64_core=y \
CFG_USER_TA_TARGETS="ta_arm32 ta_arm64"
# Same as above
$ make PLATFORM=hikey CFG_ARM64_core=y CFG_USER_TA_TARGETS=ta_arm32
# Builds only 32-bit userspace

Suggested-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Platforms set supported TA targets as $(supported-ta-targets)

Rename $(ta-targets) to $(supported-ta-targets) in the platform
configuration files, in preparation for the next patch.

Suggested-by: J

Platforms set supported TA targets as $(supported-ta-targets)

Rename $(ta-targets) to $(supported-ta-targets) in the platform
configuration files, in preparation for the next patch.

Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Factor out ta-targets from platform config

Platforms use the same basic pattern again and again:

ta-targets = ta_arm32
ifeq ($(CFG_ARM64_core),y)
ta-targets += ta_arm64
endif

Let's move this p

Factor out ta-targets from platform config

Platforms use the same basic pattern again and again:

ta-targets = ta_arm32
ifeq ($(CFG_ARM64_core),y)
ta-targets += ta_arm64
endif

Let's move this pattern to core/arch/arm/arm.mk, make it the default, and
cleanup the platform configuration files.

Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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synquacer: Add RNG pseudo TA

This platform provides 7 on-chip thermal sensors accessible from secure
world only. So, using thermal noise from these sensors we have tried to
create an entropy source

synquacer: Add RNG pseudo TA

This platform provides 7 on-chip thermal sensors accessible from secure
world only. So, using thermal noise from these sensors we have tried to
create an entropy source as a pseudo TA.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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synquacer: Enable secure timer interrupt framework

Currently there is no means to perform background housekeeping in
secure world on Synquacer platforms. Use an (optional) periodic
timer to allow an

synquacer: Enable secure timer interrupt framework

Currently there is no means to perform background housekeeping in
secure world on Synquacer platforms. Use an (optional) periodic
timer to allow any housekeeping to be performed.

Although it could be expanded, at present the code is fairly simple
because we expect only a single PTA to exploit the timer interrupt.
The secure timer interrupt is configured to fire every 2ms.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: arm64: Add Secure EL1 physical timer framework

As an implementation of generic timer, arm64 platforms provides secure
EL1 physical timer. So enable corresponding framework. For more
informatio

core: arm64: Add Secure EL1 physical timer framework

As an implementation of generic timer, arm64 platforms provides secure
EL1 physical timer. So enable corresponding framework. For more
information refer to section: D6.1.5 Timers - ARMv8-A RM.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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libtomcrypt: Import SHA512/256 approved hash algorithm

SHA-512/256 is an approved hash algorithm and a vetted conditioner as
per NIST.SP.800-90B spec. We have used it to condition raw thermal
sensor

libtomcrypt: Import SHA512/256 approved hash algorithm

SHA-512/256 is an approved hash algorithm and a vetted conditioner as
per NIST.SP.800-90B spec. We have used it to condition raw thermal
sensor noise on Developerbox to condense entropy.

It is imported from libtomcrypt:
Git url: https://github.com/libtom/libtomcrypt.git, release tag: v1.18.0.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: io_{set|clr|clrset}bits32() helpers

Introduce new iomem util functions to set, clear or set and clear
bit masks in peripheral interfaces.

io_setbits32(addr, mask) sets the bits enabled in mas

core: io_{set|clr|clrset}bits32() helpers

Introduce new iomem util functions to set, clear or set and clear
bit masks in peripheral interfaces.

io_setbits32(addr, mask) sets the bits enabled in mask at address.
io_clrbits32(addr, mask) clears the bits enabled in mask.
io_clrsetbits32(addr, clear_mask, set_mask) clears the bits enabled in
clear_mask and sets the bits enabled in set_mask.

These functions are more friendly in instruction blocks to sets and
clears bitmasks in peripheral registers. They provide a more readable
implementation than playing with io_mask32() for the equivalent
sequence, for example, extracted from a DDR controller driver:

(...)
/* IOs powering down (PUBL registers) */

io_setbits32(ddrphy_base + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD);
io_setbits_32(ddrphy_base + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDR);

io_clrsetbits32(ddrphy_base + DDRPHYC_ACIOCR,
DDRPHYC_ACIOCR_CKPDD_MASK, DDRPHYC_ACIOCR_CKPDD_0);

io_clrsetbits32(ddrphy_base + DDRPHYC_ACIOCR,
DDRPHYC_ACIOCR_CKPDR_MASK, DDRPHYC_ACIOCR_CKPDR_0);

io_clrsetbits32(ddrphy_base + DDRPHYC_ACIOCR,
DDRPHYC_ACIOCR_CSPDD_MASK, DDRPHYC_ACIOCR_CSPDD_0);
(...)

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: imx: add iMX7S WaARP7 MBL board definition

This patch adds an OP-TEE port for the i.MX7S WaRP7 for the MBED Linux OS
boot flow.

BootROM -> ATF/BL2
ATF -> FIP {u-boot, OPTEE}
OPTEE -> {po

arm: imx: add iMX7S WaARP7 MBL board definition

This patch adds an OP-TEE port for the i.MX7S WaRP7 for the MBED Linux OS
boot flow.

BootROM -> ATF/BL2
ATF -> FIP {u-boot, OPTEE}
OPTEE -> {populates DTB overlay}
u-boot -> FIT {DTB, Kernel, initramfs}
Merges DTB and OPTEE DTB-overlay
Linux

The current warp7 port looks like
BootROM -> u-boot
u-boot -> Load {Kernel, OPTEE, DTB}
OPTEE
Linux

In order to support the ATF bootflow a new port of OP-TEE with slightly
tweaked parameters is added here.

CFG_NS_ENTRY_ADDR = 0x87800000 is the entry point of u-boot
CFG_DT_OVERLAY = y adds DTB overlay fragments to the passed DTB

make PLATFORM=imx-mx7swarp7_mbl

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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imx: wdog: Introduce CFG_IMX_WDOG_EXT_RESET for non-DTB mode

When resetting a system that has not booted up with a full DTB in memory
the value ext_reset will always be false.

This patch introduces

imx: wdog: Introduce CFG_IMX_WDOG_EXT_RESET for non-DTB mode

When resetting a system that has not booted up with a full DTB in memory
the value ext_reset will always be false.

This patch introduces a platform define to tell the watchdog driver to
drive ext_reset.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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imx: wdog: Skip DTB wdog init on DTB overlay

When OPTEE is providing a DTB overlay to a subsequent boot stage CFG_DT
will be true as will CFG_EXTERNAL_DTB_OVERLAY.

In this case there will be no DTB

imx: wdog: Skip DTB wdog init on DTB overlay

When OPTEE is providing a DTB overlay to a subsequent boot stage CFG_DT
will be true as will CFG_EXTERNAL_DTB_OVERLAY.

In this case there will be no DTB for the imx watchdog driver to consume so
do not try to do so.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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core: always save non-secure vfp state

Prior to this patch the non-secure VFP state was only saved when it
seemed necessary based on control registers.

To make sure that non-secure VFP state isn't

core: always save non-secure vfp state

Prior to this patch the non-secure VFP state was only saved when it
seemed necessary based on control registers.

To make sure that non-secure VFP state isn't corrupted always save the
entire register file before modifying it. This is now the same behavior
on both ARMv8-A and ARMv7-A platforms.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: framework to register PM callbacks

Introduce a framework for power management callback registering.

Drivers and services can register a callback function for the platform
suspend and resume s

core: framework to register PM callbacks

Introduce a framework for power management callback registering.

Drivers and services can register a callback function for the platform
suspend and resume sequences. A private address handle can be registered
with the callback and retrieved from the callback. Callback can be
registered with a specific call order as defined per PM_CB_ORDER_*.

Callback shall return an error if failing to complete target transition.
This information may be used by the platform to resume a platform on
non-fatal failure to suspend.

Callbacks are related to a callback level. It defines the callbacks
call ordering, allowing core low level drivers (as clocks or the GIC)
to be suspended after all drivers and resume before these.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Cedric Neveux <cedric.neveux@nxp.com>

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