1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_uart.h> 11 #include <kernel/generic_boot.h> 12 #include <kernel/misc.h> 13 #include <kernel/panic.h> 14 #include <kernel/pm_stubs.h> 15 #include <kernel/spinlock.h> 16 #include <mm/core_memprot.h> 17 #include <platform_config.h> 18 #include <sm/psci.h> 19 #include <stm32_util.h> 20 #include <tee/entry_std.h> 21 #include <tee/entry_fast.h> 22 #include <trace.h> 23 24 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CONSOLE_UART_SIZE); 25 26 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 27 register_phys_mem(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 28 29 static struct console_pdata console_data; 30 31 static void main_fiq(void); 32 33 static const struct thread_handlers handlers = { 34 .std_smc = tee_entry_std, 35 .fast_smc = tee_entry_fast, 36 .nintr = main_fiq, 37 .cpu_on = pm_panic, 38 .cpu_off = pm_panic, 39 .cpu_suspend = pm_panic, 40 .cpu_resume = pm_panic, 41 .system_off = pm_panic, 42 .system_reset = pm_panic, 43 }; 44 45 const struct thread_handlers *generic_boot_get_handlers(void) 46 { 47 return &handlers; 48 } 49 50 #define _ID2STR(id) (#id) 51 #define ID2STR(id) _ID2STR(id) 52 53 static TEE_Result platform_banner(void) 54 { 55 #ifdef CFG_EMBED_DTB 56 IMSG("Platform stm32mp1: flavor %s - DT %s", 57 ID2STR(PLATFORM_FLAVOR), 58 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 59 #else 60 IMSG("Platform stm32mp1: flavor %s - no device tree", 61 ID2STR(PLATFORM_FLAVOR)); 62 #endif 63 64 return TEE_SUCCESS; 65 } 66 service_init(platform_banner); 67 68 void console_init(void) 69 { 70 stm32_uart_init(&console_data, CONSOLE_UART_BASE); 71 register_serial_console(&console_data.chip); 72 } 73 74 /* 75 * GIC init, used also for primary/secondary boot core wake completion 76 */ 77 static struct gic_data gic_data; 78 79 static void main_fiq(void) 80 { 81 gic_it_handle(&gic_data); 82 } 83 84 void main_init_gic(void) 85 { 86 assert(cpu_mmu_enabled()); 87 88 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 89 itr_init(&gic_data.chip); 90 91 stm32mp_register_online_cpu(); 92 } 93 94 void main_secondary_init_gic(void) 95 { 96 gic_cpu_init(&gic_data); 97 98 stm32mp_register_online_cpu(); 99 } 100 101 uintptr_t get_gicc_base(void) 102 { 103 uintptr_t pbase = GIC_BASE + GICC_OFFSET; 104 105 if (cpu_mmu_enabled()) 106 return (uintptr_t)phys_to_virt_io(pbase); 107 108 return pbase; 109 } 110 111 uintptr_t get_gicd_base(void) 112 { 113 uintptr_t pbase = GIC_BASE + GICD_OFFSET; 114 115 if (cpu_mmu_enabled()) 116 return (uintptr_t)phys_to_virt_io(pbase); 117 118 return pbase; 119 } 120 121 uint32_t may_spin_lock(unsigned int *lock) 122 { 123 if (!lock || !cpu_mmu_enabled()) 124 return 0; 125 126 return cpu_spin_lock_xsave(lock); 127 } 128 129 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 130 { 131 if (!lock || !cpu_mmu_enabled()) 132 return; 133 134 cpu_spin_unlock_xrestore(lock, exceptions); 135 } 136 137 static uintptr_t stm32_tamp_base(void) 138 { 139 static struct io_pa_va base = { .pa = TAMP_BASE }; 140 141 return io_pa_or_va(&base); 142 } 143 144 static uintptr_t bkpreg_base(void) 145 { 146 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 147 } 148 149 uintptr_t stm32mp_bkpreg(unsigned int idx) 150 { 151 return bkpreg_base() + (idx * sizeof(uint32_t)); 152 } 153