1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_uart.h> 11 #include <kernel/generic_boot.h> 12 #include <kernel/misc.h> 13 #include <kernel/panic.h> 14 #include <kernel/pm_stubs.h> 15 #include <mm/core_memprot.h> 16 #include <platform_config.h> 17 #include <sm/psci.h> 18 #include <stm32_util.h> 19 #include <tee/entry_std.h> 20 #include <tee/entry_fast.h> 21 #include <trace.h> 22 23 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CONSOLE_UART_SIZE); 24 25 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 26 register_phys_mem(MEM_AREA_IO_SEC, BKP_REGS_BASE, SMALL_PAGE_SIZE); 27 28 static struct console_pdata console_data; 29 30 static void main_fiq(void); 31 32 static const struct thread_handlers handlers = { 33 .std_smc = tee_entry_std, 34 .fast_smc = tee_entry_fast, 35 .nintr = main_fiq, 36 .cpu_on = pm_panic, 37 .cpu_off = pm_panic, 38 .cpu_suspend = pm_panic, 39 .cpu_resume = pm_panic, 40 .system_off = pm_panic, 41 .system_reset = pm_panic, 42 }; 43 44 const struct thread_handlers *generic_boot_get_handlers(void) 45 { 46 return &handlers; 47 } 48 49 #define _ID2STR(id) (#id) 50 #define ID2STR(id) _ID2STR(id) 51 52 static TEE_Result platform_banner(void) 53 { 54 #ifdef CFG_EMBED_DTB 55 IMSG("Platform stm32mp1: flavor %s - DT %s", 56 ID2STR(PLATFORM_FLAVOR), 57 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 58 #else 59 IMSG("Platform stm32mp1: flavor %s - no device tree", 60 ID2STR(PLATFORM_FLAVOR)); 61 #endif 62 63 return TEE_SUCCESS; 64 } 65 service_init(platform_banner); 66 67 void console_init(void) 68 { 69 stm32_uart_init(&console_data, CONSOLE_UART_BASE); 70 register_serial_console(&console_data.chip); 71 } 72 73 /* 74 * GIC init, used also for primary/secondary boot core wake completion 75 */ 76 static struct gic_data gic_data; 77 78 static void main_fiq(void) 79 { 80 gic_it_handle(&gic_data); 81 } 82 83 void main_init_gic(void) 84 { 85 assert(cpu_mmu_enabled()); 86 87 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 88 itr_init(&gic_data.chip); 89 } 90 91 void main_secondary_init_gic(void) 92 { 93 gic_cpu_init(&gic_data); 94 } 95 96 uintptr_t get_gicc_base(void) 97 { 98 uintptr_t pbase = GIC_BASE + GICC_OFFSET; 99 100 if (cpu_mmu_enabled()) 101 return (uintptr_t)phys_to_virt_io(pbase); 102 103 return pbase; 104 } 105 106 uintptr_t get_gicd_base(void) 107 { 108 uintptr_t pbase = GIC_BASE + GICD_OFFSET; 109 110 if (cpu_mmu_enabled()) 111 return (uintptr_t)phys_to_virt_io(pbase); 112 113 return pbase; 114 } 115