riscv: plat-virt: move stack alignment definition

The 16-byte stack alignment is a RISC-V ABI requirement
that applies to all RISC-V platforms. Move this definition
from the virt platform configurat

riscv: plat-virt: move stack alignment definition

The 16-byte stack alignment is a RISC-V ABI requirement
that applies to all RISC-V platforms. Move this definition
from the virt platform configuration to riscv.h.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: kernel: entry.S: remove unused boot_args array

The boot_args array is unused anywhere and its contents
are cleared during the zeroing of the .bss section, so it
serves no purpose. Removing it

riscv: kernel: entry.S: remove unused boot_args array

The boot_args array is unused anywhere and its contents
are cleared during the zeroing of the .bss section, so it
serves no purpose. Removing it simplifies the code.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: imx: disable ELE on i.MX8ULP by default

On i.MX8ULP, there is only one MU to communicate with ELE,
which cannot be dedicated on OP-TEE side all the time.
There may be ELE services running on L

core: imx: disable ELE on i.MX8ULP by default

On i.MX8ULP, there is only one MU to communicate with ELE,
which cannot be dedicated on OP-TEE side all the time.
There may be ELE services running on Linux side, which can
cause conflict with OP-TEE, So disabling ELE by default.
Moreover i.MX8ULP also has CAAM, so HUK and Random number
are coming from CAAM.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rockchip: rk3588: add OTP_S support and HUK

Add OTP_S support for Rockchip rk3588
Add tee_otp_get_hw_unique_key()

Signed-off-by: Ed Tubbs <ectubbs@gmail.com>
Acked-by: Etienne Carriere <etienn

plat-rockchip: rk3588: add OTP_S support and HUK

Add OTP_S support for Rockchip rk3588
Add tee_otp_get_hw_unique_key()

Signed-off-by: Ed Tubbs <ectubbs@gmail.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: pta: fix virt_to_phys() self tests

Only test on VCORE_FREE_* addresses if CFG_DYN_CONFIG=y since those
addresses otherwise are unmapped or even unassigned.

Fixes: a05b3a459a3b ("core: pta: ad

core: pta: fix virt_to_phys() self tests

Only test on VCORE_FREE_* addresses if CFG_DYN_CONFIG=y since those
addresses otherwise are unmapped or even unassigned.

Fixes: a05b3a459a3b ("core: pta: add self tests for virt_to_phys()")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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ta: enable ubsan support for TAs

Introduce CFG_TA_SANITIZE_UNDEFINED config to sanitize trusted
applications. If CFG_TA_SANITIZE_UNDEFINED is set sanitize flags are
propagated to internal TAs (avb,

ta: enable ubsan support for TAs

Introduce CFG_TA_SANITIZE_UNDEFINED config to sanitize trusted
applications. If CFG_TA_SANITIZE_UNDEFINED is set sanitize flags are
propagated to internal TAs (avb, pkcs11, remoteproc, trusted_keys) and
external TAs, which are built with the devkit.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ldelf: enable ubsan support

Ubsan support was previously limited to core code. This commit moves the
ubsan runtime implementation to libutils, making it available for ldelf
and trusted applications.

ldelf: enable ubsan support

Ubsan support was previously limited to core code. This commit moves the
ubsan runtime implementation to libutils, making it available for ldelf
and trusted applications.

As a result, ldelf will now be built with ubsan support when
CFG_CORE_SANITIZE_UNDEFINED is enabled.

Additionally, to avoid potential infinite recursion, ubsan
instrumentation is explicitly disabled for ubsan.c.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: remove THREAD_CORE_LOCAL_STACKCHECK_RECURSION

THREAD_CORE_LOCAL_STACKCHECK_RECURSION was introduced in the commit
b5ec8152f3e5 ("core: arm: refactor boot"). However, clearing the
stackche

core: arm: remove THREAD_CORE_LOCAL_STACKCHECK_RECURSION

THREAD_CORE_LOCAL_STACKCHECK_RECURSION was introduced in the commit
b5ec8152f3e5 ("core: arm: refactor boot"). However, clearing the
stackcheck_recursion flag from assembly during boot isn't needed since
the stack pointer is set up in synch with the recorded information in
thread_core_local. So remove the unnecessary clearing and remove
THREAD_CORE_LOCAL_STACKCHECK_RECURSION.

Reported-by: Alvin Chang <alvinga@andestech.com>
Closes: https://github.com/OP-TEE/optee_os/commit/b5ec8152f3e5ad8cc111952f0483f5cf903aac7c#r154088026
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: enable SCMI PERF for stm32mp13

Enable CFG_SCMI_MSG_PERF_DOMAIN for STM32MP13 that is used
to provide CPU OPP to linux.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Rev

plat-stm32mp1: conf: enable SCMI PERF for stm32mp13

Enable CFG_SCMI_MSG_PERF_DOMAIN for STM32MP13 that is used
to provide CPU OPP to linux.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: SCMI performance domain for CPU DVFS

Implement scmi-msg perf protocol platform handlers to drive CPU
voltage/frequency scaling support.

Co-developed-by: Etienne Carriere <etienne.car

plat-stm32mp1: SCMI performance domain for CPU DVFS

Implement scmi-msg perf protocol platform handlers to drive CPU
voltage/frequency scaling support.

Co-developed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: scmi-msg: support performance domains for DVFS

Implement some of the SCMI performance domain management messages
in scmi-msg drivers to support basic DVFS scenario.

Co-developed-by: Etienn

drivers: scmi-msg: support performance domains for DVFS

Implement some of the SCMI performance domain management messages
in scmi-msg drivers to support basic DVFS scenario.

Co-developed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_cpu_opp: skip OPP unsupported by SOC

Use device ID to remove not supported OPP.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@fos

drivers: stm32_cpu_opp: skip OPP unsupported by SOC

Use device ID to remove not supported OPP.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>

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dts: stm32: describe supported-hw on CPU OPP for STM32MP13

Describe supported hardware for each OPP.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Acked-by: Etienne Carriere <etienne.carrie

dts: stm32: describe supported-hw on CPU OPP for STM32MP13

Describe supported hardware for each OPP.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: chip and STM32MP15 platform identification

New platform function to get the chip identification using
DBGMCU SoC register.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>

plat-stm32mp1: chip and STM32MP15 platform identification

New platform function to get the chip identification using
DBGMCU SoC register.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: retrieve chip id from syscfg

Chip ID is read from SYSCFG. Add the associated read
function and new CHIP IDs.

Use the chip id to dynamically detect the CRYPTO hardware
support, the se

plat-stm32mp1: retrieve chip id from syscfg

Chip ID is read from SYSCFG. Add the associated read
function and new CHIP IDs.

Use the chip id to dynamically detect the CRYPTO hardware
support, the second CPU core, and CPU OPP.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_cpu_opp: skip OPP with unsupported voltage

Remove operating points that could not be handled
by the regulator supplying the CPU.

Signed-off-by: Patrick Delaunay <patrick.delaunay@fos

drivers: stm32_cpu_opp: skip OPP with unsupported voltage

Remove operating points that could not be handled
by the regulator supplying the CPU.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: default enable CFG_STM32_CPU_OPP for STM32MP13

Enable CFG_STM32_CPU_OPP for STM32MP13 and increase
CFG_STM32MP_OPP_COUNT to 3 OPP.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.co

plat-stm32mp1: default enable CFG_STM32_CPU_OPP for STM32MP13

Enable CFG_STM32_CPU_OPP for STM32MP13 and increase
CFG_STM32MP_OPP_COUNT to 3 OPP.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: describe CPU OPP for STM32MP13

Describe CPU operating points for STM32MP13 boards.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@fos

dts: stm32: describe CPU OPP for STM32MP13

Describe CPU operating points for STM32MP13 boards.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>

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drivers: add stm32 CPU DVFS driver

drivers/cpu_opp.c implements dynamic voltage and frequency
scaling for the CPU.
It is used at boot time to set an higher operating point than
the one used to boot.

drivers: add stm32 CPU DVFS driver

drivers/cpu_opp.c implements dynamic voltage and frequency
scaling for the CPU.
It is used at boot time to set an higher operating point than
the one used to boot.
It will be used by the SCMI performance service.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: boot: fix calling page_alloc_init()

The functions page_alloc_init() and nex_page_alloc_init() depends on
MEM_AREA_TEE_DYN_VASPACE and MEM_AREA_NEX_DYN_VASPACE, but the memory
areas are on

core: arm: boot: fix calling page_alloc_init()

The functions page_alloc_init() and nex_page_alloc_init() depends on
MEM_AREA_TEE_DYN_VASPACE and MEM_AREA_NEX_DYN_VASPACE, but the memory
areas are only available with CFG_DYN_CONFIG so check that before
calling the functions.

Fixes: 0e12fb0c2d75 ("core: arm: boot: call page_alloc_init()")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: fix CFG_BOOT_INIT_THREAD_CORE_LOCAL0

CFG_BOOT_INIT_THREAD_CORE_LOCAL0 is misleading since it's concerning the
core id of the boot CPU. So rename the configuration flag to
CFG_BOOT_INIT_CURRENT

core: fix CFG_BOOT_INIT_THREAD_CORE_LOCAL0

CFG_BOOT_INIT_THREAD_CORE_LOCAL0 is misleading since it's concerning the
core id of the boot CPU. So rename the configuration flag to
CFG_BOOT_INIT_CURRENT_THREAD_CORE_LOCAL and update the code as needed.
Only thread_init_thread_core_local() has a change of behaviour where the
boot CPU now can have any core id.

Fixes: b5ec8152f3e5 ("core: arm: refactor boot")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: disable unused i2c1 and i2c2

i2c1 and i2c2 on Avenger96 board are not consumed by OP-TEE,
therefore they can be disabled.

Link: https://github.com/OP-TEE/optee_os/issues/7296
Acked-by:

dts: stm32: disable unused i2c1 and i2c2

i2c1 and i2c2 on Avenger96 board are not consumed by OP-TEE,
therefore they can be disabled.

Link: https://github.com/OP-TEE/optee_os/issues/7296
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Daniel Lang <ldaniell14260@gmail.com>

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core: arm: boot: call page_alloc_init()

Call page_alloc_init()/nex_page_alloc_init() from init_primary() after
unused boot memory has been released. virt_guest_created() calls
page_alloc_init().

Th

core: arm: boot: call page_alloc_init()

Call page_alloc_init()/nex_page_alloc_init() from init_primary() after
unused boot memory has been released. virt_guest_created() calls
page_alloc_init().

This allows virt_page_alloc() to be used instead of boot_mem_alloc() now
that boot_mem_alloc() can't be used any longer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: add virt_page_alloc()

Add virt_page_alloc() to allocate memory from physical pool and map it
in a virtual address pool.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-

core: mm: add virt_page_alloc()

Add virt_page_alloc() to allocate memory from physical pool and map it
in a virtual address pool.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: add phys_mem_alloc_flags()

Add phys_mem_alloc_flags() taking MAF_* flags to control memory
allocation. The new flag MAF_CORE_MEM behaves like
{nex_,}phys_mem_core_alloc(), if the flag is

core: mm: add phys_mem_alloc_flags()

Add phys_mem_alloc_flags() taking MAF_* flags to control memory
allocation. The new flag MAF_CORE_MEM behaves like
{nex_,}phys_mem_core_alloc(), if the flag is absent it becomes
{nex_,}phys_mem_ta_alloc().

The MAF_NEX flag selects Nexus memory.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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