drivers: clk: stm32mp1: fix index ordering parent clock array

Fix order in stm32mp1_clk_parent_name[].

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etie

drivers: clk: stm32mp1: fix index ordering parent clock array

Fix order in stm32mp1_clk_parent_name[].

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: stm32mp1: fix HCLK6 parent clock

Fix get_parent_id_parent() the return HCLK6 parent clock that previous
implementation forbade.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com

drivers: clk: stm32mp1: fix HCLK6 parent clock

Fix get_parent_id_parent() the return HCLK6 parent clock that previous
implementation forbade.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: stm32mp1: fix BRSRAM parent clock reference

Fix reference to BKPSRAM parent clock for platform stm32mp1. No
functional change as parent clock reference used prior the change
(_PCLK5) l

drivers: clk: stm32mp1: fix BRSRAM parent clock reference

Fix reference to BKPSRAM parent clock for platform stm32mp1. No
functional change as parent clock reference used prior the change
(_PCLK5) led to the same parent clock rate value.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: stm32mp15: support RTC and MPU clocks

Add RTC and MPU clocks support to platform stm32mp1.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <et

drivers: clk: stm32mp15: support RTC and MPU clocks

Add RTC and MPU clocks support to platform stm32mp1.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: stm32mp15: split oscillator and parent clock IDs

Use specific identifiers for root oscillators (prefixed OSC_) while
parent clock IDs are left unchanged.

Reviewed-by: Lionel Debieve <

drivers: clk: stm32mp15: split oscillator and parent clock IDs

Use specific identifiers for root oscillators (prefixed OSC_) while
parent clock IDs are left unchanged.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: crypto: TEE_PopulateTransientObject() should check key size

The GlobalPlatform TEE Internal Core API specification specifies the
panic reasons for TEE_PopulateTransientObject() as follows:
"If

core: crypto: TEE_PopulateTransientObject() should check key size

The GlobalPlatform TEE Internal Core API specification specifies the
panic reasons for TEE_PopulateTransientObject() as follows:
"If the implementation detects any other error associated with this
function that is not explicitly associated with a defined return code
for this function.". There is no explicit return code for the case of
an attribute that would be an invalid key length for the specified
algorithm, but it seems that panicking the TA would be permitted and
even desirable in order to prevent other issues with subsequent calls
using such a key.

Add a key size check to tee_svc_cryp_obj_populate_type() so that
syscall_cryp_obj_populate() will return TEE_ERROR_BAD_PARAMETER when
a key of invalid length is supplied. This error code is converted into
a panic by TEE_PopulateTransientObject().

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: crypto: DSA key size is given by TEE_ATTR_DSA_PRIME

The size of a DSA key is the size of the prime number (p) and not the
size of the subprime (q). Therefore the size indicator flag in the
def

core: crypto: DSA key size is given by TEE_ATTR_DSA_PRIME

The size of a DSA key is the size of the prime number (p) and not the
size of the subprime (q). Therefore the size indicator flag in the
definition of DSA cryptographic object attributes should be associated
with TEE_ATTR_DSA_PRIME, not with TEE_ATTR_DSA_SUBPRIME.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: caam: add imx8ulp CAAM HAL

Add imx8ulp CAAM HAL functions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

core: imx: add support for i.MX8ULP

Add support for i.MX8ULP platform.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

drivers: caam: disable the use of interrupts for some platforms

On some i.MX platforms, all CAAM JRs share the same line of interrupts.
To avoid conflicts with the other job ring owners, skip the
en

drivers: caam: disable the use of interrupts for some platforms

On some i.MX platforms, all CAAM JRs share the same line of interrupts.
To avoid conflicts with the other job ring owners, skip the
enable/disable of job ring interruptions in OP-TEE CAAM driver.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: use a paged scattered array for DT drivers list

Fixes macro DEFINE_DT_DRIVER() to use SCATTERED_ARRAY_DEFINE_PG_ITEM()
that defines a pageable resources whereas SCATTERED_ARRAY_DEFINE_ITEM()
a

core: use a paged scattered array for DT drivers list

Fixes macro DEFINE_DT_DRIVER() to use SCATTERED_ARRAY_DEFINE_PG_ITEM()
that defines a pageable resources whereas SCATTERED_ARRAY_DEFINE_ITEM()
assumes array and its dependencies must be linked in the rodata_init
section. Indeed DT driver probing is done after pager is initialized.

Fixes: 61bdedea9452 ("core: define DT drivers using scattered arrays")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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crypto: drivers: se050: ecc sign/verify padding

Pad small messages with zeroes during sign/verify.

Fixes xtest pkcs11_1019.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienn

crypto: drivers: se050: ecc sign/verify padding

Pad small messages with zeroes during sign/verify.

Fixes xtest pkcs11_1019.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: plat-ls: ls1028a: fix uart address

Fix UART0_BASE address for LS1028 platform

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

drivers: crypto: se050: build Plug-and-Trust using the TEE makefiles

Building the Plug-and-Trust library required building OP-TEE first in
order to get some architecture specific definitions.
This m

drivers: crypto: se050: build Plug-and-Trust using the TEE makefiles

Building the Plug-and-Trust library required building OP-TEE first in
order to get some architecture specific definitions.
This makes the integration with yocto metas unnecessarily complex.

The following commit simplifies the build sequence: the user would
need to clone the Plug-and-Trust tree [1] to an accessible location in
the filesystem and then build OP-TEE as usual passing the path to the
Plug-and-Trust tree in CFG_NXP_SE05X_PLUG_AND_TRUST.

[1] https://github.com/foundriesio/plug-and-trust.git

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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core: spmc: Fix flags and tag in retrieve request

Inside check_retrieve_request() the flags and tag where swapped.
Store them in the correct variable.

Fixes: de66193d9849 ("core: FF-A: ADD FFA_MEM_

core: spmc: Fix flags and tag in retrieve request

Inside check_retrieve_request() the flags and tag where swapped.
Store them in the correct variable.

Fixes: de66193d9849 ("core: FF-A: ADD FFA_MEM_RETRIEVE for SPs")
Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: allow non-secure to read DDR registers

Changes stm32mp1 ETZPC configuration to allow non-secure read access
to DDRCTRL and DDRPHYC interface register. This change will be needed
by ne

plat-stm32mp1: allow non-secure to read DDR registers

Changes stm32mp1 ETZPC configuration to allow non-secure read access
to DDRCTRL and DDRPHYC interface register. This change will be needed
by next U-Boot release v2022.04 since merge of [1] in order to
dynamically compute the DDR size.

Link: [1] https://source.denx.de/u-boot/u-boot/-/commit/d72e7bbe7c2841f161848d57b723495a731d0121
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: imx: add support for i.MX8DXL

Add the i.MX 8DXL SoC support.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

core: imx: crypto_conf: change CAAM default job ring for mscale platforms

Change the default CAAM job ring index from 0 to 2 for the following
platforms:
* imx8mmevk
* imx8mnevk
* imx8mpevk
* im

core: imx: crypto_conf: change CAAM default job ring for mscale platforms

Change the default CAAM job ring index from 0 to 2 for the following
platforms:
* imx8mmevk
* imx8mnevk
* imx8mpevk
* imx8mqevk
It leaves JR0 available for the HAB to authenticate and decrypt boot
images.

Fixes: 2d7a8964 ("driver: implement CAAM driver")
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: imx_wdog: fix compilation warning on watchdog driver

$ make PLATFORM=imx-mx7ulpevk CFG_DT=n
core/drivers/imx_wdog.c:42:13: warning: ext_reset_output defined but not used [-Wunused-variable]

drivers: imx_wdog: fix compilation warning on watchdog driver

$ make PLATFORM=imx-mx7ulpevk CFG_DT=n
core/drivers/imx_wdog.c:42:13: warning: ext_reset_output defined but not used [-Wunused-variable]
42 | static bool ext_reset_output;
| ^~~~~~~~~~~~~~~~

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: imx_wdog: fix compilation watchdog driver on mx7ulp

Define WDOG_BASE and WDOG_SIZE value for mx7ulp platform.

$ make PLATFORM=imx-mx7ulpevk CFG_DT=n
core/drivers/imx_wdog.c:151:42: error:

drivers: imx_wdog: fix compilation watchdog driver on mx7ulp

Define WDOG_BASE and WDOG_SIZE value for mx7ulp platform.

$ make PLATFORM=imx-mx7ulpevk CFG_DT=n
core/drivers/imx_wdog.c:151:42: error: WDOG_BASE undeclared here (not in a function); did you mean WDOG_CS?
151 | register_phys_mem_pgdir(MEM_AREA_IO_SEC, WDOG_BASE, CORE_MMU_PGDIR_SIZE);
|

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: enable the CAAM on imx8q platforms

Enabled the CAAM on the following platforms:
* imx8qm
* imx8qxp

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jero

core: imx: enable the CAAM on imx8q platforms

Enabled the CAAM on the following platforms:
* imx8qm
* imx8qxp

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: fix aligned buffer allocation for DMA

For aligned memory buffer and DMA CAAM access, the allocated buffer size
must be rounded up to a certain value depending of the DMA behaviour on

drivers: caam: fix aligned buffer allocation for DMA

For aligned memory buffer and DMA CAAM access, the allocated buffer size
must be rounded up to a certain value depending of the DMA behaviour on
the platform.
For the imx8qm/qxp, the allocated aligned buffer size must be rounded up
to 4 bytes.

Signed-off-by: Remi Koman <remi.koman@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: set CAAM configuration for imx8q platforms

Define the JR block size, JR index and the JR interruption number for
the following platforms:
* imx8qm
* imx8qxp

Signed-off-by: Clement Faur

core: imx: set CAAM configuration for imx8q platforms

Define the JR block size, JR index and the JR interruption number for
the following platforms:
* imx8qm
* imx8qxp

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: clk: move stm32mp1 clock driver to clock drivers directory

Moves stm32mp15 clock driver to core/drivers/clk and adds configuration
switch CFG_STM32MP15_CLK to embed or not the driver. Platf

drivers: clk: move stm32mp1 clock driver to clock drivers directory

Moves stm32mp15 clock driver to core/drivers/clk and adds configuration
switch CFG_STM32MP15_CLK to embed or not the driver. Platform stm32mp1
mandates CFG_STM32MP15_CLK=y.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: mandate generic clock driver support

Changes stm32mp1 platform to mandate use of the generic clock driver
(CFG_DRVIERS_CLK=y). The platform clock driver implementation is
updated to r

plat-stm32mp1: mandate generic clock driver support

Changes stm32mp1 platform to mandate use of the generic clock driver
(CFG_DRVIERS_CLK=y). The platform clock driver implementation is
updated to remove all implementation related to when CFG_DRVIERS_CLK
is disabled.

CFG_DRIVERS_CLK_DT must be disabled if there is no embedded DTB for
that platform.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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