1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0+) 2 /* 3 * Copyright (C) 2018-2019, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/stm32mp1_rcc.h> 9 #include <drivers/clk.h> 10 #include <drivers/clk_dt.h> 11 #include <dt-bindings/clock/stm32mp1-clks.h> 12 #include <initcall.h> 13 #include <io.h> 14 #include <keep.h> 15 #include <kernel/dt.h> 16 #include <kernel/boot.h> 17 #include <kernel/panic.h> 18 #include <kernel/spinlock.h> 19 #include <libfdt.h> 20 #include <platform_config.h> 21 #include <stdio.h> 22 #include <stm32_util.h> 23 #include <trace.h> 24 #include <util.h> 25 26 /* Identifiers for root oscillators */ 27 enum stm32mp_osc_id { 28 OSC_HSI, 29 OSC_HSE, 30 OSC_CSI, 31 OSC_LSI, 32 OSC_LSE, 33 OSC_I2S_CKIN, 34 OSC_USB_PHY_48, 35 NB_OSC, 36 _UNKNOWN_OSC_ID = 0xffU 37 }; 38 39 /* Identifiers for parent clocks */ 40 enum stm32mp1_parent_id { 41 _HSI, 42 _HSE, 43 _CSI, 44 _LSI, 45 _LSE, 46 _I2S_CKIN, 47 _USB_PHY_48, 48 _HSI_KER, 49 _HSE_KER, 50 _HSE_KER_DIV2, 51 _CSI_KER, 52 _PLL1_P, 53 _PLL1_Q, 54 _PLL1_R, 55 _PLL2_P, 56 _PLL2_Q, 57 _PLL2_R, 58 _PLL3_P, 59 _PLL3_Q, 60 _PLL3_R, 61 _PLL4_P, 62 _PLL4_Q, 63 _PLL4_R, 64 _ACLK, 65 _PCLK1, 66 _PCLK2, 67 _PCLK3, 68 _PCLK4, 69 _PCLK5, 70 _HCLK5, 71 _HCLK6, 72 _HCLK2, 73 _CK_PER, 74 _CK_MPU, 75 _CK_MCU, 76 _PARENT_NB, 77 _UNKNOWN_ID = 0xff, 78 }; 79 80 /* 81 * Identifiers for parent clock selectors. 82 * This enum lists only the parent clocks we are interested in. 83 */ 84 enum stm32mp1_parent_sel { 85 _STGEN_SEL, 86 _I2C46_SEL, 87 _SPI6_SEL, 88 _USART1_SEL, 89 _RNG1_SEL, 90 _UART6_SEL, 91 _UART24_SEL, 92 _UART35_SEL, 93 _UART78_SEL, 94 _AXISS_SEL, 95 _MCUSS_SEL, 96 _USBPHY_SEL, 97 _USBO_SEL, 98 _RTC_SEL, 99 _PARENT_SEL_NB, 100 _UNKNOWN_SEL = 0xff, 101 }; 102 103 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 104 [_HSE] = CK_HSE, 105 [_HSI] = CK_HSI, 106 [_CSI] = CK_CSI, 107 [_LSE] = CK_LSE, 108 [_LSI] = CK_LSI, 109 [_I2S_CKIN] = _UNKNOWN_ID, 110 [_USB_PHY_48] = _UNKNOWN_ID, 111 [_HSI_KER] = CK_HSI, 112 [_HSE_KER] = CK_HSE, 113 [_HSE_KER_DIV2] = CK_HSE_DIV2, 114 [_CSI_KER] = CK_CSI, 115 [_PLL1_P] = PLL1_P, 116 [_PLL1_Q] = PLL1_Q, 117 [_PLL1_R] = PLL1_R, 118 [_PLL2_P] = PLL2_P, 119 [_PLL2_Q] = PLL2_Q, 120 [_PLL2_R] = PLL2_R, 121 [_PLL3_P] = PLL3_P, 122 [_PLL3_Q] = PLL3_Q, 123 [_PLL3_R] = PLL3_R, 124 [_PLL4_P] = PLL4_P, 125 [_PLL4_Q] = PLL4_Q, 126 [_PLL4_R] = PLL4_R, 127 [_ACLK] = CK_AXI, 128 [_PCLK1] = CK_AXI, 129 [_PCLK2] = CK_AXI, 130 [_PCLK3] = CK_AXI, 131 [_PCLK4] = CK_AXI, 132 [_PCLK5] = CK_AXI, 133 [_HCLK5] = CK_AXI, 134 [_HCLK6] = CK_AXI, 135 [_HCLK2] = CK_AXI, 136 [_CK_PER] = CK_PER, 137 [_CK_MPU] = CK_MPU, 138 [_CK_MCU] = CK_MCU, 139 }; 140 141 static enum stm32mp1_parent_id osc_id2parent_id(enum stm32mp_osc_id osc_id) 142 { 143 assert(osc_id >= OSC_HSI && osc_id < NB_OSC); 144 COMPILE_TIME_ASSERT((int)OSC_HSI == (int)_HSI && 145 (int)OSC_HSE == (int)_HSE && 146 (int)OSC_CSI == (int)_CSI && 147 (int)OSC_LSI == (int)_LSI && 148 (int)OSC_LSE == (int)_LSE && 149 (int)OSC_I2S_CKIN == (int)_I2S_CKIN && 150 (int)OSC_USB_PHY_48 == (int)_USB_PHY_48); 151 152 return (enum stm32mp1_parent_id)osc_id; 153 } 154 155 static enum stm32mp1_parent_id clock_id2parent_id(unsigned long id) 156 { 157 size_t n = 0; 158 159 COMPILE_TIME_ASSERT(STM32MP1_LAST_CLK < _UNKNOWN_ID); 160 161 for (n = 0; n < ARRAY_SIZE(parent_id_clock_id); n++) 162 if (parent_id_clock_id[n] == id) 163 return (enum stm32mp1_parent_id)n; 164 165 return _UNKNOWN_ID; 166 } 167 168 /* Identifiers for PLLs and their configuration resources */ 169 enum stm32mp1_pll_id { 170 _PLL1, 171 _PLL2, 172 _PLL3, 173 _PLL4, 174 _PLL_NB 175 }; 176 177 enum stm32mp1_div_id { 178 _DIV_P, 179 _DIV_Q, 180 _DIV_R, 181 _DIV_NB, 182 }; 183 184 enum stm32mp1_plltype { 185 PLL_800, 186 PLL_1600, 187 PLL_TYPE_NB 188 }; 189 190 /* 191 * Clock generic gates clocks which state is controlled by a single RCC bit 192 * 193 * @offset: RCC register byte offset from RCC base where clock is controlled 194 * @bit: Bit position in the RCC 32bit register 195 * @clock_id: Identifier used for the clock in the clock driver API 196 * @set_clr: Non-null if and only-if RCC register is a CLEAR/SET register 197 * (CLEAR register is at offset RCC_MP_ENCLRR_OFFSET from SET register) 198 * @secure: One of N_S or SEC, defined below 199 * @sel: _UNKNOWN_ID (fixed parent) or reference to parent clock selector 200 * (8bit storage of ID from enum stm32mp1_parent_sel) 201 * @fixed: _UNKNOWN_ID (selectable paranet) or reference to parent clock 202 * (8bit storage of ID from enum stm32mp1_parent_id) 203 */ 204 struct stm32mp1_clk_gate { 205 uint16_t offset; 206 uint8_t bit; 207 uint8_t clock_id; 208 uint8_t set_clr; 209 uint8_t secure; 210 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 211 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 212 }; 213 214 /* Parent clock selection: select register info, parent clocks references */ 215 struct stm32mp1_clk_sel { 216 uint16_t offset; 217 uint8_t src; 218 uint8_t msk; 219 uint8_t nb_parent; 220 const uint8_t *parent; 221 }; 222 223 #define REFCLK_SIZE 4 224 /* PLL control: type, control register offsets, up-to-4 selectable parent */ 225 struct stm32mp1_clk_pll { 226 enum stm32mp1_plltype plltype; 227 uint16_t rckxselr; 228 uint16_t pllxcfgr1; 229 uint16_t pllxcfgr2; 230 uint16_t pllxfracr; 231 uint16_t pllxcr; 232 uint16_t pllxcsgr; 233 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 234 }; 235 236 #define N_S 0 /* Non-secure can access RCC interface */ 237 #define SEC 1 /* RCC[TZEN] protects RCC interface */ 238 239 /* Clocks with selectable source and not set/clr register access */ 240 #define _CLK_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 241 { \ 242 .offset = (_offset), \ 243 .bit = (_bit), \ 244 .clock_id = (_clock_id), \ 245 .set_clr = 0, \ 246 .secure = (_sec), \ 247 .sel = (_parent_sel), \ 248 .fixed = _UNKNOWN_ID, \ 249 } 250 251 /* Clocks with fixed source and not set/clr register access */ 252 #define _CLK_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 253 { \ 254 .offset = (_offset), \ 255 .bit = (_bit), \ 256 .clock_id = (_clock_id), \ 257 .set_clr = 0, \ 258 .secure = (_sec), \ 259 .sel = _UNKNOWN_SEL, \ 260 .fixed = (_parent), \ 261 } 262 263 /* Clocks with selectable source and set/clr register access */ 264 #define _CLK_SC_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 265 { \ 266 .offset = (_offset), \ 267 .bit = (_bit), \ 268 .clock_id = (_clock_id), \ 269 .set_clr = 1, \ 270 .secure = (_sec), \ 271 .sel = (_parent_sel), \ 272 .fixed = _UNKNOWN_ID, \ 273 } 274 275 /* Clocks with fixed source and set/clr register access */ 276 #define _CLK_SC_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 277 { \ 278 .offset = (_offset), \ 279 .bit = (_bit), \ 280 .clock_id = (_clock_id), \ 281 .set_clr = 1, \ 282 .secure = (_sec), \ 283 .sel = _UNKNOWN_SEL, \ 284 .fixed = (_parent), \ 285 } 286 287 /* 288 * Clocks with selectable source and set/clr register access 289 * and enable bit position defined by a label (argument _bit) 290 */ 291 #define _CLK_SC2_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 292 { \ 293 .offset = (_offset), \ 294 .clock_id = (_clock_id), \ 295 .bit = _offset ## _ ## _bit ## _POS, \ 296 .set_clr = 1, \ 297 .secure = (_sec), \ 298 .sel = (_parent_sel), \ 299 .fixed = _UNKNOWN_ID, \ 300 } 301 #define _CLK_SC2_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 302 { \ 303 .offset = (_offset), \ 304 .clock_id = (_clock_id), \ 305 .bit = _offset ## _ ## _bit ## _POS, \ 306 .set_clr = 1, \ 307 .secure = (_sec), \ 308 .sel = _UNKNOWN_SEL, \ 309 .fixed = (_parent), \ 310 } 311 312 #define _CLK_PARENT(idx, _offset, _src, _mask, _parent) \ 313 [(idx)] = { \ 314 .offset = (_offset), \ 315 .src = (_src), \ 316 .msk = (_mask), \ 317 .parent = (_parent), \ 318 .nb_parent = ARRAY_SIZE(_parent) \ 319 } 320 321 #define _CLK_PLL(_idx, _type, _off1, _off2, _off3, _off4, \ 322 _off5, _off6, _p1, _p2, _p3, _p4) \ 323 [(_idx)] = { \ 324 .plltype = (_type), \ 325 .rckxselr = (_off1), \ 326 .pllxcfgr1 = (_off2), \ 327 .pllxcfgr2 = (_off3), \ 328 .pllxfracr = (_off4), \ 329 .pllxcr = (_off5), \ 330 .pllxcsgr = (_off6), \ 331 .refclk[0] = (_p1), \ 332 .refclk[1] = (_p2), \ 333 .refclk[2] = (_p3), \ 334 .refclk[3] = (_p4), \ 335 } 336 337 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 338 339 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 340 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 341 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 342 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 343 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 344 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 345 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 346 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 347 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 348 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 349 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 351 352 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, SPI6EN, SPI6_K, _SPI6_SEL), 353 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C4EN, I2C4_K, _I2C46_SEL), 354 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C6EN, I2C6_K, _I2C46_SEL), 355 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, USART1EN, USART1_K, _USART1_SEL), 356 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, RTCAPBEN, RTCAPB, _PCLK5), 357 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC1EN, TZC1, _PCLK5), 358 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC2EN, TZC2, _PCLK5), 359 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZPCEN, TZPC, _PCLK5), 360 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, IWDG1APBEN, IWDG1, _PCLK5), 361 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, BSECEN, BSEC, _PCLK5), 362 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, STGENEN, STGEN_K, _STGEN_SEL), 363 364 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, GPIOZEN, GPIOZ, _HCLK5), 365 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, CRYP1EN, CRYP1, _HCLK5), 366 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, HASH1EN, HASH1, _HCLK5), 367 _CLK_SC2_SELEC(SEC, RCC_MP_AHB5ENSETR, RNG1EN, RNG1_K, _RNG1_SEL), 368 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, BKPSRAMEN, BKPSRAM, _PCLK5), 369 370 _CLK_SC2_FIXED(SEC, RCC_MP_TZAHB6ENSETR, MDMA, MDMA, _HCLK6), 371 372 _CLK_SELEC(SEC, RCC_BDCR, RCC_BDCR_RTCCKEN_POS, RTC, _RTC_SEL), 373 374 /* Non-secure clocks */ 375 #ifdef CFG_WITH_NSEC_GPIOS 376 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_ID), 377 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_ID), 378 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_ID), 379 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_ID), 380 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_ID), 381 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_ID), 382 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_ID), 383 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_ID), 384 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_ID), 385 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_ID), 386 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_ID), 387 #endif 388 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 389 #ifdef CFG_WITH_NSEC_UARTS 390 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 391 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 392 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 393 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 394 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 395 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 396 #endif 397 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 398 #ifdef CFG_WITH_NSEC_UARTS 399 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 400 #endif 401 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 402 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 403 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 404 405 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 406 }; 407 DECLARE_KEEP_PAGER(stm32mp1_clk_gate); 408 409 const uint8_t stm32mp1_clk_on[] = { 410 CK_HSE, CK_CSI, CK_LSI, CK_LSE, CK_HSI, CK_HSE_DIV2, 411 PLL1_P, PLL1_Q, PLL1_R, PLL2_P, PLL2_Q, PLL2_R, PLL3_P, PLL3_Q, PLL3_R, 412 CK_AXI, CK_MPU, CK_MCU, 413 }; 414 415 /* Parents for secure aware clocks in the xxxSELR value ordering */ 416 static const uint8_t stgen_parents[] = { 417 _HSI_KER, _HSE_KER 418 }; 419 420 static const uint8_t i2c46_parents[] = { 421 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 422 }; 423 424 static const uint8_t spi6_parents[] = { 425 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 426 }; 427 428 static const uint8_t usart1_parents[] = { 429 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 430 }; 431 432 static const uint8_t rng1_parents[] = { 433 _CSI, _PLL4_R, _LSE, _LSI 434 }; 435 436 /* Parents for (some) non-secure clocks */ 437 #ifdef CFG_WITH_NSEC_UARTS 438 static const uint8_t uart6_parents[] = { 439 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 440 }; 441 442 static const uint8_t uart234578_parents[] = { 443 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 444 }; 445 #endif 446 447 static const uint8_t axiss_parents[] = { 448 _HSI, _HSE, _PLL2_P 449 }; 450 451 static const uint8_t mcuss_parents[] = { 452 _HSI, _HSE, _CSI, _PLL3_P 453 }; 454 455 static const uint8_t rtc_parents[] = { 456 _UNKNOWN_ID, _LSE, _LSI, _HSE 457 }; 458 459 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 460 /* Secure aware clocks */ 461 _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 462 _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 463 _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents), 464 _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents), 465 _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents), 466 _CLK_PARENT(_RTC_SEL, RCC_BDCR, 0, 0x3, rtc_parents), 467 /* Always non-secure clocks (maybe used in some way in secure world) */ 468 #ifdef CFG_WITH_NSEC_UARTS 469 _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 470 _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents), 471 _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents), 472 _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents), 473 #endif 474 _CLK_PARENT(_AXISS_SEL, RCC_ASSCKSELR, 0, 0x3, axiss_parents), 475 _CLK_PARENT(_MCUSS_SEL, RCC_MSSCKSELR, 0, 0x3, mcuss_parents), 476 }; 477 478 /* PLLNCFGR2 register divider by output */ 479 static const uint8_t pllncfgr2[_DIV_NB] = { 480 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 481 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 482 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 483 }; 484 485 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 486 _CLK_PLL(_PLL1, PLL_1600, 487 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 488 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 489 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 490 _CLK_PLL(_PLL2, PLL_1600, 491 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 492 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 493 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 494 _CLK_PLL(_PLL3, PLL_800, 495 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 496 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 497 OSC_HSI, OSC_HSE, OSC_CSI, _UNKNOWN_OSC_ID), 498 _CLK_PLL(_PLL4, PLL_800, 499 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 500 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 501 OSC_HSI, OSC_HSE, OSC_CSI, OSC_I2S_CKIN), 502 }; 503 504 /* Prescaler table lookups for clock computation */ 505 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 506 static const uint8_t stm32mp1_mcu_div[16] = { 507 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 508 }; 509 510 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 511 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 512 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 513 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 514 0, 1, 2, 3, 4, 4, 4, 4 515 }; 516 517 /* div = /1 /2 /3 /4 */ 518 static const uint8_t stm32mp1_axi_div[8] = { 519 1, 2, 3, 4, 4, 4, 4, 4 520 }; 521 522 static const char __maybe_unused *const stm32mp1_clk_parent_name[_PARENT_NB] = { 523 [_HSI] = "HSI", 524 [_HSE] = "HSE", 525 [_CSI] = "CSI", 526 [_LSI] = "LSI", 527 [_LSE] = "LSE", 528 [_I2S_CKIN] = "I2S_CKIN", 529 [_HSI_KER] = "HSI_KER", 530 [_HSE_KER] = "HSE_KER", 531 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 532 [_CSI_KER] = "CSI_KER", 533 [_PLL1_P] = "PLL1_P", 534 [_PLL1_Q] = "PLL1_Q", 535 [_PLL1_R] = "PLL1_R", 536 [_PLL2_P] = "PLL2_P", 537 [_PLL2_Q] = "PLL2_Q", 538 [_PLL2_R] = "PLL2_R", 539 [_PLL3_P] = "PLL3_P", 540 [_PLL3_Q] = "PLL3_Q", 541 [_PLL3_R] = "PLL3_R", 542 [_PLL4_P] = "PLL4_P", 543 [_PLL4_Q] = "PLL4_Q", 544 [_PLL4_R] = "PLL4_R", 545 [_ACLK] = "ACLK", 546 [_PCLK1] = "PCLK1", 547 [_PCLK2] = "PCLK2", 548 [_PCLK3] = "PCLK3", 549 [_PCLK4] = "PCLK4", 550 [_PCLK5] = "PCLK5", 551 [_HCLK5] = "HCLK5", 552 [_HCLK6] = "HCLK6", 553 [_HCLK2] = "HCLK2", 554 [_CK_PER] = "CK_PER", 555 [_CK_MPU] = "CK_MPU", 556 [_CK_MCU] = "CK_MCU", 557 [_USB_PHY_48] = "USB_PHY_48", 558 }; 559 560 /* 561 * Oscillator frequency in Hz. This array shall be initialized 562 * according to platform. 563 */ 564 static unsigned long stm32mp1_osc[NB_OSC]; 565 566 static unsigned long osc_frequency(enum stm32mp_osc_id idx) 567 { 568 if (idx >= ARRAY_SIZE(stm32mp1_osc)) { 569 DMSG("clk id %d not found", idx); 570 return 0; 571 } 572 573 return stm32mp1_osc[idx]; 574 } 575 576 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 577 { 578 return &stm32mp1_clk_gate[idx]; 579 } 580 581 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 582 { 583 return &stm32mp1_clk_sel[idx]; 584 } 585 586 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 587 { 588 return &stm32mp1_clk_pll[idx]; 589 } 590 591 static int stm32mp1_clk_get_gated_id(unsigned long id) 592 { 593 unsigned int i = 0; 594 595 for (i = 0; i < NB_GATES; i++) 596 if (gate_ref(i)->clock_id == id) 597 return i; 598 599 DMSG("clk id %lu not found", id); 600 return -1; 601 } 602 603 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 604 { 605 return (enum stm32mp1_parent_sel)gate_ref(i)->sel; 606 } 607 608 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 609 { 610 return (enum stm32mp1_parent_id)gate_ref(i)->fixed; 611 } 612 613 static int stm32mp1_clk_get_parent(unsigned long id) 614 { 615 const struct stm32mp1_clk_sel *sel = NULL; 616 enum stm32mp1_parent_id parent_id = 0; 617 uint32_t p_sel = 0; 618 int i = 0; 619 enum stm32mp1_parent_id p = _UNKNOWN_ID; 620 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 621 vaddr_t rcc_base = stm32_rcc_base(); 622 623 parent_id = clock_id2parent_id(id); 624 if (parent_id != _UNKNOWN_ID) 625 return (int)parent_id; 626 627 i = stm32mp1_clk_get_gated_id(id); 628 if (i < 0) 629 panic(); 630 631 p = stm32mp1_clk_get_fixed_parent(i); 632 if (p < _PARENT_NB) 633 return (int)p; 634 635 s = stm32mp1_clk_get_sel(i); 636 if (s == _UNKNOWN_SEL) 637 return -1; 638 if (s >= _PARENT_SEL_NB) 639 panic(); 640 641 sel = clk_sel_ref(s); 642 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & sel->msk; 643 if (p_sel < sel->nb_parent) 644 return (int)sel->parent[p_sel]; 645 646 DMSG("No parent selected for clk %lu", id); 647 return -1; 648 } 649 650 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 651 { 652 uint32_t selr = io_read32(stm32_rcc_base() + pll->rckxselr); 653 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 654 655 return osc_frequency(pll->refclk[src]); 656 } 657 658 /* 659 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 660 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 661 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 662 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 663 */ 664 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 665 { 666 unsigned long refclk = 0; 667 unsigned long fvco = 0; 668 uint32_t cfgr1 = 0; 669 uint32_t fracr = 0; 670 uint32_t divm = 0; 671 uint32_t divn = 0; 672 673 cfgr1 = io_read32(stm32_rcc_base() + pll->pllxcfgr1); 674 fracr = io_read32(stm32_rcc_base() + pll->pllxfracr); 675 676 divm = (cfgr1 & RCC_PLLNCFGR1_DIVM_MASK) >> RCC_PLLNCFGR1_DIVM_SHIFT; 677 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 678 679 refclk = stm32mp1_pll_get_fref(pll); 680 681 /* 682 * With FRACV : 683 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 684 * Without FRACV 685 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 686 */ 687 if (fracr & RCC_PLLNFRACR_FRACLE) { 688 unsigned long long numerator = 0; 689 unsigned long long denominator = 0; 690 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 691 RCC_PLLNFRACR_FRACV_SHIFT; 692 693 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 694 numerator = refclk * numerator; 695 denominator = ((unsigned long long)divm + 1U) << 13; 696 fvco = (unsigned long)(numerator / denominator); 697 } else { 698 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 699 } 700 701 return fvco; 702 } 703 704 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 705 enum stm32mp1_div_id div_id) 706 { 707 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 708 unsigned long dfout = 0; 709 uint32_t cfgr2 = 0; 710 uint32_t divy = 0; 711 712 if (div_id >= _DIV_NB) 713 return 0; 714 715 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2); 716 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 717 718 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 719 720 return dfout; 721 } 722 723 static unsigned long get_clock_rate(enum stm32mp1_parent_id p) 724 { 725 uint32_t reg = 0; 726 unsigned long clock = 0; 727 vaddr_t rcc_base = stm32_rcc_base(); 728 729 switch (p) { 730 case _CK_MPU: 731 /* MPU sub system */ 732 reg = io_read32(rcc_base + RCC_MPCKSELR); 733 switch (reg & RCC_SELR_SRC_MASK) { 734 case RCC_MPCKSELR_HSI: 735 clock = osc_frequency(OSC_HSI); 736 break; 737 case RCC_MPCKSELR_HSE: 738 clock = osc_frequency(OSC_HSE); 739 break; 740 case RCC_MPCKSELR_PLL: 741 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 742 break; 743 case RCC_MPCKSELR_PLL_MPUDIV: 744 reg = io_read32(rcc_base + RCC_MPCKDIVR); 745 if (reg & RCC_MPUDIV_MASK) 746 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P) >> 747 stm32mp1_mpu_div[reg & RCC_MPUDIV_MASK]; 748 else 749 clock = 0; 750 break; 751 default: 752 break; 753 } 754 break; 755 /* AXI sub system */ 756 case _ACLK: 757 case _HCLK2: 758 case _HCLK5: 759 case _HCLK6: 760 case _PCLK4: 761 case _PCLK5: 762 reg = io_read32(rcc_base + RCC_ASSCKSELR); 763 switch (reg & RCC_SELR_SRC_MASK) { 764 case RCC_ASSCKSELR_HSI: 765 clock = osc_frequency(OSC_HSI); 766 break; 767 case RCC_ASSCKSELR_HSE: 768 clock = osc_frequency(OSC_HSE); 769 break; 770 case RCC_ASSCKSELR_PLL: 771 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 772 break; 773 default: 774 break; 775 } 776 777 /* System clock divider */ 778 reg = io_read32(rcc_base + RCC_AXIDIVR); 779 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 780 781 switch (p) { 782 case _PCLK4: 783 reg = io_read32(rcc_base + RCC_APB4DIVR); 784 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 785 break; 786 case _PCLK5: 787 reg = io_read32(rcc_base + RCC_APB5DIVR); 788 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 789 break; 790 default: 791 break; 792 } 793 break; 794 /* MCU sub system */ 795 case _CK_MCU: 796 case _PCLK1: 797 case _PCLK2: 798 case _PCLK3: 799 reg = io_read32(rcc_base + RCC_MSSCKSELR); 800 switch (reg & RCC_SELR_SRC_MASK) { 801 case RCC_MSSCKSELR_HSI: 802 clock = osc_frequency(OSC_HSI); 803 break; 804 case RCC_MSSCKSELR_HSE: 805 clock = osc_frequency(OSC_HSE); 806 break; 807 case RCC_MSSCKSELR_CSI: 808 clock = osc_frequency(OSC_CSI); 809 break; 810 case RCC_MSSCKSELR_PLL: 811 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 812 break; 813 default: 814 break; 815 } 816 817 /* MCU clock divider */ 818 reg = io_read32(rcc_base + RCC_MCUDIVR); 819 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 820 821 switch (p) { 822 case _PCLK1: 823 reg = io_read32(rcc_base + RCC_APB1DIVR); 824 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 825 break; 826 case _PCLK2: 827 reg = io_read32(rcc_base + RCC_APB2DIVR); 828 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 829 break; 830 case _PCLK3: 831 reg = io_read32(rcc_base + RCC_APB3DIVR); 832 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 833 break; 834 case _CK_MCU: 835 default: 836 break; 837 } 838 break; 839 case _CK_PER: 840 reg = io_read32(rcc_base + RCC_CPERCKSELR); 841 switch (reg & RCC_SELR_SRC_MASK) { 842 case RCC_CPERCKSELR_HSI: 843 clock = osc_frequency(OSC_HSI); 844 break; 845 case RCC_CPERCKSELR_HSE: 846 clock = osc_frequency(OSC_HSE); 847 break; 848 case RCC_CPERCKSELR_CSI: 849 clock = osc_frequency(OSC_CSI); 850 break; 851 default: 852 break; 853 } 854 break; 855 case _HSI: 856 case _HSI_KER: 857 clock = osc_frequency(OSC_HSI); 858 break; 859 case _CSI: 860 case _CSI_KER: 861 clock = osc_frequency(OSC_CSI); 862 break; 863 case _HSE: 864 case _HSE_KER: 865 clock = osc_frequency(OSC_HSE); 866 break; 867 case _HSE_KER_DIV2: 868 clock = osc_frequency(OSC_HSE) >> 1; 869 break; 870 break; 871 case _LSI: 872 clock = osc_frequency(OSC_LSI); 873 break; 874 case _LSE: 875 clock = osc_frequency(OSC_LSE); 876 break; 877 /* PLL */ 878 case _PLL1_P: 879 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 880 break; 881 case _PLL1_Q: 882 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 883 break; 884 case _PLL1_R: 885 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 886 break; 887 case _PLL2_P: 888 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 889 break; 890 case _PLL2_Q: 891 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 892 break; 893 case _PLL2_R: 894 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 895 break; 896 case _PLL3_P: 897 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 898 break; 899 case _PLL3_Q: 900 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 901 break; 902 case _PLL3_R: 903 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 904 break; 905 case _PLL4_P: 906 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 907 break; 908 case _PLL4_Q: 909 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 910 break; 911 case _PLL4_R: 912 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 913 break; 914 /* Other */ 915 case _USB_PHY_48: 916 clock = osc_frequency(OSC_USB_PHY_48); 917 break; 918 default: 919 break; 920 } 921 922 return clock; 923 } 924 925 static void __clk_enable(const struct stm32mp1_clk_gate *gate) 926 { 927 vaddr_t base = stm32_rcc_base(); 928 uint32_t bit = BIT(gate->bit); 929 930 if (gate->set_clr) 931 io_write32(base + gate->offset, bit); 932 else 933 io_setbits32_stm32shregs(base + gate->offset, bit); 934 935 FMSG("Clock %u has been enabled", gate->clock_id); 936 } 937 938 static void __clk_disable(const struct stm32mp1_clk_gate *gate) 939 { 940 vaddr_t base = stm32_rcc_base(); 941 uint32_t bit = BIT(gate->bit); 942 943 if (gate->set_clr) 944 io_write32(base + gate->offset + RCC_MP_ENCLRR_OFFSET, bit); 945 else 946 io_clrbits32_stm32shregs(base + gate->offset, bit); 947 948 FMSG("Clock %u has been disabled", gate->clock_id); 949 } 950 951 static long get_timer_rate(long parent_rate, unsigned int apb_bus) 952 { 953 uint32_t timgxpre = 0; 954 uint32_t apbxdiv = 0; 955 vaddr_t rcc_base = stm32_rcc_base(); 956 957 switch (apb_bus) { 958 case 1: 959 apbxdiv = io_read32(rcc_base + RCC_APB1DIVR) & 960 RCC_APBXDIV_MASK; 961 timgxpre = io_read32(rcc_base + RCC_TIMG1PRER) & 962 RCC_TIMGXPRER_TIMGXPRE; 963 break; 964 case 2: 965 apbxdiv = io_read32(rcc_base + RCC_APB2DIVR) & 966 RCC_APBXDIV_MASK; 967 timgxpre = io_read32(rcc_base + RCC_TIMG2PRER) & 968 RCC_TIMGXPRER_TIMGXPRE; 969 break; 970 default: 971 panic(); 972 break; 973 } 974 975 if (apbxdiv == 0) 976 return parent_rate; 977 978 return parent_rate * (timgxpre + 1) * 2; 979 } 980 981 static unsigned long _stm32_clock_get_rate(unsigned long id) 982 { 983 enum stm32mp1_parent_id p = _UNKNOWN_ID; 984 unsigned long rate = 0; 985 986 p = stm32mp1_clk_get_parent(id); 987 if (p < 0) 988 return 0; 989 990 rate = get_clock_rate(p); 991 992 if ((id >= TIM2_K) && (id <= TIM14_K)) 993 rate = get_timer_rate(rate, 1); 994 995 if ((id >= TIM1_K) && (id <= TIM17_K)) 996 rate = get_timer_rate(rate, 2); 997 998 return rate; 999 } 1000 1001 /* 1002 * Get the parent ID of the target parent clock, or -1 if no parent found. 1003 */ 1004 static enum stm32mp1_parent_id get_parent_id_parent(enum stm32mp1_parent_id id) 1005 { 1006 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 1007 enum stm32mp1_pll_id pll_id = _PLL_NB; 1008 uint32_t p_sel = 0; 1009 1010 switch (id) { 1011 case _ACLK: 1012 case _PCLK4: 1013 case _PCLK5: 1014 s = _AXISS_SEL; 1015 break; 1016 case _PLL1_P: 1017 case _PLL1_Q: 1018 case _PLL1_R: 1019 pll_id = _PLL1; 1020 break; 1021 case _PLL2_P: 1022 case _PLL2_Q: 1023 case _PLL2_R: 1024 pll_id = _PLL2; 1025 break; 1026 case _PLL3_P: 1027 case _PLL3_Q: 1028 case _PLL3_R: 1029 pll_id = _PLL3; 1030 break; 1031 case _PLL4_P: 1032 case _PLL4_Q: 1033 case _PLL4_R: 1034 pll_id = _PLL4; 1035 break; 1036 case _PCLK1: 1037 case _PCLK2: 1038 case _HCLK2: 1039 case _HCLK6: 1040 case _CK_PER: 1041 case _CK_MPU: 1042 case _CK_MCU: 1043 case _USB_PHY_48: 1044 /* We do not expected to access these */ 1045 panic(); 1046 break; 1047 default: 1048 /* Other parents have no parent */ 1049 return -1; 1050 } 1051 1052 if (s != _UNKNOWN_SEL) { 1053 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 1054 vaddr_t rcc_base = stm32_rcc_base(); 1055 1056 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & 1057 sel->msk; 1058 1059 if (p_sel < sel->nb_parent) 1060 return sel->parent[p_sel]; 1061 } else { 1062 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1063 1064 p_sel = io_read32(stm32_rcc_base() + pll->rckxselr) & 1065 RCC_SELR_REFCLK_SRC_MASK; 1066 1067 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) 1068 return osc_id2parent_id(pll->refclk[p_sel]); 1069 } 1070 1071 FMSG("No parent found for %s", stm32mp1_clk_parent_name[id]); 1072 return -1; 1073 } 1074 1075 /* We are only interested in knowing if PLL3 shall be secure or not */ 1076 static void secure_parent_clocks(enum stm32mp1_parent_id parent_id) 1077 { 1078 enum stm32mp1_parent_id grandparent_id = _UNKNOWN_ID; 1079 1080 switch (parent_id) { 1081 case _ACLK: 1082 case _HCLK2: 1083 case _HCLK5: 1084 case _HCLK6: 1085 case _PCLK4: 1086 case _PCLK5: 1087 /* Intermediate clock mux or clock, go deeper in clock tree */ 1088 break; 1089 case _HSI: 1090 case _HSI_KER: 1091 case _LSI: 1092 case _CSI: 1093 case _CSI_KER: 1094 case _HSE: 1095 case _HSE_KER: 1096 case _HSE_KER_DIV2: 1097 case _LSE: 1098 case _PLL1_P: 1099 case _PLL1_Q: 1100 case _PLL1_R: 1101 case _PLL2_P: 1102 case _PLL2_Q: 1103 case _PLL2_R: 1104 /* Always secure clocks, no need to go further */ 1105 return; 1106 case _PLL3_P: 1107 case _PLL3_Q: 1108 case _PLL3_R: 1109 /* PLL3 is a shared resource, registered and don't go further */ 1110 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 1111 return; 1112 default: 1113 DMSG("Cannot lookup parent clock %s", 1114 stm32mp1_clk_parent_name[parent_id]); 1115 panic(); 1116 } 1117 1118 grandparent_id = get_parent_id_parent(parent_id); 1119 if (grandparent_id >= 0) 1120 secure_parent_clocks(grandparent_id); 1121 } 1122 1123 void stm32mp_register_clock_parents_secure(unsigned long clock_id) 1124 { 1125 enum stm32mp1_parent_id parent_id = stm32mp1_clk_get_parent(clock_id); 1126 1127 if (parent_id < 0) { 1128 DMSG("No parent for clock %lu", clock_id); 1129 return; 1130 } 1131 1132 secure_parent_clocks(parent_id); 1133 } 1134 1135 #ifdef CFG_EMBED_DTB 1136 static const char *stm32mp_osc_node_label[NB_OSC] = { 1137 [OSC_LSI] = "clk-lsi", 1138 [OSC_LSE] = "clk-lse", 1139 [OSC_HSI] = "clk-hsi", 1140 [OSC_HSE] = "clk-hse", 1141 [OSC_CSI] = "clk-csi", 1142 [OSC_I2S_CKIN] = "i2s_ckin", 1143 [OSC_USB_PHY_48] = "ck_usbo_48m" 1144 }; 1145 1146 static unsigned int clk_freq_prop(const void *fdt, int node) 1147 { 1148 const fdt32_t *cuint = NULL; 1149 int ret = 0; 1150 1151 /* Disabled clocks report null rate */ 1152 if (_fdt_get_status(fdt, node) == DT_STATUS_DISABLED) 1153 return 0; 1154 1155 cuint = fdt_getprop(fdt, node, "clock-frequency", &ret); 1156 if (!cuint) 1157 panic(); 1158 1159 return fdt32_to_cpu(*cuint); 1160 } 1161 1162 static void get_osc_freq_from_dt(const void *fdt) 1163 { 1164 enum stm32mp_osc_id idx = _UNKNOWN_OSC_ID; 1165 int clk_node = fdt_path_offset(fdt, "/clocks"); 1166 1167 if (clk_node < 0) 1168 panic(); 1169 1170 COMPILE_TIME_ASSERT((int)OSC_HSI == 0); 1171 for (idx = OSC_HSI; idx < NB_OSC; idx++) { 1172 const char *name = stm32mp_osc_node_label[idx]; 1173 int subnode = 0; 1174 1175 fdt_for_each_subnode(subnode, fdt, clk_node) { 1176 const char *cchar = NULL; 1177 int ret = 0; 1178 1179 cchar = fdt_get_name(fdt, subnode, &ret); 1180 if (!cchar) 1181 panic(); 1182 1183 if (strncmp(cchar, name, (size_t)ret) == 0) { 1184 stm32mp1_osc[idx] = clk_freq_prop(fdt, subnode); 1185 1186 DMSG("Osc %s: %lu Hz", name, stm32mp1_osc[idx]); 1187 break; 1188 } 1189 } 1190 1191 if (!stm32mp1_osc[idx]) 1192 DMSG("Osc %s: no frequency info", name); 1193 } 1194 } 1195 #endif /*CFG_EMBED_DTB*/ 1196 1197 static void enable_static_secure_clocks(void) 1198 { 1199 unsigned int idx = 0; 1200 const unsigned long secure_enable[] = { 1201 DDRC1, DDRC1LP, DDRC2, DDRC2LP, DDRPHYC, DDRPHYCLP, DDRCAPB, 1202 AXIDCG, DDRPHYCAPB, DDRPHYCAPBLP, TZPC, TZC1, TZC2, STGEN_K, 1203 BSEC, 1204 }; 1205 1206 for (idx = 0; idx < ARRAY_SIZE(secure_enable); idx++) { 1207 stm32_clock_enable(secure_enable[idx]); 1208 stm32mp_register_clock_parents_secure(secure_enable[idx]); 1209 } 1210 1211 if (CFG_TEE_CORE_NB_CORE > 1) 1212 stm32_clock_enable(RTCAPB); 1213 } 1214 1215 static void __maybe_unused enable_rcc_tzen(void) 1216 { 1217 io_setbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1218 } 1219 1220 static void __maybe_unused disable_rcc_tzen(void) 1221 { 1222 IMSG("RCC is non-secure"); 1223 io_clrbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1224 } 1225 1226 #ifdef CFG_EMBED_DTB 1227 static TEE_Result stm32mp1_clk_fdt_init(const void *fdt, int node) 1228 { 1229 unsigned int i = 0; 1230 int len = 0; 1231 int ignored = 0; 1232 1233 get_osc_freq_from_dt(fdt); 1234 1235 /* 1236 * OP-TEE core is not in charge of configuring clock parenthood. 1237 * This is expected from an earlier boot stage. Modifying the clock 1238 * tree parenthood here may jeopardize already configured clocks. 1239 * The sequence below ignores such DT directives with a friendly 1240 * debug trace. 1241 */ 1242 if (fdt_getprop(fdt, node, "st,clksrc", &len)) { 1243 DMSG("Ignore source clocks configuration from DT"); 1244 ignored++; 1245 } 1246 if (fdt_getprop(fdt, node, "st,clkdiv", &len)) { 1247 DMSG("Ignore clock divisors configuration from DT"); 1248 ignored++; 1249 } 1250 if (fdt_getprop(fdt, node, "st,pkcs", &len)) { 1251 DMSG("Ignore peripheral clocks tree configuration from DT"); 1252 ignored++; 1253 } 1254 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1255 char name[] = "st,pll@X"; 1256 1257 snprintf(name, sizeof(name), "st,pll@%d", i); 1258 node = fdt_subnode_offset(fdt, node, name); 1259 if (node < 0) 1260 continue; 1261 1262 if (fdt_getprop(fdt, node, "cfg", &len) || 1263 fdt_getprop(fdt, node, "frac", &len)) { 1264 DMSG("Ignore PLL%u configurations from DT", i); 1265 ignored++; 1266 } 1267 } 1268 1269 if (ignored != 0) 1270 IMSG("DT clock tree configurations were ignored"); 1271 1272 return TEE_SUCCESS; 1273 } 1274 #endif /*CFG_EMBED_DTB*/ 1275 1276 /* 1277 * Conversion between clk references and clock gates and clock on internals 1278 * 1279 * stm32mp1_clk first cells follow stm32mp1_clk_gate[] ordering. 1280 * stm32mp1_clk last cells follow stm32mp1_clk_on[] ordering. 1281 */ 1282 static struct clk stm32mp1_clk[ARRAY_SIZE(stm32mp1_clk_gate) + 1283 ARRAY_SIZE(stm32mp1_clk_on)]; 1284 1285 #define CLK_ON_INDEX_OFFSET ((int)ARRAY_SIZE(stm32mp1_clk_gate)) 1286 1287 static bool clk_is_gate(struct clk *clk) 1288 { 1289 int clk_index = clk - stm32mp1_clk; 1290 1291 assert(clk_index >= 0 && clk_index < (int)ARRAY_SIZE(stm32mp1_clk)); 1292 return clk_index < CLK_ON_INDEX_OFFSET; 1293 } 1294 1295 static unsigned long clk_to_clock_id(struct clk *clk) 1296 { 1297 int gate_index = clk - stm32mp1_clk; 1298 int on_index = gate_index - CLK_ON_INDEX_OFFSET; 1299 1300 if (clk_is_gate(clk)) 1301 return stm32mp1_clk_gate[gate_index].clock_id; 1302 1303 return stm32mp1_clk_on[on_index]; 1304 } 1305 1306 static const struct stm32mp1_clk_gate *clk_to_gate_ref(struct clk *clk) 1307 { 1308 int gate_index = clk - stm32mp1_clk; 1309 1310 assert(clk_is_gate(clk)); 1311 1312 return stm32mp1_clk_gate + gate_index; 1313 } 1314 1315 static int clock_id_to_gate_index(unsigned long clock_id) 1316 { 1317 size_t n = 0; 1318 1319 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_gate); n++) 1320 if (stm32mp1_clk_gate[n].clock_id == clock_id) 1321 return n; 1322 1323 return -1; 1324 } 1325 1326 static int clock_id_to_always_on_index(unsigned long clock_id) 1327 { 1328 size_t n = 0; 1329 1330 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_on); n++) 1331 if (stm32mp1_clk_on[n] == clock_id) 1332 return n; 1333 1334 return -1; 1335 } 1336 1337 static struct clk *clock_id_to_clk(unsigned long clock_id) 1338 { 1339 int gate_index = clock_id_to_gate_index(clock_id); 1340 int on_index = clock_id_to_always_on_index(clock_id); 1341 1342 if (gate_index >= 0) 1343 return stm32mp1_clk + gate_index; 1344 1345 if (on_index >= 0) 1346 return stm32mp1_clk + CLK_ON_INDEX_OFFSET + on_index; 1347 1348 return NULL; 1349 } 1350 1351 #if CFG_TEE_CORE_LOG_LEVEL >= TRACE_DEBUG 1352 struct clk_name { 1353 unsigned int clock_id; 1354 const char *name; 1355 }; 1356 1357 #define CLOCK_NAME(_binding, _name) \ 1358 { .clock_id = (_binding), .name = (_name) } 1359 1360 /* Store names only for some clocks */ 1361 const struct clk_name exposed_clk_name[] = { 1362 /* Clocks used by platform drivers not yet probed from DT */ 1363 CLOCK_NAME(CK_DBG, "dbg"), 1364 CLOCK_NAME(CK_MCU, "mcu"), 1365 CLOCK_NAME(RTCAPB, "rtcapb"), 1366 CLOCK_NAME(BKPSRAM, "bkpsram"), 1367 CLOCK_NAME(RTC, "rtc"), 1368 CLOCK_NAME(CRYP1, "crpy1"), 1369 CLOCK_NAME(SYSCFG, "syscfg"), 1370 CLOCK_NAME(GPIOA, "gpioa"), 1371 CLOCK_NAME(GPIOB, "gpiob"), 1372 CLOCK_NAME(GPIOC, "gpioc"), 1373 CLOCK_NAME(GPIOD, "gpiod"), 1374 CLOCK_NAME(GPIOE, "gpioe"), 1375 CLOCK_NAME(GPIOF, "gpiof"), 1376 CLOCK_NAME(GPIOG, "gpiog"), 1377 CLOCK_NAME(GPIOH, "gpioh"), 1378 CLOCK_NAME(GPIOI, "gpioi"), 1379 CLOCK_NAME(GPIOJ, "gpioj"), 1380 CLOCK_NAME(GPIOK, "gpiok"), 1381 CLOCK_NAME(GPIOZ, "gpioz"), 1382 /* Clock exposed by SCMI. SCMI clock fmro DT bindings to come... */ 1383 CLOCK_NAME(CK_HSE, "hse"), 1384 CLOCK_NAME(CK_HSI, "hsi"), 1385 CLOCK_NAME(CK_CSI, "csi"), 1386 CLOCK_NAME(CK_LSE, "lse"), 1387 CLOCK_NAME(CK_LSI, "lsi"), 1388 CLOCK_NAME(PLL2_Q, "pll2q"), 1389 CLOCK_NAME(PLL2_R, "pll2r"), 1390 CLOCK_NAME(PLL3_Q, "pll3q"), 1391 CLOCK_NAME(PLL3_R, "pll3r"), 1392 CLOCK_NAME(CRYP1, "cryp1"), 1393 CLOCK_NAME(HASH1, "hash1"), 1394 CLOCK_NAME(I2C4_K, "i2c4"), 1395 CLOCK_NAME(I2C6_K, "i2c6"), 1396 CLOCK_NAME(IWDG1, "iwdg"), 1397 CLOCK_NAME(RNG1_K, "rng1"), 1398 CLOCK_NAME(SPI6_K, "spi6"), 1399 CLOCK_NAME(USART1_K, "usart1"), 1400 CLOCK_NAME(CK_MCU, "mcu"), 1401 }; 1402 DECLARE_KEEP_PAGER(exposed_clk_name); 1403 1404 static const char *clk_op_get_name(struct clk *clk) 1405 { 1406 unsigned long clock_id = clk_to_clock_id(clk); 1407 size_t n = 0; 1408 1409 for (n = 0; n < ARRAY_SIZE(exposed_clk_name); n++) 1410 if (exposed_clk_name[n].clock_id == clock_id) 1411 return exposed_clk_name[n].name; 1412 1413 return NULL; 1414 } 1415 #else 1416 static const char *clk_op_get_name(struct clk *clk __unused) 1417 { 1418 return NULL; 1419 } 1420 #endif /*CFG_TEE_CORE_LOG_LEVEL*/ 1421 1422 static unsigned long clk_op_compute_rate(struct clk *clk, 1423 unsigned long parent_rate __unused) 1424 { 1425 return _stm32_clock_get_rate(clk_to_clock_id(clk)); 1426 } 1427 1428 static TEE_Result clk_op_enable(struct clk *clk) 1429 { 1430 if (clk_is_gate(clk)) 1431 __clk_enable(clk_to_gate_ref(clk)); 1432 1433 return TEE_SUCCESS; 1434 } 1435 DECLARE_KEEP_PAGER(clk_op_enable); 1436 1437 static void clk_op_disable(struct clk *clk) 1438 { 1439 if (clk_is_gate(clk)) 1440 __clk_disable(clk_to_gate_ref(clk)); 1441 } 1442 DECLARE_KEEP_PAGER(clk_op_disable); 1443 1444 /* This variable is weak to break its dependency chain when linked as unpaged */ 1445 const struct clk_ops stm32mp1_clk_ops 1446 __weak __rodata_unpaged("stm32mp1_clk_ops") = { 1447 .enable = clk_op_enable, 1448 .disable = clk_op_disable, 1449 .get_rate = clk_op_compute_rate, 1450 }; 1451 1452 static TEE_Result register_stm32mp1_clocks(void) 1453 { 1454 TEE_Result res = TEE_ERROR_GENERIC; 1455 size_t n = 0; 1456 1457 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk); n++) { 1458 stm32mp1_clk[n].ops = &stm32mp1_clk_ops; 1459 stm32mp1_clk[n].name = clk_op_get_name(stm32mp1_clk + n); 1460 refcount_set(&stm32mp1_clk[n].enabled_count, 0); 1461 1462 res = clk_register(stm32mp1_clk + n); 1463 if (res) 1464 return res; 1465 } 1466 1467 return TEE_SUCCESS; 1468 } 1469 1470 /* Route platform legacy clock functions to clk driver functions */ 1471 bool stm32_clock_is_enabled(unsigned long clock_id) 1472 { 1473 struct clk *clk = clock_id_to_clk(clock_id); 1474 1475 assert(clk); 1476 return clk_is_enabled(clk); 1477 } 1478 1479 void stm32_clock_enable(unsigned long clock_id) 1480 { 1481 struct clk *clk = clock_id_to_clk(clock_id); 1482 TEE_Result __maybe_unused res = TEE_ERROR_GENERIC; 1483 1484 assert(clk); 1485 res = clk_enable(clk); 1486 assert(!res); 1487 } 1488 1489 void stm32_clock_disable(unsigned long clock_id) 1490 { 1491 struct clk *clk = clock_id_to_clk(clock_id); 1492 1493 assert(clk); 1494 clk_disable(clk); 1495 } 1496 1497 unsigned long stm32_clock_get_rate(unsigned long clock_id) 1498 { 1499 struct clk *clk = clock_id_to_clk(clock_id); 1500 1501 assert(clk); 1502 return clk_get_rate(clk); 1503 } 1504 1505 #ifdef CFG_DRIVERS_CLK_DT 1506 static struct clk *stm32mp1_clk_dt_get_clk(struct dt_driver_phandle_args *pargs, 1507 void *data __unused, TEE_Result *res) 1508 { 1509 unsigned long clock_id = pargs->args[0]; 1510 struct clk *clk = NULL; 1511 1512 *res = TEE_ERROR_BAD_PARAMETERS; 1513 1514 if (pargs->args_count != 1) 1515 return NULL; 1516 1517 clk = clock_id_to_clk(clock_id); 1518 if (!clk) 1519 return NULL; 1520 1521 *res = TEE_SUCCESS; 1522 return clk; 1523 } 1524 1525 /* Non-null reference for compat data */ 1526 static const uint8_t non_secure_rcc; 1527 1528 static TEE_Result stm32mp1_clock_provider_probe(const void *fdt, int offs, 1529 const void *compat_data) 1530 { 1531 TEE_Result res = TEE_ERROR_GENERIC; 1532 1533 if (compat_data == &non_secure_rcc) 1534 disable_rcc_tzen(); 1535 else 1536 enable_rcc_tzen(); 1537 1538 res = stm32mp1_clk_fdt_init(fdt, offs); 1539 if (res) { 1540 EMSG("Failed to initialize clocks from DT: %#"PRIx32, res); 1541 panic(); 1542 } 1543 1544 res = register_stm32mp1_clocks(); 1545 if (res) { 1546 EMSG("Failed to register clocks: %#"PRIx32, res); 1547 panic(); 1548 } 1549 1550 res = clk_dt_register_clk_provider(fdt, offs, stm32mp1_clk_dt_get_clk, 1551 NULL); 1552 if (res) { 1553 EMSG("Failed to register clock provider: %#"PRIx32, res); 1554 panic(); 1555 } 1556 1557 enable_static_secure_clocks(); 1558 1559 return TEE_SUCCESS; 1560 } 1561 1562 static const struct dt_device_match stm32mp1_clock_match_table[] = { 1563 { .compatible = "st,stm32mp1-rcc", .compat_data = &non_secure_rcc, }, 1564 { .compatible = "st,stm32mp1-rcc-secure", }, 1565 { } 1566 }; 1567 1568 DEFINE_DT_DRIVER(stm32mp1_clock_dt_driver) = { 1569 .name = "stm32mp1_clock", 1570 .type = DT_DRIVER_CLK, 1571 .match_table = stm32mp1_clock_match_table, 1572 .probe = stm32mp1_clock_provider_probe, 1573 }; 1574 #else /*CFG_DRIVERS_CLK_DT*/ 1575 static TEE_Result stm32mp1_clk_early_init(void) 1576 { 1577 TEE_Result __maybe_unused res = TEE_ERROR_GENERIC; 1578 1579 res = register_stm32mp1_clocks(); 1580 if (res) { 1581 EMSG("Failed to register clocks: %#"PRIx32, res); 1582 panic(); 1583 } 1584 1585 enable_static_secure_clocks(); 1586 1587 return TEE_SUCCESS; 1588 } 1589 1590 service_init(stm32mp1_clk_early_init); 1591 #endif /*CFG_DRIVERS_CLK_DT*/ 1592