1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0+) 2 /* 3 * Copyright (C) 2018-2019, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/stm32mp1_rcc.h> 9 #include <drivers/clk.h> 10 #include <drivers/clk_dt.h> 11 #include <dt-bindings/clock/stm32mp1-clks.h> 12 #include <initcall.h> 13 #include <io.h> 14 #include <keep.h> 15 #include <kernel/dt.h> 16 #include <kernel/boot.h> 17 #include <kernel/panic.h> 18 #include <kernel/spinlock.h> 19 #include <libfdt.h> 20 #include <platform_config.h> 21 #include <stdio.h> 22 #include <stm32_util.h> 23 #include <trace.h> 24 #include <util.h> 25 26 /* Identifiers for root oscillators */ 27 enum stm32mp_osc_id { 28 OSC_HSI, 29 OSC_HSE, 30 OSC_CSI, 31 OSC_LSI, 32 OSC_LSE, 33 OSC_I2S_CKIN, 34 OSC_USB_PHY_48, 35 NB_OSC, 36 _UNKNOWN_OSC_ID = 0xffU 37 }; 38 39 /* Identifiers for parent clocks */ 40 enum stm32mp1_parent_id { 41 _HSI, 42 _HSE, 43 _CSI, 44 _LSI, 45 _LSE, 46 _I2S_CKIN, 47 _USB_PHY_48, 48 _HSI_KER, 49 _HSE_KER, 50 _HSE_KER_DIV2, 51 _HSE_RTC, 52 _CSI_KER, 53 _PLL1_P, 54 _PLL1_Q, 55 _PLL1_R, 56 _PLL2_P, 57 _PLL2_Q, 58 _PLL2_R, 59 _PLL3_P, 60 _PLL3_Q, 61 _PLL3_R, 62 _PLL4_P, 63 _PLL4_Q, 64 _PLL4_R, 65 _ACLK, 66 _PCLK1, 67 _PCLK2, 68 _PCLK3, 69 _PCLK4, 70 _PCLK5, 71 _HCLK5, 72 _HCLK6, 73 _HCLK2, 74 _CK_PER, 75 _CK_MPU, 76 _CK_MCU, 77 _PARENT_NB, 78 _UNKNOWN_ID = 0xff, 79 }; 80 81 /* 82 * Identifiers for parent clock selectors. 83 * This enum lists only the parent clocks we are interested in. 84 */ 85 enum stm32mp1_parent_sel { 86 _STGEN_SEL, 87 _I2C46_SEL, 88 _SPI6_SEL, 89 _USART1_SEL, 90 _RNG1_SEL, 91 _UART6_SEL, 92 _UART24_SEL, 93 _UART35_SEL, 94 _UART78_SEL, 95 _AXISS_SEL, 96 _MCUSS_SEL, 97 _USBPHY_SEL, 98 _USBO_SEL, 99 _RTC_SEL, 100 _MPU_SEL, 101 _PARENT_SEL_NB, 102 _UNKNOWN_SEL = 0xff, 103 }; 104 105 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 106 [_HSE] = CK_HSE, 107 [_HSI] = CK_HSI, 108 [_CSI] = CK_CSI, 109 [_LSE] = CK_LSE, 110 [_LSI] = CK_LSI, 111 [_I2S_CKIN] = _UNKNOWN_ID, 112 [_USB_PHY_48] = _UNKNOWN_ID, 113 [_HSI_KER] = CK_HSI, 114 [_HSE_KER] = CK_HSE, 115 [_HSE_KER_DIV2] = CK_HSE_DIV2, 116 [_HSE_RTC] = _UNKNOWN_ID, 117 [_CSI_KER] = CK_CSI, 118 [_PLL1_P] = PLL1_P, 119 [_PLL1_Q] = PLL1_Q, 120 [_PLL1_R] = PLL1_R, 121 [_PLL2_P] = PLL2_P, 122 [_PLL2_Q] = PLL2_Q, 123 [_PLL2_R] = PLL2_R, 124 [_PLL3_P] = PLL3_P, 125 [_PLL3_Q] = PLL3_Q, 126 [_PLL3_R] = PLL3_R, 127 [_PLL4_P] = PLL4_P, 128 [_PLL4_Q] = PLL4_Q, 129 [_PLL4_R] = PLL4_R, 130 [_ACLK] = CK_AXI, 131 [_PCLK1] = CK_AXI, 132 [_PCLK2] = CK_AXI, 133 [_PCLK3] = CK_AXI, 134 [_PCLK4] = CK_AXI, 135 [_PCLK5] = CK_AXI, 136 [_HCLK5] = CK_AXI, 137 [_HCLK6] = CK_AXI, 138 [_HCLK2] = CK_AXI, 139 [_CK_PER] = CK_PER, 140 [_CK_MPU] = CK_MPU, 141 [_CK_MCU] = CK_MCU, 142 }; 143 144 static enum stm32mp1_parent_id osc_id2parent_id(enum stm32mp_osc_id osc_id) 145 { 146 assert(osc_id >= OSC_HSI && osc_id < NB_OSC); 147 COMPILE_TIME_ASSERT((int)OSC_HSI == (int)_HSI && 148 (int)OSC_HSE == (int)_HSE && 149 (int)OSC_CSI == (int)_CSI && 150 (int)OSC_LSI == (int)_LSI && 151 (int)OSC_LSE == (int)_LSE && 152 (int)OSC_I2S_CKIN == (int)_I2S_CKIN && 153 (int)OSC_USB_PHY_48 == (int)_USB_PHY_48); 154 155 return (enum stm32mp1_parent_id)osc_id; 156 } 157 158 static enum stm32mp1_parent_id clock_id2parent_id(unsigned long id) 159 { 160 size_t n = 0; 161 162 COMPILE_TIME_ASSERT(STM32MP1_LAST_CLK < _UNKNOWN_ID); 163 164 for (n = 0; n < ARRAY_SIZE(parent_id_clock_id); n++) 165 if (parent_id_clock_id[n] == id) 166 return (enum stm32mp1_parent_id)n; 167 168 return _UNKNOWN_ID; 169 } 170 171 /* Identifiers for PLLs and their configuration resources */ 172 enum stm32mp1_pll_id { 173 _PLL1, 174 _PLL2, 175 _PLL3, 176 _PLL4, 177 _PLL_NB 178 }; 179 180 enum stm32mp1_div_id { 181 _DIV_P, 182 _DIV_Q, 183 _DIV_R, 184 _DIV_NB, 185 }; 186 187 enum stm32mp1_plltype { 188 PLL_800, 189 PLL_1600, 190 PLL_TYPE_NB 191 }; 192 193 /* 194 * Clock generic gates clocks which state is controlled by a single RCC bit 195 * 196 * @offset: RCC register byte offset from RCC base where clock is controlled 197 * @bit: Bit position in the RCC 32bit register 198 * @clock_id: Identifier used for the clock in the clock driver API 199 * @set_clr: Non-null if and only-if RCC register is a CLEAR/SET register 200 * (CLEAR register is at offset RCC_MP_ENCLRR_OFFSET from SET register) 201 * @secure: One of N_S or SEC, defined below 202 * @sel: _UNKNOWN_ID (fixed parent) or reference to parent clock selector 203 * (8bit storage of ID from enum stm32mp1_parent_sel) 204 * @fixed: _UNKNOWN_ID (selectable paranet) or reference to parent clock 205 * (8bit storage of ID from enum stm32mp1_parent_id) 206 */ 207 struct stm32mp1_clk_gate { 208 uint16_t offset; 209 uint8_t bit; 210 uint8_t clock_id; 211 uint8_t set_clr; 212 uint8_t secure; 213 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 214 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 215 }; 216 217 /* Parent clock selection: select register info, parent clocks references */ 218 struct stm32mp1_clk_sel { 219 uint16_t offset; 220 uint8_t src; 221 uint8_t msk; 222 uint8_t nb_parent; 223 const uint8_t *parent; 224 }; 225 226 #define REFCLK_SIZE 4 227 /* PLL control: type, control register offsets, up-to-4 selectable parent */ 228 struct stm32mp1_clk_pll { 229 enum stm32mp1_plltype plltype; 230 uint16_t rckxselr; 231 uint16_t pllxcfgr1; 232 uint16_t pllxcfgr2; 233 uint16_t pllxfracr; 234 uint16_t pllxcr; 235 uint16_t pllxcsgr; 236 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 237 }; 238 239 #define N_S 0 /* Non-secure can access RCC interface */ 240 #define SEC 1 /* RCC[TZEN] protects RCC interface */ 241 242 /* Clocks with selectable source and not set/clr register access */ 243 #define _CLK_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 244 { \ 245 .offset = (_offset), \ 246 .bit = (_bit), \ 247 .clock_id = (_clock_id), \ 248 .set_clr = 0, \ 249 .secure = (_sec), \ 250 .sel = (_parent_sel), \ 251 .fixed = _UNKNOWN_ID, \ 252 } 253 254 /* Clocks with fixed source and not set/clr register access */ 255 #define _CLK_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 256 { \ 257 .offset = (_offset), \ 258 .bit = (_bit), \ 259 .clock_id = (_clock_id), \ 260 .set_clr = 0, \ 261 .secure = (_sec), \ 262 .sel = _UNKNOWN_SEL, \ 263 .fixed = (_parent), \ 264 } 265 266 /* Clocks with selectable source and set/clr register access */ 267 #define _CLK_SC_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 268 { \ 269 .offset = (_offset), \ 270 .bit = (_bit), \ 271 .clock_id = (_clock_id), \ 272 .set_clr = 1, \ 273 .secure = (_sec), \ 274 .sel = (_parent_sel), \ 275 .fixed = _UNKNOWN_ID, \ 276 } 277 278 /* Clocks with fixed source and set/clr register access */ 279 #define _CLK_SC_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 280 { \ 281 .offset = (_offset), \ 282 .bit = (_bit), \ 283 .clock_id = (_clock_id), \ 284 .set_clr = 1, \ 285 .secure = (_sec), \ 286 .sel = _UNKNOWN_SEL, \ 287 .fixed = (_parent), \ 288 } 289 290 /* 291 * Clocks with selectable source and set/clr register access 292 * and enable bit position defined by a label (argument _bit) 293 */ 294 #define _CLK_SC2_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 295 { \ 296 .offset = (_offset), \ 297 .clock_id = (_clock_id), \ 298 .bit = _offset ## _ ## _bit ## _POS, \ 299 .set_clr = 1, \ 300 .secure = (_sec), \ 301 .sel = (_parent_sel), \ 302 .fixed = _UNKNOWN_ID, \ 303 } 304 #define _CLK_SC2_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 305 { \ 306 .offset = (_offset), \ 307 .clock_id = (_clock_id), \ 308 .bit = _offset ## _ ## _bit ## _POS, \ 309 .set_clr = 1, \ 310 .secure = (_sec), \ 311 .sel = _UNKNOWN_SEL, \ 312 .fixed = (_parent), \ 313 } 314 315 #define _CLK_PARENT(idx, _offset, _src, _mask, _parent) \ 316 [(idx)] = { \ 317 .offset = (_offset), \ 318 .src = (_src), \ 319 .msk = (_mask), \ 320 .parent = (_parent), \ 321 .nb_parent = ARRAY_SIZE(_parent) \ 322 } 323 324 #define _CLK_PLL(_idx, _type, _off1, _off2, _off3, _off4, \ 325 _off5, _off6, _p1, _p2, _p3, _p4) \ 326 [(_idx)] = { \ 327 .plltype = (_type), \ 328 .rckxselr = (_off1), \ 329 .pllxcfgr1 = (_off2), \ 330 .pllxcfgr2 = (_off3), \ 331 .pllxfracr = (_off4), \ 332 .pllxcr = (_off5), \ 333 .pllxcsgr = (_off6), \ 334 .refclk[0] = (_p1), \ 335 .refclk[1] = (_p2), \ 336 .refclk[2] = (_p3), \ 337 .refclk[3] = (_p4), \ 338 } 339 340 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 341 342 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 343 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 344 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 345 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 346 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 347 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 348 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 349 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 351 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 352 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 353 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 354 355 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, SPI6EN, SPI6_K, _SPI6_SEL), 356 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C4EN, I2C4_K, _I2C46_SEL), 357 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C6EN, I2C6_K, _I2C46_SEL), 358 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, USART1EN, USART1_K, _USART1_SEL), 359 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, RTCAPBEN, RTCAPB, _PCLK5), 360 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC1EN, TZC1, _PCLK5), 361 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC2EN, TZC2, _PCLK5), 362 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZPCEN, TZPC, _PCLK5), 363 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, IWDG1APBEN, IWDG1, _PCLK5), 364 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, BSECEN, BSEC, _PCLK5), 365 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, STGENEN, STGEN_K, _STGEN_SEL), 366 367 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, GPIOZEN, GPIOZ, _HCLK5), 368 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, CRYP1EN, CRYP1, _HCLK5), 369 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, HASH1EN, HASH1, _HCLK5), 370 _CLK_SC2_SELEC(SEC, RCC_MP_AHB5ENSETR, RNG1EN, RNG1_K, _RNG1_SEL), 371 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, BKPSRAMEN, BKPSRAM, _PCLK5), 372 373 _CLK_SC2_FIXED(SEC, RCC_MP_TZAHB6ENSETR, MDMA, MDMA, _HCLK6), 374 375 _CLK_SELEC(SEC, RCC_BDCR, RCC_BDCR_RTCCKEN_POS, RTC, _RTC_SEL), 376 377 /* Non-secure clocks */ 378 #ifdef CFG_WITH_NSEC_GPIOS 379 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_ID), 380 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_ID), 381 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_ID), 382 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_ID), 383 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_ID), 384 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_ID), 385 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_ID), 386 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_ID), 387 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_ID), 388 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_ID), 389 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_ID), 390 #endif 391 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 392 #ifdef CFG_WITH_NSEC_UARTS 393 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 394 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 395 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 396 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 397 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 398 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 399 #endif 400 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 401 #ifdef CFG_WITH_NSEC_UARTS 402 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 403 #endif 404 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 405 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 406 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 407 408 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 409 }; 410 DECLARE_KEEP_PAGER(stm32mp1_clk_gate); 411 412 const uint8_t stm32mp1_clk_on[] = { 413 CK_HSE, CK_CSI, CK_LSI, CK_LSE, CK_HSI, CK_HSE_DIV2, 414 PLL1_P, PLL1_Q, PLL1_R, PLL2_P, PLL2_Q, PLL2_R, PLL3_P, PLL3_Q, PLL3_R, 415 CK_AXI, CK_MPU, CK_MCU, 416 }; 417 418 /* Parents for secure aware clocks in the xxxSELR value ordering */ 419 static const uint8_t stgen_parents[] = { 420 _HSI_KER, _HSE_KER 421 }; 422 423 static const uint8_t i2c46_parents[] = { 424 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 425 }; 426 427 static const uint8_t spi6_parents[] = { 428 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 429 }; 430 431 static const uint8_t usart1_parents[] = { 432 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 433 }; 434 435 static const uint8_t rng1_parents[] = { 436 _CSI, _PLL4_R, _LSE, _LSI 437 }; 438 439 static const uint8_t mpu_parents[] = { 440 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 441 }; 442 443 /* Parents for (some) non-secure clocks */ 444 #ifdef CFG_WITH_NSEC_UARTS 445 static const uint8_t uart6_parents[] = { 446 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 447 }; 448 449 static const uint8_t uart234578_parents[] = { 450 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 451 }; 452 #endif 453 454 static const uint8_t axiss_parents[] = { 455 _HSI, _HSE, _PLL2_P 456 }; 457 458 static const uint8_t mcuss_parents[] = { 459 _HSI, _HSE, _CSI, _PLL3_P 460 }; 461 462 static const uint8_t rtc_parents[] = { 463 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 464 }; 465 466 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 467 /* Secure aware clocks */ 468 _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 469 _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 470 _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents), 471 _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents), 472 _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents), 473 _CLK_PARENT(_RTC_SEL, RCC_BDCR, 16, 0x3, rtc_parents), 474 _CLK_PARENT(_MPU_SEL, RCC_MPCKSELR, 0, 0x3, mpu_parents), 475 /* Always non-secure clocks (maybe used in some way in secure world) */ 476 #ifdef CFG_WITH_NSEC_UARTS 477 _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 478 _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents), 479 _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents), 480 _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents), 481 #endif 482 _CLK_PARENT(_AXISS_SEL, RCC_ASSCKSELR, 0, 0x3, axiss_parents), 483 _CLK_PARENT(_MCUSS_SEL, RCC_MSSCKSELR, 0, 0x3, mcuss_parents), 484 }; 485 486 /* PLLNCFGR2 register divider by output */ 487 static const uint8_t pllncfgr2[_DIV_NB] = { 488 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 489 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 490 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 491 }; 492 493 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 494 _CLK_PLL(_PLL1, PLL_1600, 495 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 496 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 497 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 498 _CLK_PLL(_PLL2, PLL_1600, 499 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 500 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 501 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 502 _CLK_PLL(_PLL3, PLL_800, 503 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 504 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 505 OSC_HSI, OSC_HSE, OSC_CSI, _UNKNOWN_OSC_ID), 506 _CLK_PLL(_PLL4, PLL_800, 507 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 508 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 509 OSC_HSI, OSC_HSE, OSC_CSI, OSC_I2S_CKIN), 510 }; 511 512 /* Prescaler table lookups for clock computation */ 513 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 514 static const uint8_t stm32mp1_mcu_div[16] = { 515 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 516 }; 517 518 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 519 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 520 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 521 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 522 0, 1, 2, 3, 4, 4, 4, 4 523 }; 524 525 /* div = /1 /2 /3 /4 */ 526 static const uint8_t stm32mp1_axi_div[8] = { 527 1, 2, 3, 4, 4, 4, 4, 4 528 }; 529 530 static const char __maybe_unused *const stm32mp1_clk_parent_name[_PARENT_NB] = { 531 [_HSI] = "HSI", 532 [_HSE] = "HSE", 533 [_CSI] = "CSI", 534 [_LSI] = "LSI", 535 [_LSE] = "LSE", 536 [_I2S_CKIN] = "I2S_CKIN", 537 [_HSI_KER] = "HSI_KER", 538 [_HSE_KER] = "HSE_KER", 539 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 540 [_HSE_RTC] = "HSE_RTC", 541 [_CSI_KER] = "CSI_KER", 542 [_PLL1_P] = "PLL1_P", 543 [_PLL1_Q] = "PLL1_Q", 544 [_PLL1_R] = "PLL1_R", 545 [_PLL2_P] = "PLL2_P", 546 [_PLL2_Q] = "PLL2_Q", 547 [_PLL2_R] = "PLL2_R", 548 [_PLL3_P] = "PLL3_P", 549 [_PLL3_Q] = "PLL3_Q", 550 [_PLL3_R] = "PLL3_R", 551 [_PLL4_P] = "PLL4_P", 552 [_PLL4_Q] = "PLL4_Q", 553 [_PLL4_R] = "PLL4_R", 554 [_ACLK] = "ACLK", 555 [_PCLK1] = "PCLK1", 556 [_PCLK2] = "PCLK2", 557 [_PCLK3] = "PCLK3", 558 [_PCLK4] = "PCLK4", 559 [_PCLK5] = "PCLK5", 560 [_HCLK5] = "HCLK5", 561 [_HCLK6] = "HCLK6", 562 [_HCLK2] = "HCLK2", 563 [_CK_PER] = "CK_PER", 564 [_CK_MPU] = "CK_MPU", 565 [_CK_MCU] = "CK_MCU", 566 [_USB_PHY_48] = "USB_PHY_48", 567 }; 568 569 /* 570 * Oscillator frequency in Hz. This array shall be initialized 571 * according to platform. 572 */ 573 static unsigned long stm32mp1_osc[NB_OSC]; 574 575 static unsigned long osc_frequency(enum stm32mp_osc_id idx) 576 { 577 if (idx >= ARRAY_SIZE(stm32mp1_osc)) { 578 DMSG("clk id %d not found", idx); 579 return 0; 580 } 581 582 return stm32mp1_osc[idx]; 583 } 584 585 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 586 { 587 return &stm32mp1_clk_gate[idx]; 588 } 589 590 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 591 { 592 return &stm32mp1_clk_sel[idx]; 593 } 594 595 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 596 { 597 return &stm32mp1_clk_pll[idx]; 598 } 599 600 static int stm32mp1_clk_get_gated_id(unsigned long id) 601 { 602 unsigned int i = 0; 603 604 for (i = 0; i < NB_GATES; i++) 605 if (gate_ref(i)->clock_id == id) 606 return i; 607 608 DMSG("clk id %lu not found", id); 609 return -1; 610 } 611 612 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 613 { 614 return (enum stm32mp1_parent_sel)gate_ref(i)->sel; 615 } 616 617 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 618 { 619 return (enum stm32mp1_parent_id)gate_ref(i)->fixed; 620 } 621 622 static int stm32mp1_clk_get_parent(unsigned long id) 623 { 624 const struct stm32mp1_clk_sel *sel = NULL; 625 enum stm32mp1_parent_id parent_id = 0; 626 uint32_t p_sel = 0; 627 int i = 0; 628 enum stm32mp1_parent_id p = _UNKNOWN_ID; 629 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 630 vaddr_t rcc_base = stm32_rcc_base(); 631 632 parent_id = clock_id2parent_id(id); 633 if (parent_id != _UNKNOWN_ID) 634 return (int)parent_id; 635 636 i = stm32mp1_clk_get_gated_id(id); 637 if (i < 0) 638 panic(); 639 640 p = stm32mp1_clk_get_fixed_parent(i); 641 if (p < _PARENT_NB) 642 return (int)p; 643 644 s = stm32mp1_clk_get_sel(i); 645 if (s == _UNKNOWN_SEL) 646 return -1; 647 if (s >= _PARENT_SEL_NB) 648 panic(); 649 650 sel = clk_sel_ref(s); 651 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & sel->msk; 652 if (p_sel < sel->nb_parent) 653 return (int)sel->parent[p_sel]; 654 655 DMSG("No parent selected for clk %lu", id); 656 return -1; 657 } 658 659 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 660 { 661 uint32_t selr = io_read32(stm32_rcc_base() + pll->rckxselr); 662 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 663 664 return osc_frequency(pll->refclk[src]); 665 } 666 667 /* 668 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 669 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 670 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 671 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 672 */ 673 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 674 { 675 unsigned long refclk = 0; 676 unsigned long fvco = 0; 677 uint32_t cfgr1 = 0; 678 uint32_t fracr = 0; 679 uint32_t divm = 0; 680 uint32_t divn = 0; 681 682 cfgr1 = io_read32(stm32_rcc_base() + pll->pllxcfgr1); 683 fracr = io_read32(stm32_rcc_base() + pll->pllxfracr); 684 685 divm = (cfgr1 & RCC_PLLNCFGR1_DIVM_MASK) >> RCC_PLLNCFGR1_DIVM_SHIFT; 686 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 687 688 refclk = stm32mp1_pll_get_fref(pll); 689 690 /* 691 * With FRACV : 692 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 693 * Without FRACV 694 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 695 */ 696 if (fracr & RCC_PLLNFRACR_FRACLE) { 697 unsigned long long numerator = 0; 698 unsigned long long denominator = 0; 699 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 700 RCC_PLLNFRACR_FRACV_SHIFT; 701 702 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 703 numerator = refclk * numerator; 704 denominator = ((unsigned long long)divm + 1U) << 13; 705 fvco = (unsigned long)(numerator / denominator); 706 } else { 707 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 708 } 709 710 return fvco; 711 } 712 713 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 714 enum stm32mp1_div_id div_id) 715 { 716 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 717 unsigned long dfout = 0; 718 uint32_t cfgr2 = 0; 719 uint32_t divy = 0; 720 721 if (div_id >= _DIV_NB) 722 return 0; 723 724 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2); 725 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 726 727 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 728 729 return dfout; 730 } 731 732 static unsigned long get_clock_rate(enum stm32mp1_parent_id p) 733 { 734 uint32_t reg = 0; 735 unsigned long clock = 0; 736 vaddr_t rcc_base = stm32_rcc_base(); 737 738 switch (p) { 739 case _CK_MPU: 740 /* MPU sub system */ 741 reg = io_read32(rcc_base + RCC_MPCKSELR); 742 switch (reg & RCC_SELR_SRC_MASK) { 743 case RCC_MPCKSELR_HSI: 744 clock = osc_frequency(OSC_HSI); 745 break; 746 case RCC_MPCKSELR_HSE: 747 clock = osc_frequency(OSC_HSE); 748 break; 749 case RCC_MPCKSELR_PLL: 750 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 751 break; 752 case RCC_MPCKSELR_PLL_MPUDIV: 753 reg = io_read32(rcc_base + RCC_MPCKDIVR); 754 if (reg & RCC_MPUDIV_MASK) 755 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P) >> 756 stm32mp1_mpu_div[reg & RCC_MPUDIV_MASK]; 757 else 758 clock = 0; 759 break; 760 default: 761 break; 762 } 763 break; 764 /* AXI sub system */ 765 case _ACLK: 766 case _HCLK2: 767 case _HCLK5: 768 case _HCLK6: 769 case _PCLK4: 770 case _PCLK5: 771 reg = io_read32(rcc_base + RCC_ASSCKSELR); 772 switch (reg & RCC_SELR_SRC_MASK) { 773 case RCC_ASSCKSELR_HSI: 774 clock = osc_frequency(OSC_HSI); 775 break; 776 case RCC_ASSCKSELR_HSE: 777 clock = osc_frequency(OSC_HSE); 778 break; 779 case RCC_ASSCKSELR_PLL: 780 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 781 break; 782 default: 783 break; 784 } 785 786 /* System clock divider */ 787 reg = io_read32(rcc_base + RCC_AXIDIVR); 788 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 789 790 switch (p) { 791 case _PCLK4: 792 reg = io_read32(rcc_base + RCC_APB4DIVR); 793 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 794 break; 795 case _PCLK5: 796 reg = io_read32(rcc_base + RCC_APB5DIVR); 797 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 798 break; 799 default: 800 break; 801 } 802 break; 803 /* MCU sub system */ 804 case _CK_MCU: 805 case _PCLK1: 806 case _PCLK2: 807 case _PCLK3: 808 reg = io_read32(rcc_base + RCC_MSSCKSELR); 809 switch (reg & RCC_SELR_SRC_MASK) { 810 case RCC_MSSCKSELR_HSI: 811 clock = osc_frequency(OSC_HSI); 812 break; 813 case RCC_MSSCKSELR_HSE: 814 clock = osc_frequency(OSC_HSE); 815 break; 816 case RCC_MSSCKSELR_CSI: 817 clock = osc_frequency(OSC_CSI); 818 break; 819 case RCC_MSSCKSELR_PLL: 820 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 821 break; 822 default: 823 break; 824 } 825 826 /* MCU clock divider */ 827 reg = io_read32(rcc_base + RCC_MCUDIVR); 828 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 829 830 switch (p) { 831 case _PCLK1: 832 reg = io_read32(rcc_base + RCC_APB1DIVR); 833 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 834 break; 835 case _PCLK2: 836 reg = io_read32(rcc_base + RCC_APB2DIVR); 837 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 838 break; 839 case _PCLK3: 840 reg = io_read32(rcc_base + RCC_APB3DIVR); 841 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 842 break; 843 case _CK_MCU: 844 default: 845 break; 846 } 847 break; 848 case _CK_PER: 849 reg = io_read32(rcc_base + RCC_CPERCKSELR); 850 switch (reg & RCC_SELR_SRC_MASK) { 851 case RCC_CPERCKSELR_HSI: 852 clock = osc_frequency(OSC_HSI); 853 break; 854 case RCC_CPERCKSELR_HSE: 855 clock = osc_frequency(OSC_HSE); 856 break; 857 case RCC_CPERCKSELR_CSI: 858 clock = osc_frequency(OSC_CSI); 859 break; 860 default: 861 break; 862 } 863 break; 864 case _HSI: 865 case _HSI_KER: 866 clock = osc_frequency(OSC_HSI); 867 break; 868 case _CSI: 869 case _CSI_KER: 870 clock = osc_frequency(OSC_CSI); 871 break; 872 case _HSE: 873 case _HSE_KER: 874 clock = osc_frequency(OSC_HSE); 875 break; 876 case _HSE_KER_DIV2: 877 clock = osc_frequency(OSC_HSE) >> 1; 878 break; 879 case _HSE_RTC: 880 clock = osc_frequency(OSC_HSE); 881 clock /= (io_read32(rcc_base + RCC_RTCDIVR) & 882 RCC_DIVR_DIV_MASK) + 1; 883 break; 884 case _LSI: 885 clock = osc_frequency(OSC_LSI); 886 break; 887 case _LSE: 888 clock = osc_frequency(OSC_LSE); 889 break; 890 /* PLL */ 891 case _PLL1_P: 892 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 893 break; 894 case _PLL1_Q: 895 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 896 break; 897 case _PLL1_R: 898 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 899 break; 900 case _PLL2_P: 901 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 902 break; 903 case _PLL2_Q: 904 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 905 break; 906 case _PLL2_R: 907 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 908 break; 909 case _PLL3_P: 910 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 911 break; 912 case _PLL3_Q: 913 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 914 break; 915 case _PLL3_R: 916 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 917 break; 918 case _PLL4_P: 919 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 920 break; 921 case _PLL4_Q: 922 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 923 break; 924 case _PLL4_R: 925 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 926 break; 927 /* Other */ 928 case _USB_PHY_48: 929 clock = osc_frequency(OSC_USB_PHY_48); 930 break; 931 default: 932 break; 933 } 934 935 return clock; 936 } 937 938 static void __clk_enable(const struct stm32mp1_clk_gate *gate) 939 { 940 vaddr_t base = stm32_rcc_base(); 941 uint32_t bit = BIT(gate->bit); 942 943 if (gate->set_clr) 944 io_write32(base + gate->offset, bit); 945 else 946 io_setbits32_stm32shregs(base + gate->offset, bit); 947 948 FMSG("Clock %u has been enabled", gate->clock_id); 949 } 950 951 static void __clk_disable(const struct stm32mp1_clk_gate *gate) 952 { 953 vaddr_t base = stm32_rcc_base(); 954 uint32_t bit = BIT(gate->bit); 955 956 if (gate->set_clr) 957 io_write32(base + gate->offset + RCC_MP_ENCLRR_OFFSET, bit); 958 else 959 io_clrbits32_stm32shregs(base + gate->offset, bit); 960 961 FMSG("Clock %u has been disabled", gate->clock_id); 962 } 963 964 static long get_timer_rate(long parent_rate, unsigned int apb_bus) 965 { 966 uint32_t timgxpre = 0; 967 uint32_t apbxdiv = 0; 968 vaddr_t rcc_base = stm32_rcc_base(); 969 970 switch (apb_bus) { 971 case 1: 972 apbxdiv = io_read32(rcc_base + RCC_APB1DIVR) & 973 RCC_APBXDIV_MASK; 974 timgxpre = io_read32(rcc_base + RCC_TIMG1PRER) & 975 RCC_TIMGXPRER_TIMGXPRE; 976 break; 977 case 2: 978 apbxdiv = io_read32(rcc_base + RCC_APB2DIVR) & 979 RCC_APBXDIV_MASK; 980 timgxpre = io_read32(rcc_base + RCC_TIMG2PRER) & 981 RCC_TIMGXPRER_TIMGXPRE; 982 break; 983 default: 984 panic(); 985 break; 986 } 987 988 if (apbxdiv == 0) 989 return parent_rate; 990 991 return parent_rate * (timgxpre + 1) * 2; 992 } 993 994 static unsigned long _stm32_clock_get_rate(unsigned long id) 995 { 996 enum stm32mp1_parent_id p = _UNKNOWN_ID; 997 unsigned long rate = 0; 998 999 p = stm32mp1_clk_get_parent(id); 1000 if (p < 0) 1001 return 0; 1002 1003 rate = get_clock_rate(p); 1004 1005 if ((id >= TIM2_K) && (id <= TIM14_K)) 1006 rate = get_timer_rate(rate, 1); 1007 1008 if ((id >= TIM1_K) && (id <= TIM17_K)) 1009 rate = get_timer_rate(rate, 2); 1010 1011 return rate; 1012 } 1013 1014 /* 1015 * Get the parent ID of the target parent clock, or -1 if no parent found. 1016 */ 1017 static enum stm32mp1_parent_id get_parent_id_parent(enum stm32mp1_parent_id id) 1018 { 1019 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 1020 enum stm32mp1_pll_id pll_id = _PLL_NB; 1021 uint32_t p_sel = 0; 1022 1023 switch (id) { 1024 case _ACLK: 1025 case _PCLK4: 1026 case _PCLK5: 1027 s = _AXISS_SEL; 1028 break; 1029 case _PLL1_P: 1030 case _PLL1_Q: 1031 case _PLL1_R: 1032 pll_id = _PLL1; 1033 break; 1034 case _PLL2_P: 1035 case _PLL2_Q: 1036 case _PLL2_R: 1037 pll_id = _PLL2; 1038 break; 1039 case _PLL3_P: 1040 case _PLL3_Q: 1041 case _PLL3_R: 1042 pll_id = _PLL3; 1043 break; 1044 case _PLL4_P: 1045 case _PLL4_Q: 1046 case _PLL4_R: 1047 pll_id = _PLL4; 1048 break; 1049 case _PCLK1: 1050 case _PCLK2: 1051 case _HCLK2: 1052 case _HCLK6: 1053 case _CK_PER: 1054 case _CK_MPU: 1055 case _CK_MCU: 1056 case _USB_PHY_48: 1057 /* We do not expected to access these */ 1058 panic(); 1059 break; 1060 default: 1061 /* Other parents have no parent */ 1062 return -1; 1063 } 1064 1065 if (s != _UNKNOWN_SEL) { 1066 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 1067 vaddr_t rcc_base = stm32_rcc_base(); 1068 1069 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & 1070 sel->msk; 1071 1072 if (p_sel < sel->nb_parent) 1073 return sel->parent[p_sel]; 1074 } else { 1075 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1076 1077 p_sel = io_read32(stm32_rcc_base() + pll->rckxselr) & 1078 RCC_SELR_REFCLK_SRC_MASK; 1079 1080 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) 1081 return osc_id2parent_id(pll->refclk[p_sel]); 1082 } 1083 1084 FMSG("No parent found for %s", stm32mp1_clk_parent_name[id]); 1085 return -1; 1086 } 1087 1088 /* We are only interested in knowing if PLL3 shall be secure or not */ 1089 static void secure_parent_clocks(enum stm32mp1_parent_id parent_id) 1090 { 1091 enum stm32mp1_parent_id grandparent_id = _UNKNOWN_ID; 1092 1093 switch (parent_id) { 1094 case _ACLK: 1095 case _HCLK2: 1096 case _HCLK5: 1097 case _HCLK6: 1098 case _PCLK4: 1099 case _PCLK5: 1100 /* Intermediate clock mux or clock, go deeper in clock tree */ 1101 break; 1102 case _HSI: 1103 case _HSI_KER: 1104 case _LSI: 1105 case _CSI: 1106 case _CSI_KER: 1107 case _HSE: 1108 case _HSE_KER: 1109 case _HSE_KER_DIV2: 1110 case _HSE_RTC: 1111 case _LSE: 1112 case _PLL1_P: 1113 case _PLL1_Q: 1114 case _PLL1_R: 1115 case _PLL2_P: 1116 case _PLL2_Q: 1117 case _PLL2_R: 1118 /* Always secure clocks, no need to go further */ 1119 return; 1120 case _PLL3_P: 1121 case _PLL3_Q: 1122 case _PLL3_R: 1123 /* PLL3 is a shared resource, registered and don't go further */ 1124 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 1125 return; 1126 default: 1127 DMSG("Cannot lookup parent clock %s", 1128 stm32mp1_clk_parent_name[parent_id]); 1129 panic(); 1130 } 1131 1132 grandparent_id = get_parent_id_parent(parent_id); 1133 if (grandparent_id >= 0) 1134 secure_parent_clocks(grandparent_id); 1135 } 1136 1137 void stm32mp_register_clock_parents_secure(unsigned long clock_id) 1138 { 1139 enum stm32mp1_parent_id parent_id = stm32mp1_clk_get_parent(clock_id); 1140 1141 if (parent_id < 0) { 1142 DMSG("No parent for clock %lu", clock_id); 1143 return; 1144 } 1145 1146 secure_parent_clocks(parent_id); 1147 } 1148 1149 #ifdef CFG_EMBED_DTB 1150 static const char *stm32mp_osc_node_label[NB_OSC] = { 1151 [OSC_LSI] = "clk-lsi", 1152 [OSC_LSE] = "clk-lse", 1153 [OSC_HSI] = "clk-hsi", 1154 [OSC_HSE] = "clk-hse", 1155 [OSC_CSI] = "clk-csi", 1156 [OSC_I2S_CKIN] = "i2s_ckin", 1157 [OSC_USB_PHY_48] = "ck_usbo_48m" 1158 }; 1159 1160 static unsigned int clk_freq_prop(const void *fdt, int node) 1161 { 1162 const fdt32_t *cuint = NULL; 1163 int ret = 0; 1164 1165 /* Disabled clocks report null rate */ 1166 if (_fdt_get_status(fdt, node) == DT_STATUS_DISABLED) 1167 return 0; 1168 1169 cuint = fdt_getprop(fdt, node, "clock-frequency", &ret); 1170 if (!cuint) 1171 panic(); 1172 1173 return fdt32_to_cpu(*cuint); 1174 } 1175 1176 static void get_osc_freq_from_dt(const void *fdt) 1177 { 1178 enum stm32mp_osc_id idx = _UNKNOWN_OSC_ID; 1179 int clk_node = fdt_path_offset(fdt, "/clocks"); 1180 1181 if (clk_node < 0) 1182 panic(); 1183 1184 COMPILE_TIME_ASSERT((int)OSC_HSI == 0); 1185 for (idx = OSC_HSI; idx < NB_OSC; idx++) { 1186 const char *name = stm32mp_osc_node_label[idx]; 1187 int subnode = 0; 1188 1189 fdt_for_each_subnode(subnode, fdt, clk_node) { 1190 const char *cchar = NULL; 1191 int ret = 0; 1192 1193 cchar = fdt_get_name(fdt, subnode, &ret); 1194 if (!cchar) 1195 panic(); 1196 1197 if (strncmp(cchar, name, (size_t)ret) == 0) { 1198 stm32mp1_osc[idx] = clk_freq_prop(fdt, subnode); 1199 1200 DMSG("Osc %s: %lu Hz", name, stm32mp1_osc[idx]); 1201 break; 1202 } 1203 } 1204 1205 if (!stm32mp1_osc[idx]) 1206 DMSG("Osc %s: no frequency info", name); 1207 } 1208 } 1209 #endif /*CFG_EMBED_DTB*/ 1210 1211 static void enable_static_secure_clocks(void) 1212 { 1213 unsigned int idx = 0; 1214 const unsigned long secure_enable[] = { 1215 DDRC1, DDRC1LP, DDRC2, DDRC2LP, DDRPHYC, DDRPHYCLP, DDRCAPB, 1216 AXIDCG, DDRPHYCAPB, DDRPHYCAPBLP, TZPC, TZC1, TZC2, STGEN_K, 1217 BSEC, 1218 }; 1219 1220 for (idx = 0; idx < ARRAY_SIZE(secure_enable); idx++) { 1221 stm32_clock_enable(secure_enable[idx]); 1222 stm32mp_register_clock_parents_secure(secure_enable[idx]); 1223 } 1224 1225 if (CFG_TEE_CORE_NB_CORE > 1) 1226 stm32_clock_enable(RTCAPB); 1227 } 1228 1229 static void __maybe_unused enable_rcc_tzen(void) 1230 { 1231 io_setbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1232 } 1233 1234 static void __maybe_unused disable_rcc_tzen(void) 1235 { 1236 IMSG("RCC is non-secure"); 1237 io_clrbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1238 } 1239 1240 #ifdef CFG_EMBED_DTB 1241 static TEE_Result stm32mp1_clk_fdt_init(const void *fdt, int node) 1242 { 1243 unsigned int i = 0; 1244 int len = 0; 1245 int ignored = 0; 1246 1247 get_osc_freq_from_dt(fdt); 1248 1249 /* 1250 * OP-TEE core is not in charge of configuring clock parenthood. 1251 * This is expected from an earlier boot stage. Modifying the clock 1252 * tree parenthood here may jeopardize already configured clocks. 1253 * The sequence below ignores such DT directives with a friendly 1254 * debug trace. 1255 */ 1256 if (fdt_getprop(fdt, node, "st,clksrc", &len)) { 1257 DMSG("Ignore source clocks configuration from DT"); 1258 ignored++; 1259 } 1260 if (fdt_getprop(fdt, node, "st,clkdiv", &len)) { 1261 DMSG("Ignore clock divisors configuration from DT"); 1262 ignored++; 1263 } 1264 if (fdt_getprop(fdt, node, "st,pkcs", &len)) { 1265 DMSG("Ignore peripheral clocks tree configuration from DT"); 1266 ignored++; 1267 } 1268 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1269 char name[] = "st,pll@X"; 1270 1271 snprintf(name, sizeof(name), "st,pll@%d", i); 1272 node = fdt_subnode_offset(fdt, node, name); 1273 if (node < 0) 1274 continue; 1275 1276 if (fdt_getprop(fdt, node, "cfg", &len) || 1277 fdt_getprop(fdt, node, "frac", &len)) { 1278 DMSG("Ignore PLL%u configurations from DT", i); 1279 ignored++; 1280 } 1281 } 1282 1283 if (ignored != 0) 1284 IMSG("DT clock tree configurations were ignored"); 1285 1286 return TEE_SUCCESS; 1287 } 1288 #endif /*CFG_EMBED_DTB*/ 1289 1290 /* 1291 * Conversion between clk references and clock gates and clock on internals 1292 * 1293 * stm32mp1_clk first cells follow stm32mp1_clk_gate[] ordering. 1294 * stm32mp1_clk last cells follow stm32mp1_clk_on[] ordering. 1295 */ 1296 static struct clk stm32mp1_clk[ARRAY_SIZE(stm32mp1_clk_gate) + 1297 ARRAY_SIZE(stm32mp1_clk_on)]; 1298 1299 #define CLK_ON_INDEX_OFFSET ((int)ARRAY_SIZE(stm32mp1_clk_gate)) 1300 1301 static bool clk_is_gate(struct clk *clk) 1302 { 1303 int clk_index = clk - stm32mp1_clk; 1304 1305 assert(clk_index >= 0 && clk_index < (int)ARRAY_SIZE(stm32mp1_clk)); 1306 return clk_index < CLK_ON_INDEX_OFFSET; 1307 } 1308 1309 static unsigned long clk_to_clock_id(struct clk *clk) 1310 { 1311 int gate_index = clk - stm32mp1_clk; 1312 int on_index = gate_index - CLK_ON_INDEX_OFFSET; 1313 1314 if (clk_is_gate(clk)) 1315 return stm32mp1_clk_gate[gate_index].clock_id; 1316 1317 return stm32mp1_clk_on[on_index]; 1318 } 1319 1320 static const struct stm32mp1_clk_gate *clk_to_gate_ref(struct clk *clk) 1321 { 1322 int gate_index = clk - stm32mp1_clk; 1323 1324 assert(clk_is_gate(clk)); 1325 1326 return stm32mp1_clk_gate + gate_index; 1327 } 1328 1329 static int clock_id_to_gate_index(unsigned long clock_id) 1330 { 1331 size_t n = 0; 1332 1333 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_gate); n++) 1334 if (stm32mp1_clk_gate[n].clock_id == clock_id) 1335 return n; 1336 1337 return -1; 1338 } 1339 1340 static int clock_id_to_always_on_index(unsigned long clock_id) 1341 { 1342 size_t n = 0; 1343 1344 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_on); n++) 1345 if (stm32mp1_clk_on[n] == clock_id) 1346 return n; 1347 1348 return -1; 1349 } 1350 1351 static struct clk *clock_id_to_clk(unsigned long clock_id) 1352 { 1353 int gate_index = clock_id_to_gate_index(clock_id); 1354 int on_index = clock_id_to_always_on_index(clock_id); 1355 1356 if (gate_index >= 0) 1357 return stm32mp1_clk + gate_index; 1358 1359 if (on_index >= 0) 1360 return stm32mp1_clk + CLK_ON_INDEX_OFFSET + on_index; 1361 1362 return NULL; 1363 } 1364 1365 #if CFG_TEE_CORE_LOG_LEVEL >= TRACE_DEBUG 1366 struct clk_name { 1367 unsigned int clock_id; 1368 const char *name; 1369 }; 1370 1371 #define CLOCK_NAME(_binding, _name) \ 1372 { .clock_id = (_binding), .name = (_name) } 1373 1374 /* Store names only for some clocks */ 1375 const struct clk_name exposed_clk_name[] = { 1376 /* Clocks used by platform drivers not yet probed from DT */ 1377 CLOCK_NAME(CK_DBG, "dbg"), 1378 CLOCK_NAME(CK_MCU, "mcu"), 1379 CLOCK_NAME(RTCAPB, "rtcapb"), 1380 CLOCK_NAME(BKPSRAM, "bkpsram"), 1381 CLOCK_NAME(RTC, "rtc"), 1382 CLOCK_NAME(CRYP1, "crpy1"), 1383 CLOCK_NAME(SYSCFG, "syscfg"), 1384 CLOCK_NAME(GPIOA, "gpioa"), 1385 CLOCK_NAME(GPIOB, "gpiob"), 1386 CLOCK_NAME(GPIOC, "gpioc"), 1387 CLOCK_NAME(GPIOD, "gpiod"), 1388 CLOCK_NAME(GPIOE, "gpioe"), 1389 CLOCK_NAME(GPIOF, "gpiof"), 1390 CLOCK_NAME(GPIOG, "gpiog"), 1391 CLOCK_NAME(GPIOH, "gpioh"), 1392 CLOCK_NAME(GPIOI, "gpioi"), 1393 CLOCK_NAME(GPIOJ, "gpioj"), 1394 CLOCK_NAME(GPIOK, "gpiok"), 1395 CLOCK_NAME(GPIOZ, "gpioz"), 1396 /* Clock exposed by SCMI. SCMI clock fmro DT bindings to come... */ 1397 CLOCK_NAME(CK_HSE, "hse"), 1398 CLOCK_NAME(CK_HSI, "hsi"), 1399 CLOCK_NAME(CK_CSI, "csi"), 1400 CLOCK_NAME(CK_LSE, "lse"), 1401 CLOCK_NAME(CK_LSI, "lsi"), 1402 CLOCK_NAME(PLL2_Q, "pll2q"), 1403 CLOCK_NAME(PLL2_R, "pll2r"), 1404 CLOCK_NAME(PLL3_Q, "pll3q"), 1405 CLOCK_NAME(PLL3_R, "pll3r"), 1406 CLOCK_NAME(CRYP1, "cryp1"), 1407 CLOCK_NAME(HASH1, "hash1"), 1408 CLOCK_NAME(I2C4_K, "i2c4"), 1409 CLOCK_NAME(I2C6_K, "i2c6"), 1410 CLOCK_NAME(IWDG1, "iwdg"), 1411 CLOCK_NAME(RNG1_K, "rng1"), 1412 CLOCK_NAME(SPI6_K, "spi6"), 1413 CLOCK_NAME(USART1_K, "usart1"), 1414 CLOCK_NAME(CK_MCU, "mcu"), 1415 }; 1416 DECLARE_KEEP_PAGER(exposed_clk_name); 1417 1418 static const char *clk_op_get_name(struct clk *clk) 1419 { 1420 unsigned long clock_id = clk_to_clock_id(clk); 1421 size_t n = 0; 1422 1423 for (n = 0; n < ARRAY_SIZE(exposed_clk_name); n++) 1424 if (exposed_clk_name[n].clock_id == clock_id) 1425 return exposed_clk_name[n].name; 1426 1427 return NULL; 1428 } 1429 #else 1430 static const char *clk_op_get_name(struct clk *clk __unused) 1431 { 1432 return NULL; 1433 } 1434 #endif /*CFG_TEE_CORE_LOG_LEVEL*/ 1435 1436 static unsigned long clk_op_compute_rate(struct clk *clk, 1437 unsigned long parent_rate __unused) 1438 { 1439 return _stm32_clock_get_rate(clk_to_clock_id(clk)); 1440 } 1441 1442 static TEE_Result clk_op_enable(struct clk *clk) 1443 { 1444 if (clk_is_gate(clk)) 1445 __clk_enable(clk_to_gate_ref(clk)); 1446 1447 return TEE_SUCCESS; 1448 } 1449 DECLARE_KEEP_PAGER(clk_op_enable); 1450 1451 static void clk_op_disable(struct clk *clk) 1452 { 1453 if (clk_is_gate(clk)) 1454 __clk_disable(clk_to_gate_ref(clk)); 1455 } 1456 DECLARE_KEEP_PAGER(clk_op_disable); 1457 1458 /* This variable is weak to break its dependency chain when linked as unpaged */ 1459 const struct clk_ops stm32mp1_clk_ops 1460 __weak __rodata_unpaged("stm32mp1_clk_ops") = { 1461 .enable = clk_op_enable, 1462 .disable = clk_op_disable, 1463 .get_rate = clk_op_compute_rate, 1464 }; 1465 1466 static TEE_Result register_stm32mp1_clocks(void) 1467 { 1468 TEE_Result res = TEE_ERROR_GENERIC; 1469 size_t n = 0; 1470 1471 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk); n++) { 1472 stm32mp1_clk[n].ops = &stm32mp1_clk_ops; 1473 stm32mp1_clk[n].name = clk_op_get_name(stm32mp1_clk + n); 1474 refcount_set(&stm32mp1_clk[n].enabled_count, 0); 1475 1476 res = clk_register(stm32mp1_clk + n); 1477 if (res) 1478 return res; 1479 } 1480 1481 return TEE_SUCCESS; 1482 } 1483 1484 /* Route platform legacy clock functions to clk driver functions */ 1485 bool stm32_clock_is_enabled(unsigned long clock_id) 1486 { 1487 struct clk *clk = clock_id_to_clk(clock_id); 1488 1489 assert(clk); 1490 return clk_is_enabled(clk); 1491 } 1492 1493 void stm32_clock_enable(unsigned long clock_id) 1494 { 1495 struct clk *clk = clock_id_to_clk(clock_id); 1496 TEE_Result __maybe_unused res = TEE_ERROR_GENERIC; 1497 1498 assert(clk); 1499 res = clk_enable(clk); 1500 assert(!res); 1501 } 1502 1503 void stm32_clock_disable(unsigned long clock_id) 1504 { 1505 struct clk *clk = clock_id_to_clk(clock_id); 1506 1507 assert(clk); 1508 clk_disable(clk); 1509 } 1510 1511 unsigned long stm32_clock_get_rate(unsigned long clock_id) 1512 { 1513 struct clk *clk = clock_id_to_clk(clock_id); 1514 1515 assert(clk); 1516 return clk_get_rate(clk); 1517 } 1518 1519 #ifdef CFG_DRIVERS_CLK_DT 1520 static struct clk *stm32mp1_clk_dt_get_clk(struct dt_driver_phandle_args *pargs, 1521 void *data __unused, TEE_Result *res) 1522 { 1523 unsigned long clock_id = pargs->args[0]; 1524 struct clk *clk = NULL; 1525 1526 *res = TEE_ERROR_BAD_PARAMETERS; 1527 1528 if (pargs->args_count != 1) 1529 return NULL; 1530 1531 clk = clock_id_to_clk(clock_id); 1532 if (!clk) 1533 return NULL; 1534 1535 *res = TEE_SUCCESS; 1536 return clk; 1537 } 1538 1539 /* Non-null reference for compat data */ 1540 static const uint8_t non_secure_rcc; 1541 1542 static TEE_Result stm32mp1_clock_provider_probe(const void *fdt, int offs, 1543 const void *compat_data) 1544 { 1545 TEE_Result res = TEE_ERROR_GENERIC; 1546 1547 if (compat_data == &non_secure_rcc) 1548 disable_rcc_tzen(); 1549 else 1550 enable_rcc_tzen(); 1551 1552 res = stm32mp1_clk_fdt_init(fdt, offs); 1553 if (res) { 1554 EMSG("Failed to initialize clocks from DT: %#"PRIx32, res); 1555 panic(); 1556 } 1557 1558 res = register_stm32mp1_clocks(); 1559 if (res) { 1560 EMSG("Failed to register clocks: %#"PRIx32, res); 1561 panic(); 1562 } 1563 1564 res = clk_dt_register_clk_provider(fdt, offs, stm32mp1_clk_dt_get_clk, 1565 NULL); 1566 if (res) { 1567 EMSG("Failed to register clock provider: %#"PRIx32, res); 1568 panic(); 1569 } 1570 1571 enable_static_secure_clocks(); 1572 1573 return TEE_SUCCESS; 1574 } 1575 1576 static const struct dt_device_match stm32mp1_clock_match_table[] = { 1577 { .compatible = "st,stm32mp1-rcc", .compat_data = &non_secure_rcc, }, 1578 { .compatible = "st,stm32mp1-rcc-secure", }, 1579 { } 1580 }; 1581 1582 DEFINE_DT_DRIVER(stm32mp1_clock_dt_driver) = { 1583 .name = "stm32mp1_clock", 1584 .type = DT_DRIVER_CLK, 1585 .match_table = stm32mp1_clock_match_table, 1586 .probe = stm32mp1_clock_provider_probe, 1587 }; 1588 #else /*CFG_DRIVERS_CLK_DT*/ 1589 static TEE_Result stm32mp1_clk_early_init(void) 1590 { 1591 TEE_Result __maybe_unused res = TEE_ERROR_GENERIC; 1592 1593 res = register_stm32mp1_clocks(); 1594 if (res) { 1595 EMSG("Failed to register clocks: %#"PRIx32, res); 1596 panic(); 1597 } 1598 1599 enable_static_secure_clocks(); 1600 1601 return TEE_SUCCESS; 1602 } 1603 1604 service_init(stm32mp1_clk_early_init); 1605 #endif /*CFG_DRIVERS_CLK_DT*/ 1606