1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0+) 2 /* 3 * Copyright (C) 2018-2019, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/stm32mp1_rcc.h> 9 #include <drivers/clk.h> 10 #include <drivers/clk_dt.h> 11 #include <dt-bindings/clock/stm32mp1-clks.h> 12 #include <initcall.h> 13 #include <io.h> 14 #include <keep.h> 15 #include <kernel/dt.h> 16 #include <kernel/boot.h> 17 #include <kernel/panic.h> 18 #include <kernel/spinlock.h> 19 #include <libfdt.h> 20 #include <platform_config.h> 21 #include <stdio.h> 22 #include <stm32_util.h> 23 #include <trace.h> 24 #include <util.h> 25 26 /* Identifiers for root oscillators */ 27 enum stm32mp_osc_id { 28 _HSI = 0, 29 _HSE, 30 _CSI, 31 _LSI, 32 _LSE, 33 _I2S_CKIN, 34 _USB_PHY_48, 35 NB_OSC, 36 _UNKNOWN_OSC_ID = 0xffU 37 }; 38 39 /* Identifiers for parent clocks */ 40 enum stm32mp1_parent_id { 41 /* 42 * Oscillators are valid IDs for parent clock and are already 43 * defined in enum stm32mp_osc_id, ending at NB_OSC - 1. 44 * This enum defines IDs are the other possible clock parents. 45 */ 46 _HSI_KER = NB_OSC, 47 _HSE_KER, 48 _HSE_KER_DIV2, 49 _CSI_KER, 50 _PLL1_P, 51 _PLL1_Q, 52 _PLL1_R, 53 _PLL2_P, 54 _PLL2_Q, 55 _PLL2_R, 56 _PLL3_P, 57 _PLL3_Q, 58 _PLL3_R, 59 _PLL4_P, 60 _PLL4_Q, 61 _PLL4_R, 62 _ACLK, 63 _PCLK1, 64 _PCLK2, 65 _PCLK3, 66 _PCLK4, 67 _PCLK5, 68 _HCLK5, 69 _HCLK6, 70 _HCLK2, 71 _CK_PER, 72 _CK_MPU, 73 _CK_MCU, 74 _PARENT_NB, 75 _UNKNOWN_ID = 0xff, 76 }; 77 78 /* 79 * Identifiers for parent clock selectors. 80 * This enum lists only the parent clocks we are interested in. 81 */ 82 enum stm32mp1_parent_sel { 83 _STGEN_SEL, 84 _I2C46_SEL, 85 _SPI6_SEL, 86 _USART1_SEL, 87 _RNG1_SEL, 88 _UART6_SEL, 89 _UART24_SEL, 90 _UART35_SEL, 91 _UART78_SEL, 92 _AXISS_SEL, 93 _MCUSS_SEL, 94 _USBPHY_SEL, 95 _USBO_SEL, 96 _RTC_SEL, 97 _PARENT_SEL_NB, 98 _UNKNOWN_SEL = 0xff, 99 }; 100 101 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 102 [_HSE] = CK_HSE, 103 [_HSI] = CK_HSI, 104 [_CSI] = CK_CSI, 105 [_LSE] = CK_LSE, 106 [_LSI] = CK_LSI, 107 [_I2S_CKIN] = _UNKNOWN_ID, 108 [_USB_PHY_48] = _UNKNOWN_ID, 109 [_HSI_KER] = CK_HSI, 110 [_HSE_KER] = CK_HSE, 111 [_HSE_KER_DIV2] = CK_HSE_DIV2, 112 [_CSI_KER] = CK_CSI, 113 [_PLL1_P] = PLL1_P, 114 [_PLL1_Q] = PLL1_Q, 115 [_PLL1_R] = PLL1_R, 116 [_PLL2_P] = PLL2_P, 117 [_PLL2_Q] = PLL2_Q, 118 [_PLL2_R] = PLL2_R, 119 [_PLL3_P] = PLL3_P, 120 [_PLL3_Q] = PLL3_Q, 121 [_PLL3_R] = PLL3_R, 122 [_PLL4_P] = PLL4_P, 123 [_PLL4_Q] = PLL4_Q, 124 [_PLL4_R] = PLL4_R, 125 [_ACLK] = CK_AXI, 126 [_PCLK1] = CK_AXI, 127 [_PCLK2] = CK_AXI, 128 [_PCLK3] = CK_AXI, 129 [_PCLK4] = CK_AXI, 130 [_PCLK5] = CK_AXI, 131 [_HCLK5] = CK_AXI, 132 [_HCLK6] = CK_AXI, 133 [_HCLK2] = CK_AXI, 134 [_CK_PER] = CK_PER, 135 [_CK_MPU] = CK_MPU, 136 [_CK_MCU] = CK_MCU, 137 }; 138 139 static enum stm32mp1_parent_id clock_id2parent_id(unsigned long id) 140 { 141 size_t n = 0; 142 143 COMPILE_TIME_ASSERT(STM32MP1_LAST_CLK < _UNKNOWN_ID); 144 145 for (n = 0; n < ARRAY_SIZE(parent_id_clock_id); n++) 146 if (parent_id_clock_id[n] == id) 147 return (enum stm32mp1_parent_id)n; 148 149 return _UNKNOWN_ID; 150 } 151 152 /* Identifiers for PLLs and their configuration resources */ 153 enum stm32mp1_pll_id { 154 _PLL1, 155 _PLL2, 156 _PLL3, 157 _PLL4, 158 _PLL_NB 159 }; 160 161 enum stm32mp1_div_id { 162 _DIV_P, 163 _DIV_Q, 164 _DIV_R, 165 _DIV_NB, 166 }; 167 168 enum stm32mp1_plltype { 169 PLL_800, 170 PLL_1600, 171 PLL_TYPE_NB 172 }; 173 174 /* 175 * Clock generic gates clocks which state is controlled by a single RCC bit 176 * 177 * @offset: RCC register byte offset from RCC base where clock is controlled 178 * @bit: Bit position in the RCC 32bit register 179 * @clock_id: Identifier used for the clock in the clock driver API 180 * @set_clr: Non-null if and only-if RCC register is a CLEAR/SET register 181 * (CLEAR register is at offset RCC_MP_ENCLRR_OFFSET from SET register) 182 * @secure: One of N_S or SEC, defined below 183 * @sel: _UNKNOWN_ID (fixed parent) or reference to parent clock selector 184 * (8bit storage of ID from enum stm32mp1_parent_sel) 185 * @fixed: _UNKNOWN_ID (selectable paranet) or reference to parent clock 186 * (8bit storage of ID from enum stm32mp1_parent_id) 187 */ 188 struct stm32mp1_clk_gate { 189 uint16_t offset; 190 uint8_t bit; 191 uint8_t clock_id; 192 uint8_t set_clr; 193 uint8_t secure; 194 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 195 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 196 }; 197 198 /* Parent clock selection: select register info, parent clocks references */ 199 struct stm32mp1_clk_sel { 200 uint16_t offset; 201 uint8_t src; 202 uint8_t msk; 203 uint8_t nb_parent; 204 const uint8_t *parent; 205 }; 206 207 #define REFCLK_SIZE 4 208 /* PLL control: type, control register offsets, up-to-4 selectable parent */ 209 struct stm32mp1_clk_pll { 210 enum stm32mp1_plltype plltype; 211 uint16_t rckxselr; 212 uint16_t pllxcfgr1; 213 uint16_t pllxcfgr2; 214 uint16_t pllxfracr; 215 uint16_t pllxcr; 216 uint16_t pllxcsgr; 217 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 218 }; 219 220 #define N_S 0 /* Non-secure can access RCC interface */ 221 #define SEC 1 /* RCC[TZEN] protects RCC interface */ 222 223 /* Clocks with selectable source and not set/clr register access */ 224 #define _CLK_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 225 { \ 226 .offset = (_offset), \ 227 .bit = (_bit), \ 228 .clock_id = (_clock_id), \ 229 .set_clr = 0, \ 230 .secure = (_sec), \ 231 .sel = (_parent_sel), \ 232 .fixed = _UNKNOWN_ID, \ 233 } 234 235 /* Clocks with fixed source and not set/clr register access */ 236 #define _CLK_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 237 { \ 238 .offset = (_offset), \ 239 .bit = (_bit), \ 240 .clock_id = (_clock_id), \ 241 .set_clr = 0, \ 242 .secure = (_sec), \ 243 .sel = _UNKNOWN_SEL, \ 244 .fixed = (_parent), \ 245 } 246 247 /* Clocks with selectable source and set/clr register access */ 248 #define _CLK_SC_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 249 { \ 250 .offset = (_offset), \ 251 .bit = (_bit), \ 252 .clock_id = (_clock_id), \ 253 .set_clr = 1, \ 254 .secure = (_sec), \ 255 .sel = (_parent_sel), \ 256 .fixed = _UNKNOWN_ID, \ 257 } 258 259 /* Clocks with fixed source and set/clr register access */ 260 #define _CLK_SC_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 261 { \ 262 .offset = (_offset), \ 263 .bit = (_bit), \ 264 .clock_id = (_clock_id), \ 265 .set_clr = 1, \ 266 .secure = (_sec), \ 267 .sel = _UNKNOWN_SEL, \ 268 .fixed = (_parent), \ 269 } 270 271 /* 272 * Clocks with selectable source and set/clr register access 273 * and enable bit position defined by a label (argument _bit) 274 */ 275 #define _CLK_SC2_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 276 { \ 277 .offset = (_offset), \ 278 .clock_id = (_clock_id), \ 279 .bit = _offset ## _ ## _bit ## _POS, \ 280 .set_clr = 1, \ 281 .secure = (_sec), \ 282 .sel = (_parent_sel), \ 283 .fixed = _UNKNOWN_ID, \ 284 } 285 #define _CLK_SC2_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 286 { \ 287 .offset = (_offset), \ 288 .clock_id = (_clock_id), \ 289 .bit = _offset ## _ ## _bit ## _POS, \ 290 .set_clr = 1, \ 291 .secure = (_sec), \ 292 .sel = _UNKNOWN_SEL, \ 293 .fixed = (_parent), \ 294 } 295 296 #define _CLK_PARENT(idx, _offset, _src, _mask, _parent) \ 297 [(idx)] = { \ 298 .offset = (_offset), \ 299 .src = (_src), \ 300 .msk = (_mask), \ 301 .parent = (_parent), \ 302 .nb_parent = ARRAY_SIZE(_parent) \ 303 } 304 305 #define _CLK_PLL(_idx, _type, _off1, _off2, _off3, _off4, \ 306 _off5, _off6, _p1, _p2, _p3, _p4) \ 307 [(_idx)] = { \ 308 .plltype = (_type), \ 309 .rckxselr = (_off1), \ 310 .pllxcfgr1 = (_off2), \ 311 .pllxcfgr2 = (_off3), \ 312 .pllxfracr = (_off4), \ 313 .pllxcr = (_off5), \ 314 .pllxcsgr = (_off6), \ 315 .refclk[0] = (_p1), \ 316 .refclk[1] = (_p2), \ 317 .refclk[2] = (_p3), \ 318 .refclk[3] = (_p4), \ 319 } 320 321 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 322 323 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 324 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 325 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 326 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 327 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 328 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 329 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 330 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 331 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 332 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 333 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 334 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 335 336 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, SPI6EN, SPI6_K, _SPI6_SEL), 337 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C4EN, I2C4_K, _I2C46_SEL), 338 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C6EN, I2C6_K, _I2C46_SEL), 339 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, USART1EN, USART1_K, _USART1_SEL), 340 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, RTCAPBEN, RTCAPB, _PCLK5), 341 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC1EN, TZC1, _PCLK5), 342 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC2EN, TZC2, _PCLK5), 343 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZPCEN, TZPC, _PCLK5), 344 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, IWDG1APBEN, IWDG1, _PCLK5), 345 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, BSECEN, BSEC, _PCLK5), 346 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, STGENEN, STGEN_K, _STGEN_SEL), 347 348 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, GPIOZEN, GPIOZ, _HCLK5), 349 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, CRYP1EN, CRYP1, _HCLK5), 350 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, HASH1EN, HASH1, _HCLK5), 351 _CLK_SC2_SELEC(SEC, RCC_MP_AHB5ENSETR, RNG1EN, RNG1_K, _RNG1_SEL), 352 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, BKPSRAMEN, BKPSRAM, _PCLK5), 353 354 _CLK_SC2_FIXED(SEC, RCC_MP_TZAHB6ENSETR, MDMA, MDMA, _HCLK6), 355 356 _CLK_SELEC(SEC, RCC_BDCR, RCC_BDCR_RTCCKEN_POS, RTC, _RTC_SEL), 357 358 /* Non-secure clocks */ 359 #ifdef CFG_WITH_NSEC_GPIOS 360 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_ID), 361 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_ID), 362 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_ID), 363 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_ID), 364 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_ID), 365 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_ID), 366 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_ID), 367 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_ID), 368 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_ID), 369 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_ID), 370 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_ID), 371 #endif 372 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 373 #ifdef CFG_WITH_NSEC_UARTS 374 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 375 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 376 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 377 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 378 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 379 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 380 #endif 381 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 382 #ifdef CFG_WITH_NSEC_UARTS 383 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 384 #endif 385 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 386 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 387 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 388 389 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 390 }; 391 DECLARE_KEEP_PAGER(stm32mp1_clk_gate); 392 393 const uint8_t stm32mp1_clk_on[] = { 394 CK_HSE, CK_CSI, CK_LSI, CK_LSE, CK_HSI, CK_HSE_DIV2, 395 PLL1_P, PLL1_Q, PLL1_R, PLL2_P, PLL2_Q, PLL2_R, PLL3_P, PLL3_Q, PLL3_R, 396 CK_AXI, CK_MPU, CK_MCU, 397 }; 398 399 /* Parents for secure aware clocks in the xxxSELR value ordering */ 400 static const uint8_t stgen_parents[] = { 401 _HSI_KER, _HSE_KER 402 }; 403 404 static const uint8_t i2c46_parents[] = { 405 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 406 }; 407 408 static const uint8_t spi6_parents[] = { 409 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 410 }; 411 412 static const uint8_t usart1_parents[] = { 413 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 414 }; 415 416 static const uint8_t rng1_parents[] = { 417 _CSI, _PLL4_R, _LSE, _LSI 418 }; 419 420 /* Parents for (some) non-secure clocks */ 421 #ifdef CFG_WITH_NSEC_UARTS 422 static const uint8_t uart6_parents[] = { 423 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 424 }; 425 426 static const uint8_t uart234578_parents[] = { 427 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 428 }; 429 #endif 430 431 static const uint8_t axiss_parents[] = { 432 _HSI, _HSE, _PLL2_P 433 }; 434 435 static const uint8_t mcuss_parents[] = { 436 _HSI, _HSE, _CSI, _PLL3_P 437 }; 438 439 static const uint8_t rtc_parents[] = { 440 _UNKNOWN_ID, _LSE, _LSI, _HSE 441 }; 442 443 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 444 /* Secure aware clocks */ 445 _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 446 _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 447 _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents), 448 _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents), 449 _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents), 450 _CLK_PARENT(_RTC_SEL, RCC_BDCR, 0, 0x3, rtc_parents), 451 /* Always non-secure clocks (maybe used in some way in secure world) */ 452 #ifdef CFG_WITH_NSEC_UARTS 453 _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 454 _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents), 455 _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents), 456 _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents), 457 #endif 458 _CLK_PARENT(_AXISS_SEL, RCC_ASSCKSELR, 0, 0x3, axiss_parents), 459 _CLK_PARENT(_MCUSS_SEL, RCC_MSSCKSELR, 0, 0x3, mcuss_parents), 460 }; 461 462 /* PLLNCFGR2 register divider by output */ 463 static const uint8_t pllncfgr2[_DIV_NB] = { 464 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 465 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 466 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 467 }; 468 469 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 470 _CLK_PLL(_PLL1, PLL_1600, 471 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 472 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 473 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 474 _CLK_PLL(_PLL2, PLL_1600, 475 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 476 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 477 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 478 _CLK_PLL(_PLL3, PLL_800, 479 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 480 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 481 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 482 _CLK_PLL(_PLL4, PLL_800, 483 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 484 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 485 _HSI, _HSE, _CSI, _I2S_CKIN), 486 }; 487 488 /* Prescaler table lookups for clock computation */ 489 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 490 static const uint8_t stm32mp1_mcu_div[16] = { 491 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 492 }; 493 494 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 495 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 496 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 497 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 498 0, 1, 2, 3, 4, 4, 4, 4 499 }; 500 501 /* div = /1 /2 /3 /4 */ 502 static const uint8_t stm32mp1_axi_div[8] = { 503 1, 2, 3, 4, 4, 4, 4, 4 504 }; 505 506 static const char __maybe_unused *const stm32mp1_clk_parent_name[_PARENT_NB] = { 507 [_HSI] = "HSI", 508 [_HSE] = "HSE", 509 [_CSI] = "CSI", 510 [_LSI] = "LSI", 511 [_LSE] = "LSE", 512 [_I2S_CKIN] = "I2S_CKIN", 513 [_HSI_KER] = "HSI_KER", 514 [_HSE_KER] = "HSE_KER", 515 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 516 [_CSI_KER] = "CSI_KER", 517 [_PLL1_P] = "PLL1_P", 518 [_PLL1_Q] = "PLL1_Q", 519 [_PLL1_R] = "PLL1_R", 520 [_PLL2_P] = "PLL2_P", 521 [_PLL2_Q] = "PLL2_Q", 522 [_PLL2_R] = "PLL2_R", 523 [_PLL3_P] = "PLL3_P", 524 [_PLL3_Q] = "PLL3_Q", 525 [_PLL3_R] = "PLL3_R", 526 [_PLL4_P] = "PLL4_P", 527 [_PLL4_Q] = "PLL4_Q", 528 [_PLL4_R] = "PLL4_R", 529 [_ACLK] = "ACLK", 530 [_PCLK1] = "PCLK1", 531 [_PCLK2] = "PCLK2", 532 [_PCLK3] = "PCLK3", 533 [_PCLK4] = "PCLK4", 534 [_PCLK5] = "PCLK5", 535 [_HCLK5] = "HCLK5", 536 [_HCLK6] = "HCLK6", 537 [_HCLK2] = "HCLK2", 538 [_CK_PER] = "CK_PER", 539 [_CK_MPU] = "CK_MPU", 540 [_CK_MCU] = "CK_MCU", 541 [_USB_PHY_48] = "USB_PHY_48", 542 }; 543 544 /* 545 * Oscillator frequency in Hz. This array shall be initialized 546 * according to platform. 547 */ 548 static unsigned long stm32mp1_osc[NB_OSC]; 549 550 static unsigned long osc_frequency(enum stm32mp_osc_id idx) 551 { 552 if (idx >= ARRAY_SIZE(stm32mp1_osc)) { 553 DMSG("clk id %d not found", idx); 554 return 0; 555 } 556 557 return stm32mp1_osc[idx]; 558 } 559 560 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 561 { 562 return &stm32mp1_clk_gate[idx]; 563 } 564 565 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 566 { 567 return &stm32mp1_clk_sel[idx]; 568 } 569 570 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 571 { 572 return &stm32mp1_clk_pll[idx]; 573 } 574 575 static int stm32mp1_clk_get_gated_id(unsigned long id) 576 { 577 unsigned int i = 0; 578 579 for (i = 0; i < NB_GATES; i++) 580 if (gate_ref(i)->clock_id == id) 581 return i; 582 583 DMSG("clk id %lu not found", id); 584 return -1; 585 } 586 587 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 588 { 589 return (enum stm32mp1_parent_sel)gate_ref(i)->sel; 590 } 591 592 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 593 { 594 return (enum stm32mp1_parent_id)gate_ref(i)->fixed; 595 } 596 597 static int stm32mp1_clk_get_parent(unsigned long id) 598 { 599 const struct stm32mp1_clk_sel *sel = NULL; 600 enum stm32mp1_parent_id parent_id = 0; 601 uint32_t p_sel = 0; 602 int i = 0; 603 enum stm32mp1_parent_id p = _UNKNOWN_ID; 604 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 605 vaddr_t rcc_base = stm32_rcc_base(); 606 607 parent_id = clock_id2parent_id(id); 608 if (parent_id != _UNKNOWN_ID) 609 return (int)parent_id; 610 611 i = stm32mp1_clk_get_gated_id(id); 612 if (i < 0) 613 panic(); 614 615 p = stm32mp1_clk_get_fixed_parent(i); 616 if (p < _PARENT_NB) 617 return (int)p; 618 619 s = stm32mp1_clk_get_sel(i); 620 if (s == _UNKNOWN_SEL) 621 return -1; 622 if (s >= _PARENT_SEL_NB) 623 panic(); 624 625 sel = clk_sel_ref(s); 626 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & sel->msk; 627 if (p_sel < sel->nb_parent) 628 return (int)sel->parent[p_sel]; 629 630 DMSG("No parent selected for clk %lu", id); 631 return -1; 632 } 633 634 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 635 { 636 uint32_t selr = io_read32(stm32_rcc_base() + pll->rckxselr); 637 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 638 639 return osc_frequency(pll->refclk[src]); 640 } 641 642 /* 643 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 644 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 645 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 646 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 647 */ 648 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 649 { 650 unsigned long refclk = 0; 651 unsigned long fvco = 0; 652 uint32_t cfgr1 = 0; 653 uint32_t fracr = 0; 654 uint32_t divm = 0; 655 uint32_t divn = 0; 656 657 cfgr1 = io_read32(stm32_rcc_base() + pll->pllxcfgr1); 658 fracr = io_read32(stm32_rcc_base() + pll->pllxfracr); 659 660 divm = (cfgr1 & RCC_PLLNCFGR1_DIVM_MASK) >> RCC_PLLNCFGR1_DIVM_SHIFT; 661 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 662 663 refclk = stm32mp1_pll_get_fref(pll); 664 665 /* 666 * With FRACV : 667 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 668 * Without FRACV 669 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 670 */ 671 if (fracr & RCC_PLLNFRACR_FRACLE) { 672 unsigned long long numerator = 0; 673 unsigned long long denominator = 0; 674 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 675 RCC_PLLNFRACR_FRACV_SHIFT; 676 677 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 678 numerator = refclk * numerator; 679 denominator = ((unsigned long long)divm + 1U) << 13; 680 fvco = (unsigned long)(numerator / denominator); 681 } else { 682 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 683 } 684 685 return fvco; 686 } 687 688 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 689 enum stm32mp1_div_id div_id) 690 { 691 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 692 unsigned long dfout = 0; 693 uint32_t cfgr2 = 0; 694 uint32_t divy = 0; 695 696 if (div_id >= _DIV_NB) 697 return 0; 698 699 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2); 700 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 701 702 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 703 704 return dfout; 705 } 706 707 static unsigned long get_clock_rate(int p) 708 { 709 uint32_t reg = 0; 710 unsigned long clock = 0; 711 vaddr_t rcc_base = stm32_rcc_base(); 712 713 switch (p) { 714 case _CK_MPU: 715 /* MPU sub system */ 716 reg = io_read32(rcc_base + RCC_MPCKSELR); 717 switch (reg & RCC_SELR_SRC_MASK) { 718 case RCC_MPCKSELR_HSI: 719 clock = osc_frequency(_HSI); 720 break; 721 case RCC_MPCKSELR_HSE: 722 clock = osc_frequency(_HSE); 723 break; 724 case RCC_MPCKSELR_PLL: 725 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 726 break; 727 case RCC_MPCKSELR_PLL_MPUDIV: 728 reg = io_read32(rcc_base + RCC_MPCKDIVR); 729 if (reg & RCC_MPUDIV_MASK) 730 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P) >> 731 stm32mp1_mpu_div[reg & RCC_MPUDIV_MASK]; 732 else 733 clock = 0; 734 break; 735 default: 736 break; 737 } 738 break; 739 /* AXI sub system */ 740 case _ACLK: 741 case _HCLK2: 742 case _HCLK5: 743 case _HCLK6: 744 case _PCLK4: 745 case _PCLK5: 746 reg = io_read32(rcc_base + RCC_ASSCKSELR); 747 switch (reg & RCC_SELR_SRC_MASK) { 748 case RCC_ASSCKSELR_HSI: 749 clock = osc_frequency(_HSI); 750 break; 751 case RCC_ASSCKSELR_HSE: 752 clock = osc_frequency(_HSE); 753 break; 754 case RCC_ASSCKSELR_PLL: 755 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 756 break; 757 default: 758 break; 759 } 760 761 /* System clock divider */ 762 reg = io_read32(rcc_base + RCC_AXIDIVR); 763 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 764 765 switch (p) { 766 case _PCLK4: 767 reg = io_read32(rcc_base + RCC_APB4DIVR); 768 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 769 break; 770 case _PCLK5: 771 reg = io_read32(rcc_base + RCC_APB5DIVR); 772 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 773 break; 774 default: 775 break; 776 } 777 break; 778 /* MCU sub system */ 779 case _CK_MCU: 780 case _PCLK1: 781 case _PCLK2: 782 case _PCLK3: 783 reg = io_read32(rcc_base + RCC_MSSCKSELR); 784 switch (reg & RCC_SELR_SRC_MASK) { 785 case RCC_MSSCKSELR_HSI: 786 clock = osc_frequency(_HSI); 787 break; 788 case RCC_MSSCKSELR_HSE: 789 clock = osc_frequency(_HSE); 790 break; 791 case RCC_MSSCKSELR_CSI: 792 clock = osc_frequency(_CSI); 793 break; 794 case RCC_MSSCKSELR_PLL: 795 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 796 break; 797 default: 798 break; 799 } 800 801 /* MCU clock divider */ 802 reg = io_read32(rcc_base + RCC_MCUDIVR); 803 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 804 805 switch (p) { 806 case _PCLK1: 807 reg = io_read32(rcc_base + RCC_APB1DIVR); 808 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 809 break; 810 case _PCLK2: 811 reg = io_read32(rcc_base + RCC_APB2DIVR); 812 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 813 break; 814 case _PCLK3: 815 reg = io_read32(rcc_base + RCC_APB3DIVR); 816 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 817 break; 818 case _CK_MCU: 819 default: 820 break; 821 } 822 break; 823 case _CK_PER: 824 reg = io_read32(rcc_base + RCC_CPERCKSELR); 825 switch (reg & RCC_SELR_SRC_MASK) { 826 case RCC_CPERCKSELR_HSI: 827 clock = osc_frequency(_HSI); 828 break; 829 case RCC_CPERCKSELR_HSE: 830 clock = osc_frequency(_HSE); 831 break; 832 case RCC_CPERCKSELR_CSI: 833 clock = osc_frequency(_CSI); 834 break; 835 default: 836 break; 837 } 838 break; 839 case _HSI: 840 case _HSI_KER: 841 clock = osc_frequency(_HSI); 842 break; 843 case _CSI: 844 case _CSI_KER: 845 clock = osc_frequency(_CSI); 846 break; 847 case _HSE: 848 case _HSE_KER: 849 clock = osc_frequency(_HSE); 850 break; 851 case _HSE_KER_DIV2: 852 clock = osc_frequency(_HSE) >> 1; 853 break; 854 case _LSI: 855 clock = osc_frequency(_LSI); 856 break; 857 case _LSE: 858 clock = osc_frequency(_LSE); 859 break; 860 /* PLL */ 861 case _PLL1_P: 862 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 863 break; 864 case _PLL1_Q: 865 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 866 break; 867 case _PLL1_R: 868 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 869 break; 870 case _PLL2_P: 871 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 872 break; 873 case _PLL2_Q: 874 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 875 break; 876 case _PLL2_R: 877 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 878 break; 879 case _PLL3_P: 880 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 881 break; 882 case _PLL3_Q: 883 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 884 break; 885 case _PLL3_R: 886 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 887 break; 888 case _PLL4_P: 889 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 890 break; 891 case _PLL4_Q: 892 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 893 break; 894 case _PLL4_R: 895 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 896 break; 897 /* Other */ 898 case _USB_PHY_48: 899 clock = osc_frequency(_USB_PHY_48); 900 break; 901 default: 902 break; 903 } 904 905 return clock; 906 } 907 908 static void __clk_enable(const struct stm32mp1_clk_gate *gate) 909 { 910 vaddr_t base = stm32_rcc_base(); 911 uint32_t bit = BIT(gate->bit); 912 913 if (gate->set_clr) 914 io_write32(base + gate->offset, bit); 915 else 916 io_setbits32_stm32shregs(base + gate->offset, bit); 917 918 FMSG("Clock %u has been enabled", gate->clock_id); 919 } 920 921 static void __clk_disable(const struct stm32mp1_clk_gate *gate) 922 { 923 vaddr_t base = stm32_rcc_base(); 924 uint32_t bit = BIT(gate->bit); 925 926 if (gate->set_clr) 927 io_write32(base + gate->offset + RCC_MP_ENCLRR_OFFSET, bit); 928 else 929 io_clrbits32_stm32shregs(base + gate->offset, bit); 930 931 FMSG("Clock %u has been disabled", gate->clock_id); 932 } 933 934 static long get_timer_rate(long parent_rate, unsigned int apb_bus) 935 { 936 uint32_t timgxpre = 0; 937 uint32_t apbxdiv = 0; 938 vaddr_t rcc_base = stm32_rcc_base(); 939 940 switch (apb_bus) { 941 case 1: 942 apbxdiv = io_read32(rcc_base + RCC_APB1DIVR) & 943 RCC_APBXDIV_MASK; 944 timgxpre = io_read32(rcc_base + RCC_TIMG1PRER) & 945 RCC_TIMGXPRER_TIMGXPRE; 946 break; 947 case 2: 948 apbxdiv = io_read32(rcc_base + RCC_APB2DIVR) & 949 RCC_APBXDIV_MASK; 950 timgxpre = io_read32(rcc_base + RCC_TIMG2PRER) & 951 RCC_TIMGXPRER_TIMGXPRE; 952 break; 953 default: 954 panic(); 955 break; 956 } 957 958 if (apbxdiv == 0) 959 return parent_rate; 960 961 return parent_rate * (timgxpre + 1) * 2; 962 } 963 964 static unsigned long _stm32_clock_get_rate(unsigned long id) 965 { 966 int p = 0; 967 unsigned long rate = 0; 968 969 p = stm32mp1_clk_get_parent(id); 970 if (p < 0) 971 return 0; 972 973 rate = get_clock_rate(p); 974 975 if ((id >= TIM2_K) && (id <= TIM14_K)) 976 rate = get_timer_rate(rate, 1); 977 978 if ((id >= TIM1_K) && (id <= TIM17_K)) 979 rate = get_timer_rate(rate, 2); 980 981 return rate; 982 } 983 984 /* 985 * Get the parent ID of the target parent clock, or -1 if no parent found. 986 */ 987 static int get_parent_id_parent(unsigned int parent_id) 988 { 989 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 990 enum stm32mp1_pll_id pll_id = _PLL_NB; 991 uint32_t p_sel = 0; 992 993 switch (parent_id) { 994 case _ACLK: 995 case _PCLK4: 996 case _PCLK5: 997 s = _AXISS_SEL; 998 break; 999 case _PLL1_P: 1000 case _PLL1_Q: 1001 case _PLL1_R: 1002 pll_id = _PLL1; 1003 break; 1004 case _PLL2_P: 1005 case _PLL2_Q: 1006 case _PLL2_R: 1007 pll_id = _PLL2; 1008 break; 1009 case _PLL3_P: 1010 case _PLL3_Q: 1011 case _PLL3_R: 1012 pll_id = _PLL3; 1013 break; 1014 case _PLL4_P: 1015 case _PLL4_Q: 1016 case _PLL4_R: 1017 pll_id = _PLL4; 1018 break; 1019 case _PCLK1: 1020 case _PCLK2: 1021 case _HCLK2: 1022 case _HCLK6: 1023 case _CK_PER: 1024 case _CK_MPU: 1025 case _CK_MCU: 1026 case _USB_PHY_48: 1027 /* We do not expected to access these */ 1028 panic(); 1029 break; 1030 default: 1031 /* Other parents have no parent */ 1032 return -1; 1033 } 1034 1035 if (s != _UNKNOWN_SEL) { 1036 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 1037 vaddr_t rcc_base = stm32_rcc_base(); 1038 1039 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & 1040 sel->msk; 1041 1042 if (p_sel < sel->nb_parent) 1043 return sel->parent[p_sel]; 1044 } else { 1045 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1046 1047 p_sel = io_read32(stm32_rcc_base() + pll->rckxselr) & 1048 RCC_SELR_REFCLK_SRC_MASK; 1049 1050 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) 1051 return pll->refclk[p_sel]; 1052 } 1053 1054 FMSG("No parent found for %s", stm32mp1_clk_parent_name[parent_id]); 1055 return -1; 1056 } 1057 1058 /* We are only interested in knowing if PLL3 shall be secure or not */ 1059 static void secure_parent_clocks(unsigned long parent_id) 1060 { 1061 int grandparent_id = 0; 1062 1063 switch (parent_id) { 1064 case _ACLK: 1065 case _HCLK2: 1066 case _HCLK5: 1067 case _HCLK6: 1068 case _PCLK4: 1069 case _PCLK5: 1070 /* Intermediate clock mux or clock, go deeper in clock tree */ 1071 break; 1072 case _HSI: 1073 case _HSI_KER: 1074 case _LSI: 1075 case _CSI: 1076 case _CSI_KER: 1077 case _HSE: 1078 case _HSE_KER: 1079 case _HSE_KER_DIV2: 1080 case _LSE: 1081 case _PLL1_P: 1082 case _PLL1_Q: 1083 case _PLL1_R: 1084 case _PLL2_P: 1085 case _PLL2_Q: 1086 case _PLL2_R: 1087 /* Always secure clocks, no need to go further */ 1088 return; 1089 case _PLL3_P: 1090 case _PLL3_Q: 1091 case _PLL3_R: 1092 /* PLL3 is a shared resource, registered and don't go further */ 1093 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 1094 return; 1095 default: 1096 DMSG("Cannot lookup parent clock %s", 1097 stm32mp1_clk_parent_name[parent_id]); 1098 panic(); 1099 } 1100 1101 grandparent_id = get_parent_id_parent(parent_id); 1102 if (grandparent_id >= 0) 1103 secure_parent_clocks(grandparent_id); 1104 } 1105 1106 void stm32mp_register_clock_parents_secure(unsigned long clock_id) 1107 { 1108 int parent_id = stm32mp1_clk_get_parent(clock_id); 1109 1110 if (parent_id < 0) { 1111 DMSG("No parent for clock %lu", clock_id); 1112 return; 1113 } 1114 1115 secure_parent_clocks(parent_id); 1116 } 1117 1118 #ifdef CFG_EMBED_DTB 1119 static const char *stm32mp_osc_node_label[NB_OSC] = { 1120 [_LSI] = "clk-lsi", 1121 [_LSE] = "clk-lse", 1122 [_HSI] = "clk-hsi", 1123 [_HSE] = "clk-hse", 1124 [_CSI] = "clk-csi", 1125 [_I2S_CKIN] = "i2s_ckin", 1126 [_USB_PHY_48] = "ck_usbo_48m" 1127 }; 1128 1129 static unsigned int clk_freq_prop(const void *fdt, int node) 1130 { 1131 const fdt32_t *cuint = NULL; 1132 int ret = 0; 1133 1134 /* Disabled clocks report null rate */ 1135 if (_fdt_get_status(fdt, node) == DT_STATUS_DISABLED) 1136 return 0; 1137 1138 cuint = fdt_getprop(fdt, node, "clock-frequency", &ret); 1139 if (!cuint) 1140 panic(); 1141 1142 return fdt32_to_cpu(*cuint); 1143 } 1144 1145 static void get_osc_freq_from_dt(const void *fdt) 1146 { 1147 enum stm32mp_osc_id idx = _UNKNOWN_OSC_ID; 1148 int clk_node = fdt_path_offset(fdt, "/clocks"); 1149 1150 if (clk_node < 0) 1151 panic(); 1152 1153 COMPILE_TIME_ASSERT((int)_HSI == 0); 1154 for (idx = _HSI; idx < NB_OSC; idx++) { 1155 const char *name = stm32mp_osc_node_label[idx]; 1156 int subnode = 0; 1157 1158 fdt_for_each_subnode(subnode, fdt, clk_node) { 1159 const char *cchar = NULL; 1160 int ret = 0; 1161 1162 cchar = fdt_get_name(fdt, subnode, &ret); 1163 if (!cchar) 1164 panic(); 1165 1166 if (strncmp(cchar, name, (size_t)ret) == 0) { 1167 stm32mp1_osc[idx] = clk_freq_prop(fdt, subnode); 1168 1169 DMSG("Osc %s: %lu Hz", name, stm32mp1_osc[idx]); 1170 break; 1171 } 1172 } 1173 1174 if (!stm32mp1_osc[idx]) 1175 DMSG("Osc %s: no frequency info", name); 1176 } 1177 } 1178 #endif /*CFG_EMBED_DTB*/ 1179 1180 static void enable_static_secure_clocks(void) 1181 { 1182 unsigned int idx = 0; 1183 const unsigned long secure_enable[] = { 1184 DDRC1, DDRC1LP, DDRC2, DDRC2LP, DDRPHYC, DDRPHYCLP, DDRCAPB, 1185 AXIDCG, DDRPHYCAPB, DDRPHYCAPBLP, TZPC, TZC1, TZC2, STGEN_K, 1186 BSEC, 1187 }; 1188 1189 for (idx = 0; idx < ARRAY_SIZE(secure_enable); idx++) { 1190 stm32_clock_enable(secure_enable[idx]); 1191 stm32mp_register_clock_parents_secure(secure_enable[idx]); 1192 } 1193 1194 if (CFG_TEE_CORE_NB_CORE > 1) 1195 stm32_clock_enable(RTCAPB); 1196 } 1197 1198 static void __maybe_unused enable_rcc_tzen(void) 1199 { 1200 io_setbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1201 } 1202 1203 static void __maybe_unused disable_rcc_tzen(void) 1204 { 1205 IMSG("RCC is non-secure"); 1206 io_clrbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1207 } 1208 1209 #ifdef CFG_EMBED_DTB 1210 static TEE_Result stm32mp1_clk_fdt_init(const void *fdt, int node) 1211 { 1212 unsigned int i = 0; 1213 int len = 0; 1214 int ignored = 0; 1215 1216 get_osc_freq_from_dt(fdt); 1217 1218 /* 1219 * OP-TEE core is not in charge of configuring clock parenthood. 1220 * This is expected from an earlier boot stage. Modifying the clock 1221 * tree parenthood here may jeopardize already configured clocks. 1222 * The sequence below ignores such DT directives with a friendly 1223 * debug trace. 1224 */ 1225 if (fdt_getprop(fdt, node, "st,clksrc", &len)) { 1226 DMSG("Ignore source clocks configuration from DT"); 1227 ignored++; 1228 } 1229 if (fdt_getprop(fdt, node, "st,clkdiv", &len)) { 1230 DMSG("Ignore clock divisors configuration from DT"); 1231 ignored++; 1232 } 1233 if (fdt_getprop(fdt, node, "st,pkcs", &len)) { 1234 DMSG("Ignore peripheral clocks tree configuration from DT"); 1235 ignored++; 1236 } 1237 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1238 char name[] = "st,pll@X"; 1239 1240 snprintf(name, sizeof(name), "st,pll@%d", i); 1241 node = fdt_subnode_offset(fdt, node, name); 1242 if (node < 0) 1243 continue; 1244 1245 if (fdt_getprop(fdt, node, "cfg", &len) || 1246 fdt_getprop(fdt, node, "frac", &len)) { 1247 DMSG("Ignore PLL%u configurations from DT", i); 1248 ignored++; 1249 } 1250 } 1251 1252 if (ignored != 0) 1253 IMSG("DT clock tree configurations were ignored"); 1254 1255 return TEE_SUCCESS; 1256 } 1257 #endif /*CFG_EMBED_DTB*/ 1258 1259 /* 1260 * Conversion between clk references and clock gates and clock on internals 1261 * 1262 * stm32mp1_clk first cells follow stm32mp1_clk_gate[] ordering. 1263 * stm32mp1_clk last cells follow stm32mp1_clk_on[] ordering. 1264 */ 1265 static struct clk stm32mp1_clk[ARRAY_SIZE(stm32mp1_clk_gate) + 1266 ARRAY_SIZE(stm32mp1_clk_on)]; 1267 1268 #define CLK_ON_INDEX_OFFSET ((int)ARRAY_SIZE(stm32mp1_clk_gate)) 1269 1270 static bool clk_is_gate(struct clk *clk) 1271 { 1272 int clk_index = clk - stm32mp1_clk; 1273 1274 assert(clk_index >= 0 && clk_index < (int)ARRAY_SIZE(stm32mp1_clk)); 1275 return clk_index < CLK_ON_INDEX_OFFSET; 1276 } 1277 1278 static unsigned long clk_to_clock_id(struct clk *clk) 1279 { 1280 int gate_index = clk - stm32mp1_clk; 1281 int on_index = gate_index - CLK_ON_INDEX_OFFSET; 1282 1283 if (clk_is_gate(clk)) 1284 return stm32mp1_clk_gate[gate_index].clock_id; 1285 1286 return stm32mp1_clk_on[on_index]; 1287 } 1288 1289 static const struct stm32mp1_clk_gate *clk_to_gate_ref(struct clk *clk) 1290 { 1291 int gate_index = clk - stm32mp1_clk; 1292 1293 assert(clk_is_gate(clk)); 1294 1295 return stm32mp1_clk_gate + gate_index; 1296 } 1297 1298 static int clock_id_to_gate_index(unsigned long clock_id) 1299 { 1300 size_t n = 0; 1301 1302 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_gate); n++) 1303 if (stm32mp1_clk_gate[n].clock_id == clock_id) 1304 return n; 1305 1306 return -1; 1307 } 1308 1309 static int clock_id_to_always_on_index(unsigned long clock_id) 1310 { 1311 size_t n = 0; 1312 1313 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_on); n++) 1314 if (stm32mp1_clk_on[n] == clock_id) 1315 return n; 1316 1317 return -1; 1318 } 1319 1320 static struct clk *clock_id_to_clk(unsigned long clock_id) 1321 { 1322 int gate_index = clock_id_to_gate_index(clock_id); 1323 int on_index = clock_id_to_always_on_index(clock_id); 1324 1325 if (gate_index >= 0) 1326 return stm32mp1_clk + gate_index; 1327 1328 if (on_index >= 0) 1329 return stm32mp1_clk + CLK_ON_INDEX_OFFSET + on_index; 1330 1331 return NULL; 1332 } 1333 1334 #if CFG_TEE_CORE_LOG_LEVEL >= TRACE_DEBUG 1335 struct clk_name { 1336 unsigned int clock_id; 1337 const char *name; 1338 }; 1339 1340 #define CLOCK_NAME(_binding, _name) \ 1341 { .clock_id = (_binding), .name = (_name) } 1342 1343 /* Store names only for some clocks */ 1344 const struct clk_name exposed_clk_name[] = { 1345 /* Clocks used by platform drivers not yet probed from DT */ 1346 CLOCK_NAME(CK_DBG, "dbg"), 1347 CLOCK_NAME(CK_MCU, "mcu"), 1348 CLOCK_NAME(RTCAPB, "rtcapb"), 1349 CLOCK_NAME(BKPSRAM, "bkpsram"), 1350 CLOCK_NAME(RTC, "rtc"), 1351 CLOCK_NAME(CRYP1, "crpy1"), 1352 CLOCK_NAME(SYSCFG, "syscfg"), 1353 CLOCK_NAME(GPIOA, "gpioa"), 1354 CLOCK_NAME(GPIOB, "gpiob"), 1355 CLOCK_NAME(GPIOC, "gpioc"), 1356 CLOCK_NAME(GPIOD, "gpiod"), 1357 CLOCK_NAME(GPIOE, "gpioe"), 1358 CLOCK_NAME(GPIOF, "gpiof"), 1359 CLOCK_NAME(GPIOG, "gpiog"), 1360 CLOCK_NAME(GPIOH, "gpioh"), 1361 CLOCK_NAME(GPIOI, "gpioi"), 1362 CLOCK_NAME(GPIOJ, "gpioj"), 1363 CLOCK_NAME(GPIOK, "gpiok"), 1364 CLOCK_NAME(GPIOZ, "gpioz"), 1365 /* Clock exposed by SCMI. SCMI clock fmro DT bindings to come... */ 1366 CLOCK_NAME(CK_HSE, "hse"), 1367 CLOCK_NAME(CK_HSI, "hsi"), 1368 CLOCK_NAME(CK_CSI, "csi"), 1369 CLOCK_NAME(CK_LSE, "lse"), 1370 CLOCK_NAME(CK_LSI, "lsi"), 1371 CLOCK_NAME(PLL2_Q, "pll2q"), 1372 CLOCK_NAME(PLL2_R, "pll2r"), 1373 CLOCK_NAME(PLL3_Q, "pll3q"), 1374 CLOCK_NAME(PLL3_R, "pll3r"), 1375 CLOCK_NAME(CRYP1, "cryp1"), 1376 CLOCK_NAME(HASH1, "hash1"), 1377 CLOCK_NAME(I2C4_K, "i2c4"), 1378 CLOCK_NAME(I2C6_K, "i2c6"), 1379 CLOCK_NAME(IWDG1, "iwdg"), 1380 CLOCK_NAME(RNG1_K, "rng1"), 1381 CLOCK_NAME(SPI6_K, "spi6"), 1382 CLOCK_NAME(USART1_K, "usart1"), 1383 CLOCK_NAME(CK_MCU, "mcu"), 1384 }; 1385 DECLARE_KEEP_PAGER(exposed_clk_name); 1386 1387 static const char *clk_op_get_name(struct clk *clk) 1388 { 1389 unsigned long clock_id = clk_to_clock_id(clk); 1390 size_t n = 0; 1391 1392 for (n = 0; n < ARRAY_SIZE(exposed_clk_name); n++) 1393 if (exposed_clk_name[n].clock_id == clock_id) 1394 return exposed_clk_name[n].name; 1395 1396 return NULL; 1397 } 1398 #else 1399 static const char *clk_op_get_name(struct clk *clk __unused) 1400 { 1401 return NULL; 1402 } 1403 #endif /*CFG_TEE_CORE_LOG_LEVEL*/ 1404 1405 static unsigned long clk_op_compute_rate(struct clk *clk, 1406 unsigned long parent_rate __unused) 1407 { 1408 return _stm32_clock_get_rate(clk_to_clock_id(clk)); 1409 } 1410 1411 static TEE_Result clk_op_enable(struct clk *clk) 1412 { 1413 if (clk_is_gate(clk)) 1414 __clk_enable(clk_to_gate_ref(clk)); 1415 1416 return TEE_SUCCESS; 1417 } 1418 DECLARE_KEEP_PAGER(clk_op_enable); 1419 1420 static void clk_op_disable(struct clk *clk) 1421 { 1422 if (clk_is_gate(clk)) 1423 __clk_disable(clk_to_gate_ref(clk)); 1424 } 1425 DECLARE_KEEP_PAGER(clk_op_disable); 1426 1427 /* This variable is weak to break its dependency chain when linked as unpaged */ 1428 const struct clk_ops stm32mp1_clk_ops 1429 __weak __rodata_unpaged("stm32mp1_clk_ops") = { 1430 .enable = clk_op_enable, 1431 .disable = clk_op_disable, 1432 .get_rate = clk_op_compute_rate, 1433 }; 1434 1435 static TEE_Result register_stm32mp1_clocks(void) 1436 { 1437 TEE_Result res = TEE_ERROR_GENERIC; 1438 size_t n = 0; 1439 1440 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk); n++) { 1441 stm32mp1_clk[n].ops = &stm32mp1_clk_ops; 1442 stm32mp1_clk[n].name = clk_op_get_name(stm32mp1_clk + n); 1443 refcount_set(&stm32mp1_clk[n].enabled_count, 0); 1444 1445 res = clk_register(stm32mp1_clk + n); 1446 if (res) 1447 return res; 1448 } 1449 1450 return TEE_SUCCESS; 1451 } 1452 1453 /* Route platform legacy clock functions to clk driver functions */ 1454 bool stm32_clock_is_enabled(unsigned long clock_id) 1455 { 1456 struct clk *clk = clock_id_to_clk(clock_id); 1457 1458 assert(clk); 1459 return clk_is_enabled(clk); 1460 } 1461 1462 void stm32_clock_enable(unsigned long clock_id) 1463 { 1464 struct clk *clk = clock_id_to_clk(clock_id); 1465 TEE_Result __maybe_unused res = TEE_ERROR_GENERIC; 1466 1467 assert(clk); 1468 res = clk_enable(clk); 1469 assert(!res); 1470 } 1471 1472 void stm32_clock_disable(unsigned long clock_id) 1473 { 1474 struct clk *clk = clock_id_to_clk(clock_id); 1475 1476 assert(clk); 1477 clk_disable(clk); 1478 } 1479 1480 unsigned long stm32_clock_get_rate(unsigned long clock_id) 1481 { 1482 struct clk *clk = clock_id_to_clk(clock_id); 1483 1484 assert(clk); 1485 return clk_get_rate(clk); 1486 } 1487 1488 #ifdef CFG_DRIVERS_CLK_DT 1489 static struct clk *stm32mp1_clk_dt_get_clk(struct dt_driver_phandle_args *pargs, 1490 void *data __unused, TEE_Result *res) 1491 { 1492 unsigned long clock_id = pargs->args[0]; 1493 struct clk *clk = NULL; 1494 1495 *res = TEE_ERROR_BAD_PARAMETERS; 1496 1497 if (pargs->args_count != 1) 1498 return NULL; 1499 1500 clk = clock_id_to_clk(clock_id); 1501 if (!clk) 1502 return NULL; 1503 1504 *res = TEE_SUCCESS; 1505 return clk; 1506 } 1507 1508 /* Non-null reference for compat data */ 1509 static const uint8_t non_secure_rcc; 1510 1511 static TEE_Result stm32mp1_clock_provider_probe(const void *fdt, int offs, 1512 const void *compat_data) 1513 { 1514 TEE_Result res = TEE_ERROR_GENERIC; 1515 1516 if (compat_data == &non_secure_rcc) 1517 disable_rcc_tzen(); 1518 else 1519 enable_rcc_tzen(); 1520 1521 res = stm32mp1_clk_fdt_init(fdt, offs); 1522 if (res) { 1523 EMSG("Failed to initialize clocks from DT: %#"PRIx32, res); 1524 panic(); 1525 } 1526 1527 res = register_stm32mp1_clocks(); 1528 if (res) { 1529 EMSG("Failed to register clocks: %#"PRIx32, res); 1530 panic(); 1531 } 1532 1533 res = clk_dt_register_clk_provider(fdt, offs, stm32mp1_clk_dt_get_clk, 1534 NULL); 1535 if (res) { 1536 EMSG("Failed to register clock provider: %#"PRIx32, res); 1537 panic(); 1538 } 1539 1540 enable_static_secure_clocks(); 1541 1542 return TEE_SUCCESS; 1543 } 1544 1545 static const struct dt_device_match stm32mp1_clock_match_table[] = { 1546 { .compatible = "st,stm32mp1-rcc", .compat_data = &non_secure_rcc, }, 1547 { .compatible = "st,stm32mp1-rcc-secure", }, 1548 { } 1549 }; 1550 1551 DEFINE_DT_DRIVER(stm32mp1_clock_dt_driver) = { 1552 .name = "stm32mp1_clock", 1553 .type = DT_DRIVER_CLK, 1554 .match_table = stm32mp1_clock_match_table, 1555 .probe = stm32mp1_clock_provider_probe, 1556 }; 1557 #else /*CFG_DRIVERS_CLK_DT*/ 1558 static TEE_Result stm32mp1_clk_early_init(void) 1559 { 1560 TEE_Result __maybe_unused res = TEE_ERROR_GENERIC; 1561 1562 res = register_stm32mp1_clocks(); 1563 if (res) { 1564 EMSG("Failed to register clocks: %#"PRIx32, res); 1565 panic(); 1566 } 1567 1568 enable_static_secure_clocks(); 1569 1570 return TEE_SUCCESS; 1571 } 1572 1573 service_init(stm32mp1_clk_early_init); 1574 #endif /*CFG_DRIVERS_CLK_DT*/ 1575