| 16b6c0f6 | 12-Apr-2019 |
Sandeep Tripathy <sandeep.tripathy@broadcom.com> |
drivers: bcm_hwrng: add HWRNG driver
low level driver for Broadcom random number generator IP.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Bharat Kumar Reddy Gooty <bharat.g
drivers: bcm_hwrng: add HWRNG driver
low level driver for Broadcom random number generator IP.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
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| c75303f7 | 08-Mar-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
stm32_i2c: handle pinctrl
Get pinctrl support from stm32_gpio.h into STM32 I2C driver. When device tree content defines pins related to an I2C interface, the I2C driver saves the pins configuration
stm32_i2c: handle pinctrl
Get pinctrl support from stm32_gpio.h into STM32 I2C driver. When device tree content defines pins related to an I2C interface, the I2C driver saves the pins configuration instances and set the registered pins in the expected power mode at runtime.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| f3c22059 | 13-Feb-2019 |
Etienne Carriere <etienne.carriere@st.com> |
stm32_rng: driver for STM32 RNG
Drivers is embedded upon CFG_STM32_RNG=y.
The driver main API functions are: - stm32_rng_read() to get a buffer of random bytes, - stm32_rng_read_raw() to get a buff
stm32_rng: driver for STM32 RNG
Drivers is embedded upon CFG_STM32_RNG=y.
The driver main API functions are: - stm32_rng_read() to get a buffer of random bytes, - stm32_rng_read_raw() to get a buffer of random bytes assuming the RNG hardware is ready, i.e clock enabled.
The device driver is initialized from DT resource when a secure DTB, currently the embedded DTB, is found.
STM32 RNG driver assumes the platform supports at most RNG instance in the secure world.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| e7dbc357 | 02-Jul-2018 |
Summer Qin <summer.qin@arm.com> |
core: add encrypt key length in AES encrypt API
Adds size of expanded AES encryption key to crypto_aes_expand_enc_key() and crypto_aes_enc_block() to make the functions more safe to call.
Reviewed-
core: add encrypt key length in AES encrypt API
Adds size of expanded AES encryption key to crypto_aes_expand_enc_key() and crypto_aes_enc_block() to make the functions more safe to call.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Summer Qin <summer.qin@arm.com> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| f1e9b21b | 08-Mar-2019 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: crypto: introduce struct crypto_authenc_ops
Uses struct crypto_authenc_ops pointer in crypto context for authenc ciphers (AES-GCM and AES-CCM) as a glue layer instead of a switch(algo) in each
core: crypto: introduce struct crypto_authenc_ops
Uses struct crypto_authenc_ops pointer in crypto context for authenc ciphers (AES-GCM and AES-CCM) as a glue layer instead of a switch(algo) in each cryto_authenc_*() function.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 96098f01 | 08-Mar-2019 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: crypto: introduce struct crypto_cipher_ops
Uses struct crypto_cipher_ops pointer in crypto context for ciphers as a glue layer instead of a switch(algo) in each crypto_cipher_*() function.
Re
core: crypto: introduce struct crypto_cipher_ops
Uses struct crypto_cipher_ops pointer in crypto context for ciphers as a glue layer instead of a switch(algo) in each crypto_cipher_*() function.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 5da36a24 | 08-Mar-2019 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: crypto: introduce struct crypto_mac_ops
Uses struct crypto_mac_ops pointer in crypto context for MACs as a glue layer instead of a switch(algo) in each crypto_mac_*() function.
Moves CBC-MAC
core: crypto: introduce struct crypto_mac_ops
Uses struct crypto_mac_ops pointer in crypto context for MACs as a glue layer instead of a switch(algo) in each crypto_mac_*() function.
Moves CBC-MAC implementation from LTC wrapper to core/crypto.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 6648f482 | 08-Mar-2019 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: crypto: introduce struct crypto_hash_ops
Uses struct crypto_hash_ops pointer in crypto context for hashes as a glue layer instead of a switch(algo) in each crypto_hash_*() function.
Reviewed-
core: crypto: introduce struct crypto_hash_ops
Uses struct crypto_hash_ops pointer in crypto context for hashes as a glue layer instead of a switch(algo) in each crypto_hash_*() function.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| b844655c | 07-Mar-2019 |
Etienne Carriere <etienne.carriere@st.com> |
stm32_i2c: driver for STM32 I2C bus
Drivers is embedded upon CFG_STM32_I2C=y.
The driver main API functions are: stm32_i2c_init() to initialize the device driver, stm32_i2c_mem_{write|read}() for I
stm32_i2c: driver for STM32 I2C bus
Drivers is embedded upon CFG_STM32_I2C=y.
The driver main API functions are: stm32_i2c_init() to initialize the device driver, stm32_i2c_mem_{write|read}() for I2C memory mode transfer, stm32_i2c_master_{transmit|receive}() for stream transfer.
2 helpers: stm32_i2c_is_device_ready() checks the hardware I2C link, stm32_i2c_get_setup_from_fdt() fills the I2C initialization structure from the content found in the DT.
I2C driver instances do not register themselves to the PM framework. Bus owner is responsible for calling the stm32_i2c_{suspend|resume}() APIs when the owner device executes a PM sequence.
stm32_i2c driver is dual licensed GPL-2.0/BSD-3-Clause. The conversion algorithm for converting device tree bindings timing information into STM32 I2C timings configuration register is shared with other packages (Linux kernel, Arm Trusted Firmware-A, U-Boot).
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
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| 9dde212d | 25-Feb-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: replace TAF with TA invocation in inline comments
TAF stands for Trusted Application Function. It is deprecated since a while. This change replaces the few remaining occurrences with TA invoca
core: replace TAF with TA invocation in inline comments
TAF stands for Trusted Application Function. It is deprecated since a while. This change replaces the few remaining occurrences with TA invocation.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| bb80916b | 25-Feb-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: use PTA as acronym for pseudo TA
Make inline comments and trace messages more consistent by using PTA as acronym for pseudo TA, rather than using pTA, PTA and pta at various places.
Signed-of
core: use PTA as acronym for pseudo TA
Make inline comments and trace messages more consistent by using PTA as acronym for pseudo TA, rather than using pTA, PTA and pta at various places.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 4df764d3 | 25-Feb-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: add inline description of TEE session field user_ctx
Replace inline comment ??? with an appropriate description of the user_ctx field which points the the caller user TA context in case a pseu
core: add inline description of TEE session field user_ctx
Replace inline comment ??? with an appropriate description of the user_ctx field which points the the caller user TA context in case a pseudo TA is invoked from the user TA client.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 99164a05 | 04-Feb-2019 |
Jerome Forissier <jerome.forissier@linaro.org> |
core: do not use virtual addresses as session identifier
Session context virtual address is returned to the REE in entry_open_session(); it is then used back in entry_close_session() and entry_invok
core: do not use virtual addresses as session identifier
Session context virtual address is returned to the REE in entry_open_session(); it is then used back in entry_close_session() and entry_invoke_command(). Sharing virtual addresses with the REE leads to virtual memory addresses disclosure that could be leveraged to defeat ASLR (if/when implemented) and/or mount an attack.
Similarly, syscall_open_ta_session() returns a session ID directly derived from the session virtual address to the caller TA.
This commit introduces a 32-bit identifier field in struct tee_ta_session. The ID is generated when the session is created, starting from the id of the last session in the queue, and counting up until a number that is not used in the session queue is found.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reported-by: Bastien Simondi <bsimondi@netflix.com> [2.1] Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
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| d64485e4 | 25-Feb-2019 |
Etienne Carriere <etienne.carriere@st.com> |
stm32_bsec: OTP driver for stm32mp platforms
BSEC is a one time programmable (OTP) memory interface for stm32mp SoCs. OTPs are grouped into 32bit words identified by a incremental ID starting from 0
stm32_bsec: OTP driver for stm32mp platforms
BSEC is a one time programmable (OTP) memory interface for stm32mp SoCs. OTPs are grouped into 32bit words identified by a incremental ID starting from 0. Shadowed OTPs are loaded in a volatile memory yet used as OTP values by the software.
The platform shall implement stm32mp_get_bsec_static_cfg() to provide BSEC driver some information as the BSEC memory size and its lower/upper threshold ID that split non-secure from secure OTPs.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Christophe Montaud <christophe.montaud@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| ae21bcac | 12-Feb-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: deprecate read32(), write32() and friends
read8(), read16(), read32() write8(), write16() and write32() are deprecated since the equivalent, prefixed with io_ were introduced are aligns functi
core: deprecate read32(), write32() and friends
read8(), read16(), read32() write8(), write16() and write32() are deprecated since the equivalent, prefixed with io_ were introduced are aligns functions API with other memory cell accesses util functions as io_mask32() or pub_be32().
This change fully removes support for the deprecated functions.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| b7d2b849 | 12-Feb-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
libutil: io_clrsetbitsX() firends for 8bit and 16bit accesses
Introduce io_setbits8(), io_clrbits8(), io_clrsetbits8() and io_setbits16(), io_clrbits16(), io_clrsetbits16() for bit clear/set util ov
libutil: io_clrsetbitsX() firends for 8bit and 16bit accesses
Introduce io_setbits8(), io_clrbits8(), io_clrsetbits8() and io_setbits16(), io_clrbits16(), io_clrsetbits16() for bit clear/set util over 8bit and 16bit memory cells on the model of existing io_clrsetbits32() and friends.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 2d0c93df | 12-Feb-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
libutil: replace write*() util functions with io_write*()
write8(), write16() and write32() expect the target written address as 1st argument and the written value as 2nd argument. This is confusing
libutil: replace write*() util functions with io_write*()
write8(), write16() and write32() expect the target written address as 1st argument and the written value as 2nd argument. This is confusing as put_be32(), put_be64(), io_mask32(), and the io_*bits32() functions expect the opposite: 1st argument is the address and 2nd argument is the written value(s).
This change introduces functions io_write8(), io_write16() and io_write32() with io_mask32() like APIs. This change introduces io_read*() for consistency: all prefixed with io_.
This change preserve the write8/write16/write32 functions for compatibility. These will be deprecated in the next OP-TEE release to lower confusion around these.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 4d22155c | 12-Feb-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: change io_{clr|set|clrset}bits32() address argument type
Change API for io_clrbits32(), io_setbits32() and io_clrsetbits32() to have a vaddr_t type address argument, rather than uintptr_t as p
core: change io_{clr|set|clrset}bits32() address argument type
Change API for io_clrbits32(), io_setbits32() and io_clrsetbits32() to have a vaddr_t type address argument, rather than uintptr_t as previously.
This change updates accordingly the callers of these functions that cover only stm32mp1 related resources.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 4b5e93ed | 11-Feb-2019 |
Etienne Carriere <etienne.carriere@st.com> |
stm32_gpio: driver for GPIO and pin control
Driver is embedded upon CFG_STM32_GPIO=y.
STM32 GPIO driver API main functions: - stm32_gpio_set_output_level() sets target output GPIO level, - stm32_gp
stm32_gpio: driver for GPIO and pin control
Driver is embedded upon CFG_STM32_GPIO=y.
STM32 GPIO driver API main functions: - stm32_gpio_set_output_level() sets target output GPIO level, - stm32_gpio_get_input_level() returns target input GPIO level, - stm32_pinctrl_load_active_cfg() loads interface pin mux active state, - stm32_pinctrl_load_standby_cfg() loads interface pin mux standby state, - stm32_pinctrl_fdt_get_pinctrl() save pin configuration from DT content, - stm32_gpio_set_secure_cfg() sets secure state for target GPIO/pin mux.
GPIO driver does not register to PM framework. It is the GPIO/pin owner responsibility to call stm32_pinctrl_load_{active|standby}_cfg() on peripherals power state transitions.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| e4e0a6cc | 08-Feb-2019 |
Etienne Carriere <etienne.carriere@st.com> |
stm32_etzpc: STM32 Extended TrustZone Protection Controller
ETZPC is a hardware instance that control access permissions to some stm32mp SoC peripheral interfaces and internal memories.
This change
stm32_etzpc: STM32 Extended TrustZone Protection Controller
ETZPC is a hardware instance that control access permissions to some stm32mp SoC peripheral interfaces and internal memories.
This change introduce the stm32_etzpc driver. It is embedded upon build directive CFG_STM32_ETZPC=y.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Mathieu BELOU <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| c4e8be26 | 30-May-2018 |
Volodymyr Babchuk <vlad.babchuk@gmail.com> |
virt: add virtualization subsystem
This patch adds virtualization framework to OP-TEE.
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> |
| a386ba2e | 07-Feb-2018 |
Volodymyr Babchuk <vlad.babchuk@gmail.com> |
tee_mm: add TEE_MM_POOL_NEX_MALLOC flag
This flag tells tee_mm to use nex_malloc pool instead of default malloc
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> Reviewed-by: Jens Wiklander
tee_mm: add TEE_MM_POOL_NEX_MALLOC flag
This flag tells tee_mm to use nex_malloc pool instead of default malloc
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| c4f75cc6 | 20-Nov-2018 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: optee_msg.h: define OPTEE_MSG_MAX_NUM_PARAMS
Defines OPTEE_MSG_MAX_NUM_PARAMS to be used with the macro OPTEE_MSG_GET_ARG_SIZE() in order to avoid unexpected wrapping.
Fixes: "Macro for check
core: optee_msg.h: define OPTEE_MSG_MAX_NUM_PARAMS
Defines OPTEE_MSG_MAX_NUM_PARAMS to be used with the macro OPTEE_MSG_GET_ARG_SIZE() in order to avoid unexpected wrapping.
Fixes: "Macro for checking size of parameter buffer can overflow" as reported by Riscure.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Joakim Bech <joakim.bech@linaro.org> (QEMU v7, v8) Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reported-by: Riscure <inforequest@riscure.com> Reported-by: Alyssa Milburn <a.a.milburn@vu.nl> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 87fdf271 | 08-Jan-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
stm32_uart: API to init console bus from a DTB
Introduce stm32_uart_init_from_dt_node() that initializes an UART device from the given DT node. The function returns the reference to the created UART
stm32_uart: API to init console bus from a DTB
Introduce stm32_uart_init_from_dt_node() that initializes an UART device from the given DT node. The function returns the reference to the created UART instance.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Joakim Bech <joakim.bech@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 107d5ec2 | 08-Jan-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
stm32_uart: rename exported structure and add secure flag
Rename structure console_pdata into stm32_uart_pdata as it will be exported over the platform and should not use such a generic naming.
Thi
stm32_uart: rename exported structure and add secure flag
Rename structure console_pdata into stm32_uart_pdata as it will be exported over the platform and should not use such a generic naming.
This change adds a secure flag to the UART device instance for used to get the appropriate virtual address when required. An UART bus could be used by the secure world in secure mode or in non-secure mode. A bus to a secure element likely mandates secure hardening of the UART. A debug console over a non-secure UART link may require the UART resources to be assigned to the non-secure world.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Joakim Bech <joakim.bech@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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