1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32_uart.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <kernel/generic_boot.h> 14 #include <kernel/dt.h> 15 #include <kernel/misc.h> 16 #include <kernel/panic.h> 17 #include <kernel/pm_stubs.h> 18 #include <kernel/spinlock.h> 19 #include <mm/core_memprot.h> 20 #include <platform_config.h> 21 #include <sm/psci.h> 22 #include <stm32_util.h> 23 #include <tee/entry_std.h> 24 #include <tee/entry_fast.h> 25 #include <trace.h> 26 27 #ifdef CFG_WITH_NSEC_UARTS 28 register_phys_mem(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 29 register_phys_mem(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 30 register_phys_mem(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 31 register_phys_mem(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 32 register_phys_mem(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 36 #endif 37 38 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 39 register_phys_mem(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 42 register_phys_mem(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 43 44 static void main_fiq(void); 45 46 static const struct thread_handlers handlers = { 47 .std_smc = tee_entry_std, 48 .fast_smc = tee_entry_fast, 49 .nintr = main_fiq, 50 .cpu_on = pm_panic, 51 .cpu_off = pm_panic, 52 .cpu_suspend = pm_panic, 53 .cpu_resume = pm_panic, 54 .system_off = pm_panic, 55 .system_reset = pm_panic, 56 }; 57 58 const struct thread_handlers *generic_boot_get_handlers(void) 59 { 60 return &handlers; 61 } 62 63 #define _ID2STR(id) (#id) 64 #define ID2STR(id) _ID2STR(id) 65 66 static TEE_Result platform_banner(void) 67 { 68 #ifdef CFG_EMBED_DTB 69 IMSG("Platform stm32mp1: flavor %s - DT %s", 70 ID2STR(PLATFORM_FLAVOR), 71 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 72 #else 73 IMSG("Platform stm32mp1: flavor %s - no device tree", 74 ID2STR(PLATFORM_FLAVOR)); 75 #endif 76 77 return TEE_SUCCESS; 78 } 79 service_init(platform_banner); 80 81 /* 82 * Console 83 * 84 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 85 * trace console. Value 0 disables the early console. 86 * 87 * We cannot use the generic serial_console support since probing 88 * the console requires the platform clock driver to be already 89 * up and ready which is done only once service_init are completed. 90 */ 91 static struct stm32_uart_pdata console_data; 92 93 void console_init(void) 94 { 95 /* Early console initialization before MMU setup */ 96 struct uart { 97 uintptr_t pa; 98 bool secure; 99 } uarts[] = { 100 [0] = { .pa = 0 }, 101 [1] = { .pa = USART1_BASE, .secure = true, }, 102 [2] = { .pa = USART2_BASE, .secure = false, }, 103 [3] = { .pa = USART3_BASE, .secure = false, }, 104 [4] = { .pa = UART4_BASE, .secure = false, }, 105 [5] = { .pa = UART5_BASE, .secure = false, }, 106 [6] = { .pa = USART6_BASE, .secure = false, }, 107 [7] = { .pa = UART7_BASE, .secure = false, }, 108 [8] = { .pa = UART8_BASE, .secure = false, }, 109 }; 110 111 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 112 assert(!cpu_mmu_enabled()); 113 114 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 115 return; 116 117 /* No clock yet bound to the UART console */ 118 console_data.clock = DT_INFO_INVALID_CLOCK; 119 120 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 121 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 122 123 register_serial_console(&console_data.chip); 124 125 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 126 } 127 128 #ifdef CFG_DT 129 static TEE_Result init_console_from_dt(void) 130 { 131 struct stm32_uart_pdata *pd; 132 void *fdt; 133 int node; 134 135 if (get_console_node_from_dt(&fdt, &node, NULL, NULL)) 136 return TEE_SUCCESS; 137 138 pd = stm32_uart_init_from_dt_node(fdt, node); 139 if (!pd) { 140 IMSG("DTB disables console"); 141 register_serial_console(NULL); 142 return TEE_SUCCESS; 143 } 144 145 /* Replace early console with the new one */ 146 console_flush(); 147 console_data = *pd; 148 free(pd); 149 register_serial_console(&console_data.chip); 150 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 151 152 return TEE_SUCCESS; 153 } 154 155 /* Probe console from DT once clock inits (service init level) are completed */ 156 service_init_late(init_console_from_dt); 157 #endif 158 159 /* 160 * GIC init, used also for primary/secondary boot core wake completion 161 */ 162 static struct gic_data gic_data; 163 164 static void main_fiq(void) 165 { 166 gic_it_handle(&gic_data); 167 } 168 169 void main_init_gic(void) 170 { 171 assert(cpu_mmu_enabled()); 172 173 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 174 itr_init(&gic_data.chip); 175 176 stm32mp_register_online_cpu(); 177 } 178 179 void main_secondary_init_gic(void) 180 { 181 gic_cpu_init(&gic_data); 182 183 stm32mp_register_online_cpu(); 184 } 185 186 #ifndef CFG_EMBED_DTB 187 static TEE_Result init_stm32mp1_drivers(void) 188 { 189 /* Without secure DTB support, some drivers must be inited */ 190 stm32_etzpc_init(ETZPC_BASE); 191 192 return TEE_SUCCESS; 193 } 194 driver_init(init_stm32mp1_drivers); 195 #endif /*!CFG_EMBED_DTB*/ 196 197 /* Platform initializations once all drivers are ready */ 198 static TEE_Result init_late_stm32mp1_drivers(void) 199 { 200 /* Secure internal memories for the platform, once ETZPC is ready */ 201 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 202 etzpc_lock_tzma(0); 203 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 204 etzpc_lock_tzma(1); 205 206 /* Static secure DECPROT configuration */ 207 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 208 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 209 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 210 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 211 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 212 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 213 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 214 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 215 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 216 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 217 /* Static non-secure DECPROT configuration */ 218 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 219 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 220 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 221 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 222 /* Release few resource to the non-secure world */ 223 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 224 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 225 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 226 227 return TEE_SUCCESS; 228 } 229 driver_init_late(init_late_stm32mp1_drivers); 230 231 uintptr_t get_gicc_base(void) 232 { 233 uintptr_t pbase = GIC_BASE + GICC_OFFSET; 234 235 if (cpu_mmu_enabled()) 236 return (uintptr_t)phys_to_virt_io(pbase); 237 238 return pbase; 239 } 240 241 uintptr_t get_gicd_base(void) 242 { 243 uintptr_t pbase = GIC_BASE + GICD_OFFSET; 244 245 if (cpu_mmu_enabled()) 246 return (uintptr_t)phys_to_virt_io(pbase); 247 248 return pbase; 249 } 250 251 uint32_t may_spin_lock(unsigned int *lock) 252 { 253 if (!lock || !cpu_mmu_enabled()) 254 return 0; 255 256 return cpu_spin_lock_xsave(lock); 257 } 258 259 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 260 { 261 if (!lock || !cpu_mmu_enabled()) 262 return; 263 264 cpu_spin_unlock_xrestore(lock, exceptions); 265 } 266 267 static uintptr_t stm32_tamp_base(void) 268 { 269 static struct io_pa_va base = { .pa = TAMP_BASE }; 270 271 return io_pa_or_va(&base); 272 } 273 274 static uintptr_t bkpreg_base(void) 275 { 276 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 277 } 278 279 uintptr_t stm32mp_bkpreg(unsigned int idx) 280 { 281 return bkpreg_base() + (idx * sizeof(uint32_t)); 282 } 283