1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_uart.h> 11 #include <kernel/generic_boot.h> 12 #include <kernel/dt.h> 13 #include <kernel/misc.h> 14 #include <kernel/panic.h> 15 #include <kernel/pm_stubs.h> 16 #include <kernel/spinlock.h> 17 #include <mm/core_memprot.h> 18 #include <platform_config.h> 19 #include <sm/psci.h> 20 #include <stm32_util.h> 21 #include <tee/entry_std.h> 22 #include <tee/entry_fast.h> 23 #include <trace.h> 24 25 #ifdef CFG_WITH_NSEC_UARTS 26 register_phys_mem(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 27 register_phys_mem(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 28 register_phys_mem(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 29 register_phys_mem(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 30 register_phys_mem(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 31 register_phys_mem(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 32 register_phys_mem(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 34 #endif 35 36 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 37 register_phys_mem(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 41 42 static void main_fiq(void); 43 44 static const struct thread_handlers handlers = { 45 .std_smc = tee_entry_std, 46 .fast_smc = tee_entry_fast, 47 .nintr = main_fiq, 48 .cpu_on = pm_panic, 49 .cpu_off = pm_panic, 50 .cpu_suspend = pm_panic, 51 .cpu_resume = pm_panic, 52 .system_off = pm_panic, 53 .system_reset = pm_panic, 54 }; 55 56 const struct thread_handlers *generic_boot_get_handlers(void) 57 { 58 return &handlers; 59 } 60 61 #define _ID2STR(id) (#id) 62 #define ID2STR(id) _ID2STR(id) 63 64 static TEE_Result platform_banner(void) 65 { 66 #ifdef CFG_EMBED_DTB 67 IMSG("Platform stm32mp1: flavor %s - DT %s", 68 ID2STR(PLATFORM_FLAVOR), 69 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 70 #else 71 IMSG("Platform stm32mp1: flavor %s - no device tree", 72 ID2STR(PLATFORM_FLAVOR)); 73 #endif 74 75 return TEE_SUCCESS; 76 } 77 service_init(platform_banner); 78 79 /* 80 * Console 81 * 82 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 83 * trace console. Value 0 disables the early console. 84 * 85 * We cannot use the generic serial_console support since probing 86 * the console requires the platform clock driver to be already 87 * up and ready which is done only once service_init are completed. 88 */ 89 static struct stm32_uart_pdata console_data; 90 91 void console_init(void) 92 { 93 /* Early console initialization before MMU setup */ 94 struct uart { 95 uintptr_t pa; 96 bool secure; 97 } uarts[] = { 98 [0] = { .pa = 0 }, 99 [1] = { .pa = USART1_BASE, .secure = true, }, 100 [2] = { .pa = USART2_BASE, .secure = false, }, 101 [3] = { .pa = USART3_BASE, .secure = false, }, 102 [4] = { .pa = UART4_BASE, .secure = false, }, 103 [5] = { .pa = UART5_BASE, .secure = false, }, 104 [6] = { .pa = USART6_BASE, .secure = false, }, 105 [7] = { .pa = UART7_BASE, .secure = false, }, 106 [8] = { .pa = UART8_BASE, .secure = false, }, 107 }; 108 109 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 110 assert(!cpu_mmu_enabled()); 111 112 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 113 return; 114 115 /* No clock yet bound to the UART console */ 116 console_data.clock = DT_INFO_INVALID_CLOCK; 117 118 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 119 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 120 121 register_serial_console(&console_data.chip); 122 123 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 124 } 125 126 #ifdef CFG_DT 127 static TEE_Result init_console_from_dt(void) 128 { 129 struct stm32_uart_pdata *pd; 130 void *fdt; 131 int node; 132 133 if (get_console_node_from_dt(&fdt, &node, NULL, NULL)) 134 return TEE_SUCCESS; 135 136 pd = stm32_uart_init_from_dt_node(fdt, node); 137 if (!pd) { 138 IMSG("DTB disables console"); 139 register_serial_console(NULL); 140 return TEE_SUCCESS; 141 } 142 143 /* Replace early console with the new one */ 144 console_flush(); 145 console_data = *pd; 146 free(pd); 147 register_serial_console(&console_data.chip); 148 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 149 150 return TEE_SUCCESS; 151 } 152 153 /* Probe console from DT once clock inits (service init level) are completed */ 154 service_init_late(init_console_from_dt); 155 #endif 156 157 /* 158 * GIC init, used also for primary/secondary boot core wake completion 159 */ 160 static struct gic_data gic_data; 161 162 static void main_fiq(void) 163 { 164 gic_it_handle(&gic_data); 165 } 166 167 void main_init_gic(void) 168 { 169 assert(cpu_mmu_enabled()); 170 171 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 172 itr_init(&gic_data.chip); 173 174 stm32mp_register_online_cpu(); 175 } 176 177 void main_secondary_init_gic(void) 178 { 179 gic_cpu_init(&gic_data); 180 181 stm32mp_register_online_cpu(); 182 } 183 184 uintptr_t get_gicc_base(void) 185 { 186 uintptr_t pbase = GIC_BASE + GICC_OFFSET; 187 188 if (cpu_mmu_enabled()) 189 return (uintptr_t)phys_to_virt_io(pbase); 190 191 return pbase; 192 } 193 194 uintptr_t get_gicd_base(void) 195 { 196 uintptr_t pbase = GIC_BASE + GICD_OFFSET; 197 198 if (cpu_mmu_enabled()) 199 return (uintptr_t)phys_to_virt_io(pbase); 200 201 return pbase; 202 } 203 204 uint32_t may_spin_lock(unsigned int *lock) 205 { 206 if (!lock || !cpu_mmu_enabled()) 207 return 0; 208 209 return cpu_spin_lock_xsave(lock); 210 } 211 212 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 213 { 214 if (!lock || !cpu_mmu_enabled()) 215 return; 216 217 cpu_spin_unlock_xrestore(lock, exceptions); 218 } 219 220 static uintptr_t stm32_tamp_base(void) 221 { 222 static struct io_pa_va base = { .pa = TAMP_BASE }; 223 224 return io_pa_or_va(&base); 225 } 226 227 static uintptr_t bkpreg_base(void) 228 { 229 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 230 } 231 232 uintptr_t stm32mp_bkpreg(unsigned int idx) 233 { 234 return bkpreg_base() + (idx * sizeof(uint32_t)); 235 } 236