1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_uart.h> 11 #include <kernel/generic_boot.h> 12 #include <kernel/misc.h> 13 #include <kernel/panic.h> 14 #include <kernel/pm_stubs.h> 15 #include <kernel/spinlock.h> 16 #include <mm/core_memprot.h> 17 #include <platform_config.h> 18 #include <sm/psci.h> 19 #include <stm32_util.h> 20 #include <tee/entry_std.h> 21 #include <tee/entry_fast.h> 22 #include <trace.h> 23 24 #ifdef CFG_WITH_NSEC_UARTS 25 register_phys_mem(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 26 register_phys_mem(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 27 register_phys_mem(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 28 register_phys_mem(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 29 register_phys_mem(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 30 register_phys_mem(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 31 register_phys_mem(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 32 register_phys_mem(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 33 #endif 34 35 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 36 register_phys_mem(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 38 39 static void main_fiq(void); 40 41 static const struct thread_handlers handlers = { 42 .std_smc = tee_entry_std, 43 .fast_smc = tee_entry_fast, 44 .nintr = main_fiq, 45 .cpu_on = pm_panic, 46 .cpu_off = pm_panic, 47 .cpu_suspend = pm_panic, 48 .cpu_resume = pm_panic, 49 .system_off = pm_panic, 50 .system_reset = pm_panic, 51 }; 52 53 const struct thread_handlers *generic_boot_get_handlers(void) 54 { 55 return &handlers; 56 } 57 58 #define _ID2STR(id) (#id) 59 #define ID2STR(id) _ID2STR(id) 60 61 static TEE_Result platform_banner(void) 62 { 63 #ifdef CFG_EMBED_DTB 64 IMSG("Platform stm32mp1: flavor %s - DT %s", 65 ID2STR(PLATFORM_FLAVOR), 66 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 67 #else 68 IMSG("Platform stm32mp1: flavor %s - no device tree", 69 ID2STR(PLATFORM_FLAVOR)); 70 #endif 71 72 return TEE_SUCCESS; 73 } 74 service_init(platform_banner); 75 76 /* 77 * Console 78 * 79 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 80 * trace console. Value 0 disables the early console. 81 */ 82 static struct stm32_uart_pdata console_data; 83 84 void console_init(void) 85 { 86 /* Early console initialization before MMU setup */ 87 struct uart { 88 uintptr_t pa; 89 bool secure; 90 } uarts[] = { 91 [0] = { .pa = 0 }, 92 [1] = { .pa = USART1_BASE, .secure = true, }, 93 [2] = { .pa = USART2_BASE, .secure = false, }, 94 [3] = { .pa = USART3_BASE, .secure = false, }, 95 [4] = { .pa = UART4_BASE, .secure = false, }, 96 [5] = { .pa = UART5_BASE, .secure = false, }, 97 [6] = { .pa = USART6_BASE, .secure = false, }, 98 [7] = { .pa = UART7_BASE, .secure = false, }, 99 [8] = { .pa = UART8_BASE, .secure = false, }, 100 }; 101 102 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 103 assert(!cpu_mmu_enabled()); 104 105 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 106 return; 107 108 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 109 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 110 111 register_serial_console(&console_data.chip); 112 113 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 114 } 115 116 /* 117 * GIC init, used also for primary/secondary boot core wake completion 118 */ 119 static struct gic_data gic_data; 120 121 static void main_fiq(void) 122 { 123 gic_it_handle(&gic_data); 124 } 125 126 void main_init_gic(void) 127 { 128 assert(cpu_mmu_enabled()); 129 130 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 131 itr_init(&gic_data.chip); 132 133 stm32mp_register_online_cpu(); 134 } 135 136 void main_secondary_init_gic(void) 137 { 138 gic_cpu_init(&gic_data); 139 140 stm32mp_register_online_cpu(); 141 } 142 143 uintptr_t get_gicc_base(void) 144 { 145 uintptr_t pbase = GIC_BASE + GICC_OFFSET; 146 147 if (cpu_mmu_enabled()) 148 return (uintptr_t)phys_to_virt_io(pbase); 149 150 return pbase; 151 } 152 153 uintptr_t get_gicd_base(void) 154 { 155 uintptr_t pbase = GIC_BASE + GICD_OFFSET; 156 157 if (cpu_mmu_enabled()) 158 return (uintptr_t)phys_to_virt_io(pbase); 159 160 return pbase; 161 } 162 163 uint32_t may_spin_lock(unsigned int *lock) 164 { 165 if (!lock || !cpu_mmu_enabled()) 166 return 0; 167 168 return cpu_spin_lock_xsave(lock); 169 } 170 171 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 172 { 173 if (!lock || !cpu_mmu_enabled()) 174 return; 175 176 cpu_spin_unlock_xrestore(lock, exceptions); 177 } 178 179 static uintptr_t stm32_tamp_base(void) 180 { 181 static struct io_pa_va base = { .pa = TAMP_BASE }; 182 183 return io_pa_or_va(&base); 184 } 185 186 static uintptr_t bkpreg_base(void) 187 { 188 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 189 } 190 191 uintptr_t stm32mp_bkpreg(unsigned int idx) 192 { 193 return bkpreg_base() + (idx * sizeof(uint32_t)); 194 } 195