| 90dee57a | 04-Apr-2022 |
Clément Léger <clement.leger@bootlin.com> |
drivers: clk: sam: export audiopll_fracck and usbck
This allows to modify the clocks rate and parents from the device-tree using assigned-clock-parents/rate properties rather than hardcoding the clo
drivers: clk: sam: export audiopll_fracck and usbck
This allows to modify the clocks rate and parents from the device-tree using assigned-clock-parents/rate properties rather than hardcoding the clocks rate.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 3a5e9803 | 07-Jun-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp1: remove SCMI0 channel index
Removes index 0 from SCMI DT binding ID macros and driver labels to synchronize with Linux kernel 5.18 that considers a single SCMI channel, see [1] and [2]
plat-stm32mp1: remove SCMI0 channel index
Removes index 0 from SCMI DT binding ID macros and driver labels to synchronize with Linux kernel 5.18 that considers a single SCMI channel, see [1] and [2].
Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-4-alexandre.torgue@foss.st.com Link: [2] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-5-alexandre.torgue@foss.st.com Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 5055cc12 | 02-Dec-2019 |
Etienne Carriere <etienne.carriere@st.com> |
dt-bindings: stm32mp1: define SCMI reset domains
Define the platform SCMI reset domains for stm32mp1 family.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Acked-by: Jerome Forissier <je
dt-bindings: stm32mp1: define SCMI reset domains
Define the platform SCMI reset domains for stm32mp1 family.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Acked-by: Jerome Forissier <jerome@forissier.org>
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