1PLATFORM_FLAVOR ?= zcu102 2 3include core/arch/arm/cpu/cortex-armv8-0.mk 4 5$(call force,CFG_TEE_CORE_NB_CORE,4) 6$(call force,CFG_CDNS_UART,y) 7$(call force,CFG_GIC,y) 8$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 9$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 10 11# Disable core ASLR for two reasons: 12# 1. There is no source for ALSR seed, as ATF does not provide a 13# DTB to OP-TEE. Hardware RNG is also not currently supported. 14# 2. OP-TEE does not boot with enabled CFG_CORE_ASLR. 15$(call force,CFG_CORE_ASLR,n) 16 17ifeq ($(CFG_ARM64_core),y) 18# ZynqMP supports up to 40 bits of physical addresses 19CFG_CORE_ARM64_PA_BITS ?= 40 20else 21$(call force,CFG_ARM32_core,y) 22endif 23 24ifneq (,$(filter $(PLATFORM_FLAVOR),zcu102 zc1751_dc1 zc1751_dc2)) 25# ZCU102 features 4 GiB of DDR 26ifeq ($(CFG_ARM64_core),y) 27CFG_DDR_SIZE ?= 0x100000000 28else 29# On 32 bit build limit to 2 GiB of RAM 30CFG_DDR_SIZE ?= 0x80000000 31endif 32endif 33 34ifneq (,$(filter $(PLATFORM_FLAVOR),ultra96)) 35# Ultra96 features 2 GiB of DDR 36CFG_DDR_SIZE ?= 0x80000000 37endif 38 39# By default use DT address as specified by Xilinx 40CFG_DT_ADDR ?= 0x100000 41 42CFG_TZDRAM_START ?= 0x60000000 43CFG_TZDRAM_SIZE ?= 0x10000000 44CFG_SHMEM_START ?= 0x70000000 45CFG_SHMEM_SIZE ?= 0x10000000 46 47CFG_WITH_STATS ?= y 48CFG_CRYPTO_WITH_CE ?= y 49 50CFG_ZYNQMP_PM ?= $(CFG_ARM64_core) 51 52ifeq ($(CFG_RPMB_FS),y) 53$(call force,CFG_ZYNQMP_HUK,y,Mandated by CFG_RPMB_FS) 54endif 55 56ifeq ($(CFG_ZYNQMP_HUK),y) 57$(call force,CFG_ZYNQMP_CSU_AES,y,Mandated by CFG_ZYNQMP_HUK) 58$(call force,CFG_ZYNQMP_CSU_PUF,y,Mandated by CFG_ZYNQMP_HUK) 59endif 60 61ifeq ($(CFG_ZYNQMP_CSU_AES),y) 62$(call force,CFG_ZYNQMP_CSUDMA,y,Mandated by CFG_ZYNQMP_CSU_AES) 63$(call force,CFG_DT,y,Mandated by CFG_ZYNQMP_CSU_AES) 64endif 65 66ifneq (,$(filter y, $(CFG_ZYNQMP_CSU_PUF) $(CFG_ZYNQMP_CSUDMA) $(CFG_ZYNQMP_CSU_AES))) 67$(call force,CFG_ZYNQMP_CSU,y,Mandated by CFG_ZYNQMP_CSU* clients) 68endif 69