1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/stm32_bsec.h> 11 #include <kernel/panic.h> 12 #include <stdint.h> 13 #include <types_ext.h> 14 15 /* Backup registers and RAM utils */ 16 vaddr_t stm32mp_bkpreg(unsigned int idx); 17 18 /* 19 * SYSCFG IO compensation. 20 * These functions assume non-secure world is suspended. 21 */ 22 void stm32mp_syscfg_enable_io_compensation(void); 23 void stm32mp_syscfg_disable_io_compensation(void); 24 25 /* Platform util for the GIC */ 26 vaddr_t get_gicc_base(void); 27 vaddr_t get_gicd_base(void); 28 29 /* 30 * Platform util functions for the GPIO driver 31 * @bank: Target GPIO bank ID as per DT bindings 32 * 33 * Platform shall implement these functions to provide to stm32_gpio 34 * driver the resource reference for a target GPIO bank. That are 35 * memory mapped interface base address, interface offset (see below) 36 * and clock identifier. 37 * 38 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 39 * check DT configuration matches platform implementation of the banks 40 * description. 41 */ 42 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 43 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 44 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 45 46 /* Platform util for PMIC support */ 47 bool stm32mp_with_pmic(void); 48 49 /* Power management service */ 50 #ifdef CFG_PSCI_ARM32 51 void stm32mp_register_online_cpu(void); 52 #else 53 static inline void stm32mp_register_online_cpu(void) 54 { 55 } 56 #endif 57 58 /* 59 * Generic spinlock function that bypass spinlock if MMU is disabled or 60 * lock is NULL. 61 */ 62 uint32_t may_spin_lock(unsigned int *lock); 63 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 64 65 /* 66 * Util for clock gating and to get clock rate for stm32 and platform drivers 67 * @id: Target clock ID, ID used in clock DT bindings 68 */ 69 void stm32_clock_enable(unsigned long id); 70 void stm32_clock_disable(unsigned long id); 71 unsigned long stm32_clock_get_rate(unsigned long id); 72 bool stm32_clock_is_enabled(unsigned long id); 73 74 /* Return true if @clock_id is shared by secure and non-secure worlds */ 75 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 76 77 /* 78 * Util for reset signal assertion/desassertion for stm32 and platform drivers 79 * @id: Target peripheral ID, ID used in reset DT bindings 80 * @to_us: Timeout out in microsecond, or 0 if not waiting signal state 81 */ 82 TEE_Result stm32_reset_assert(unsigned int id, unsigned int timeout_us); 83 TEE_Result stm32_reset_deassert(unsigned int id, unsigned int timeout_us); 84 85 /* Specific reset to manage the MCU hold boot */ 86 void stm32_reset_assert_deassert_mcu(bool assert_not_deassert); 87 88 static inline void stm32_reset_set(unsigned int id) 89 { 90 (void)stm32_reset_assert(id, 0); 91 } 92 93 static inline void stm32_reset_release(unsigned int id) 94 { 95 (void)stm32_reset_deassert(id, 0); 96 } 97 98 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 99 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 100 101 /* 102 * Structure and API function for BSEC driver to get some platform data. 103 * 104 * @base: BSEC interface registers physical base address 105 * @upper_start: Base ID for the BSEC upper words in the platform 106 * @max_id: Max value for BSEC word ID for the platform 107 */ 108 struct stm32_bsec_static_cfg { 109 paddr_t base; 110 unsigned int upper_start; 111 unsigned int max_id; 112 }; 113 114 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 115 116 /* 117 * Return true if platform is in closed_device mode 118 */ 119 bool stm32mp_is_closed_device(void); 120 121 /* 122 * Shared registers support: common lock for accessing SoC registers 123 * shared between several drivers. 124 */ 125 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 126 127 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 128 { 129 io_mask32_stm32shregs(va, value, value); 130 } 131 132 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 133 { 134 io_mask32_stm32shregs(va, 0, value); 135 } 136 137 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 138 139 /* 140 * Shared reference counter: increments by 2 on secure increment 141 * request, decrements by 2 on secure decrement request. Bit #0 142 * is set to 1 on non-secure increment request and reset to 0 on 143 * non-secure decrement request. These counters initialize to 144 * either 0, 1 or 2 upon their expect default state. 145 * Counters saturate to UINT_MAX / 2. 146 */ 147 #define SHREFCNT_NONSECURE_FLAG 0x1ul 148 #define SHREFCNT_SECURE_STEP 0x2ul 149 #define SHREFCNT_MAX (UINT_MAX / 2) 150 151 /* Return 1 if refcnt increments from 0, else return 0 */ 152 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 153 { 154 int rc = !*refcnt; 155 156 if (secure) { 157 if (*refcnt < SHREFCNT_MAX) { 158 *refcnt += SHREFCNT_SECURE_STEP; 159 assert(*refcnt < SHREFCNT_MAX); 160 } 161 } else { 162 *refcnt |= SHREFCNT_NONSECURE_FLAG; 163 } 164 165 return rc; 166 } 167 168 /* Return 1 if refcnt decrements to 0, else return 0 */ 169 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 170 { 171 int rc = 0; 172 173 if (secure) { 174 if (*refcnt < SHREFCNT_MAX) { 175 if (*refcnt < SHREFCNT_SECURE_STEP) 176 panic(); 177 178 *refcnt -= SHREFCNT_SECURE_STEP; 179 rc = !*refcnt; 180 } 181 } else { 182 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 183 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 184 } 185 186 return rc; 187 } 188 189 static inline int incr_refcnt(unsigned int *refcnt) 190 { 191 return incr_shrefcnt(refcnt, true); 192 } 193 194 static inline int decr_refcnt(unsigned int *refcnt) 195 { 196 return decr_shrefcnt(refcnt, true); 197 } 198 199 /* 200 * Shared peripherals and resources registration 201 * 202 * Resources listed in enum stm32mp_shres assigned at run-time to the 203 * non-secure world, to the secure world or shared by both worlds. 204 * In the later case, there must exist a secure service in OP-TEE 205 * for the non-secure world to access the resource. 206 * 207 * Resources may be a peripheral, a bus, a clock or a memory. 208 * 209 * Shared resources driver API functions allows drivers to register the 210 * resource as secure, non-secure or shared and to get the resource 211 * assignation state. 212 */ 213 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 214 215 enum stm32mp_shres { 216 STM32MP1_SHRES_GPIOZ_0 = 0, 217 STM32MP1_SHRES_GPIOZ_1, 218 STM32MP1_SHRES_GPIOZ_2, 219 STM32MP1_SHRES_GPIOZ_3, 220 STM32MP1_SHRES_GPIOZ_4, 221 STM32MP1_SHRES_GPIOZ_5, 222 STM32MP1_SHRES_GPIOZ_6, 223 STM32MP1_SHRES_GPIOZ_7, 224 STM32MP1_SHRES_IWDG1, 225 STM32MP1_SHRES_USART1, 226 STM32MP1_SHRES_SPI6, 227 STM32MP1_SHRES_I2C4, 228 STM32MP1_SHRES_RNG1, 229 STM32MP1_SHRES_HASH1, 230 STM32MP1_SHRES_CRYP1, 231 STM32MP1_SHRES_I2C6, 232 STM32MP1_SHRES_RTC, 233 STM32MP1_SHRES_MCU, 234 STM32MP1_SHRES_PLL3, 235 STM32MP1_SHRES_MDMA, 236 237 STM32MP1_SHRES_COUNT 238 }; 239 240 /* Register resource @id as a secure peripheral */ 241 void stm32mp_register_secure_periph(enum stm32mp_shres id); 242 243 /* Register resource @id as a non-secure peripheral */ 244 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 245 246 /* 247 * Register resource identified by @base as a secure peripheral 248 * @base: IOMEM physical base address of the resource 249 */ 250 void stm32mp_register_secure_periph_iomem(vaddr_t base); 251 252 /* 253 * Register resource identified by @base as a non-secure peripheral 254 * @base: IOMEM physical base address of the resource 255 */ 256 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 257 258 /* 259 * Register GPIO resource as a secure peripheral 260 * @bank: Bank of the target GPIO 261 * @pin: Bit position of the target GPIO in the bank 262 */ 263 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 264 265 /* 266 * Register GPIO resource as a non-secure peripheral 267 * @bank: Bank of the target GPIO 268 * @pin: Bit position of the target GPIO in the bank 269 */ 270 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 271 272 /* Return true if and only if resource @id is registered as secure */ 273 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 274 275 /* Return true if and only if GPIO bank @bank is registered as secure */ 276 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 277 278 /* Return true if and only if GPIO bank @bank is registered as shared */ 279 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 280 281 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 282 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 283 284 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 285 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 286 287 #endif /*__STM32_UTIL_H__*/ 288