1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2013, ARM Ltd 4 * Copyright (c) 2014, Allwinner Technology Co., Ltd. 5 * Copyright (c) 2018, Linaro Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <console.h> 32 #include <io.h> 33 #include <stdint.h> 34 #include <kernel/generic_boot.h> 35 #include <kernel/misc.h> 36 #include <kernel/panic.h> 37 #include <kernel/pm_stubs.h> 38 #include <kernel/delay.h> 39 #include <mm/core_mmu.h> 40 #include <mm/core_memprot.h> 41 #include <mm/tee_pager.h> 42 #include <platform_config.h> 43 #include <sm/tee_mon.h> 44 #include <sm/optee_smc.h> 45 #include <sm/psci.h> 46 #include <arm32.h> 47 48 #define REG_CPUCFG_RES0 (0x0000) 49 #define REG_CPUCFG_CPU_RST(cpu) (0x0040 + (cpu) * (0x0040)) 50 #define REG_CPUCFG_GEN_CTRL (0x0184) 51 #define REG_CPUCFG_PRIV0 (0x01a4) 52 #define REG_CPUCFG_DBG_CTRL1 (0x01e4) 53 #define REG_PRCM_CPU_PWROFF (0x0100) 54 #define REG_PRCM_CPU_PWR_CLAMP(cpu) (0x0140 + (cpu) * (0x0004)) 55 56 int psci_features(uint32_t psci_fid) 57 { 58 switch (psci_fid) { 59 #ifdef CFG_BOOT_SECONDARY_REQUEST 60 case PSCI_CPU_ON: 61 return 0; 62 #endif 63 64 default: 65 return PSCI_RET_NOT_SUPPORTED; 66 } 67 } 68 69 #ifdef CFG_BOOT_SECONDARY_REQUEST 70 int psci_cpu_on(uint32_t core_idx, uint32_t entry, 71 uint32_t context_id) 72 { 73 vaddr_t base = (vaddr_t)phys_to_virt(SUNXI_PRCM_BASE, MEM_AREA_IO_SEC); 74 vaddr_t cpucfg = (vaddr_t)phys_to_virt(SUNXI_CPUCFG_BASE, 75 MEM_AREA_IO_SEC); 76 uint32_t tmpff; 77 uint32_t val; 78 79 assert(base); 80 assert(cpucfg); 81 82 if ((core_idx == 0) || (core_idx >= CFG_TEE_CORE_NB_CORE)) 83 return PSCI_RET_INVALID_PARAMETERS; 84 85 /* set secondary cores' NS entry addresses */ 86 generic_boot_set_core_ns_entry(core_idx, entry, context_id); 87 88 val = virt_to_phys((void *)TEE_TEXT_VA_START); 89 90 /* set entry address */ 91 DMSG("set entry address for CPU %d", core_idx); 92 write32(val, cpucfg + REG_CPUCFG_PRIV0); 93 94 /* assert reset on target CPU */ 95 DMSG("assert reset on target CPU %d", core_idx); 96 write32(0, cpucfg + REG_CPUCFG_CPU_RST(core_idx)); 97 98 /* invalidate L1 cache */ 99 DMSG("invalidate L1 cache for CPU %d", core_idx); 100 write32(read32(cpucfg + REG_CPUCFG_GEN_CTRL) & (~(BIT32(core_idx))), 101 cpucfg + REG_CPUCFG_GEN_CTRL); 102 103 /* lock CPU (Disable external debug access) */ 104 DMSG("lock CPU %d", core_idx); 105 write32(read32(cpucfg + REG_CPUCFG_DBG_CTRL1) & (~(BIT32(core_idx))), 106 cpucfg + REG_CPUCFG_DBG_CTRL1); 107 108 /* release clamp */ 109 DMSG("release clamp for CPU %d", core_idx); 110 tmpff = 0x1ff; 111 do { 112 tmpff >>= 1; 113 write32(tmpff, base + REG_PRCM_CPU_PWR_CLAMP(core_idx)); 114 } while (tmpff); 115 mdelay(10); 116 117 /* clear power gating */ 118 DMSG("clear power gating for CPU %d", core_idx); 119 write32(read32(base + REG_PRCM_CPU_PWROFF) & (~(BIT32(core_idx))), 120 base + REG_PRCM_CPU_PWROFF); 121 udelay(1000); 122 123 /* de-assert reset on target CPU */ 124 DMSG("de-assert reset on target CPU %d", core_idx); 125 write32(0x03, cpucfg + REG_CPUCFG_CPU_RST(core_idx)); 126 127 /* unlock CPU (enable external debug access) */ 128 DMSG("unlock CPU %d", core_idx); 129 write32(read32(cpucfg + REG_CPUCFG_DBG_CTRL1) | (BIT32(core_idx)), 130 cpucfg + REG_CPUCFG_DBG_CTRL1); 131 132 return PSCI_RET_SUCCESS; 133 } 134 135 int psci_cpu_off(void) 136 { 137 uint32_t core_id; 138 vaddr_t base = (vaddr_t)phys_to_virt(SUNXI_PRCM_BASE, MEM_AREA_IO_SEC); 139 vaddr_t cpucfg = (vaddr_t)phys_to_virt(SUNXI_CPUCFG_BASE, 140 MEM_AREA_IO_SEC); 141 142 core_id = get_core_pos(); 143 144 DMSG("core_id: %" PRIu32, core_id); 145 146 #ifdef CFG_PSCI_ARM32 147 psci_armv7_cpu_off(); 148 #endif /* CFG_PSCI_ARM32 */ 149 150 assert(base); 151 assert(cpucfg); 152 153 /* set power gating */ 154 DMSG("set power gating for cpu %d", core_id); 155 write32(read32(base + REG_PRCM_CPU_PWROFF) | (BIT32(core_id)), 156 base + REG_PRCM_CPU_PWROFF); 157 158 /* Activate power clamp */ 159 DMSG("Activate power clamp for cpu %d", core_id); 160 write32(0xff, base + REG_PRCM_CPU_PWR_CLAMP(core_id)); 161 162 while (true) 163 wfi(); 164 165 return PSCI_RET_INTERNAL_FAILURE; 166 } 167 #endif 168