1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/rstctrl.h> 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <drivers/stm32mp1_pmic.h> 14 #include <drivers/stm32mp1_pwr.h> 15 #include <drivers/stpmic1.h> 16 #include <drivers/stpmic1_regulator.h> 17 #include <dt-bindings/clock/stm32mp1-clks.h> 18 #include <dt-bindings/regulator/st,stm32mp15-regulator.h> 19 #include <dt-bindings/reset/stm32mp1-resets.h> 20 #include <initcall.h> 21 #include <mm/core_memprot.h> 22 #include <mm/core_mmu.h> 23 #include <platform_config.h> 24 #include <stdint.h> 25 #include <speculation_barrier.h> 26 #include <stm32_util.h> 27 #include <string.h> 28 #include <tee_api_defines.h> 29 #include <util.h> 30 31 #define TIMEOUT_US_1MS 1000 32 33 #define SCMI_CLOCK_NAME_SIZE 16 34 #define SCMI_RD_NAME_SIZE 16 35 #define SCMI_VOLTD_NAME_SIZE 16 36 37 /* 38 * struct stm32_scmi_clk - Data for the exposed clock 39 * @clock_id: Clock identifier in RCC clock driver 40 * @name: Clock string ID exposed to channel 41 * @enabled: State of the SCMI clock 42 */ 43 struct stm32_scmi_clk { 44 unsigned long clock_id; 45 struct clk *clk; 46 const char *name; 47 bool enabled; 48 }; 49 50 /* 51 * struct stm32_scmi_rd - Data for the exposed reset controller 52 * @reset_id: Reset identifier in RCC reset driver 53 * @name: Reset string ID exposed to channel 54 * @rstctrl: Reset controller device 55 */ 56 struct stm32_scmi_rd { 57 unsigned long reset_id; 58 const char *name; 59 struct rstctrl *rstctrl; 60 }; 61 62 enum voltd_device { 63 VOLTD_PWR, 64 VOLTD_PMIC, 65 }; 66 67 /* 68 * struct stm32_scmi_voltd - Data for the exposed voltage domains 69 * @name: Power regulator string ID exposed to channel 70 * @priv_id: Internal string ID for the regulator 71 * @priv_dev: Internal ID for the device implementing the regulator 72 */ 73 struct stm32_scmi_voltd { 74 const char *name; 75 const char *priv_id; 76 enum voltd_device priv_dev; 77 78 }; 79 80 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 81 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 82 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 83 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 84 85 #if (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE > \ 86 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 87 #error "SCMI shared memory mismatch" 88 #endif 89 90 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 91 CFG_STM32MP1_SCMI_SHM_SIZE); 92 93 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 94 [_scmi_id] = { \ 95 .clock_id = _id, \ 96 .name = _name, \ 97 .enabled = _init_enabled, \ 98 } 99 100 static struct stm32_scmi_clk stm32_scmi0_clock[] = { 101 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 102 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 103 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 104 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 105 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 106 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 107 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 108 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 109 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 110 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 111 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 112 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 113 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 114 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 115 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 116 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 117 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 118 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 119 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 120 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 121 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 122 }; 123 124 static struct stm32_scmi_clk stm32_scmi1_clock[] = { 125 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 126 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 127 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 128 }; 129 130 #define RESET_CELL(_scmi_id, _id, _name) \ 131 [_scmi_id] = { \ 132 .reset_id = _id, \ 133 .name = _name, \ 134 } 135 136 static struct stm32_scmi_rd stm32_scmi0_reset_domain[] = { 137 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 138 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 139 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 140 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 141 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 142 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 143 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 144 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 145 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 146 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 147 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 148 RESET_CELL(RST_SCMI0_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 149 }; 150 151 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 152 [_scmi_id] = { \ 153 .priv_id = (_priv_id), \ 154 .priv_dev = (_dev_id), \ 155 .name = (_name), \ 156 } 157 158 #define PWR_REG11_NAME_ID "0" 159 #define PWR_REG18_NAME_ID "1" 160 #define PWR_USB33_NAME_ID "2" 161 162 struct stm32_scmi_voltd scmi0_voltage_domain[] = { 163 VOLTD_CELL(VOLTD_SCMI0_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 164 VOLTD_CELL(VOLTD_SCMI0_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 165 VOLTD_CELL(VOLTD_SCMI0_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 166 }; 167 168 struct channel_resources { 169 struct scmi_msg_channel *channel; 170 struct stm32_scmi_clk *clock; 171 size_t clock_count; 172 struct stm32_scmi_rd *rd; 173 size_t rd_count; 174 struct stm32_scmi_voltd *voltd; 175 size_t voltd_count; 176 }; 177 178 static const struct channel_resources scmi_channel[] = { 179 [0] = { 180 .channel = &(struct scmi_msg_channel){ 181 .shm_addr = { .pa = SMT_BUFFER0_BASE }, 182 .shm_size = SMT_BUF_SLOT_SIZE, 183 }, 184 .clock = stm32_scmi0_clock, 185 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 186 .rd = stm32_scmi0_reset_domain, 187 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 188 .voltd = scmi0_voltage_domain, 189 .voltd_count = ARRAY_SIZE(scmi0_voltage_domain), 190 }, 191 [1] = { 192 .channel = &(struct scmi_msg_channel){ 193 .shm_addr = { .pa = SMT_BUFFER1_BASE }, 194 .shm_size = SMT_BUF_SLOT_SIZE, 195 }, 196 .clock = stm32_scmi1_clock, 197 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 198 }, 199 }; 200 201 static const struct channel_resources *find_resource(unsigned int channel_id) 202 { 203 assert(channel_id < ARRAY_SIZE(scmi_channel)); 204 205 return scmi_channel + channel_id; 206 } 207 208 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 209 { 210 const size_t max_id = ARRAY_SIZE(scmi_channel); 211 unsigned int confined_id = confine_array_index(channel_id, max_id); 212 213 if (channel_id >= max_id) 214 return NULL; 215 216 return find_resource(confined_id)->channel; 217 } 218 219 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 220 { 221 unsigned int n = 0; 222 unsigned int count = 0; 223 const size_t channel_count = ARRAY_SIZE(scmi_channel); 224 225 for (n = 0; n < channel_count; n++) 226 if (scmi_channel[n].clock_count) 227 break; 228 if (n < channel_count) 229 count++; 230 231 for (n = 0; n < channel_count; n++) 232 if (scmi_channel[n].rd_count) 233 break; 234 if (n < channel_count) 235 count++; 236 237 for (n = 0; n < channel_count; n++) 238 if (scmi_channel[n].voltd_count) 239 break; 240 if (n < channel_count) 241 count++; 242 243 return count; 244 } 245 246 static const char vendor[] = "ST"; 247 static const char sub_vendor[] = ""; 248 249 const char *plat_scmi_vendor_name(void) 250 { 251 return vendor; 252 } 253 254 const char *plat_scmi_sub_vendor_name(void) 255 { 256 return sub_vendor; 257 } 258 259 /* Currently supporting Clocks and Reset Domains */ 260 static const uint8_t plat_protocol_list[] = { 261 SCMI_PROTOCOL_ID_CLOCK, 262 SCMI_PROTOCOL_ID_RESET_DOMAIN, 263 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 264 0 /* Null termination */ 265 }; 266 267 size_t plat_scmi_protocol_count(void) 268 { 269 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 270 271 assert(count == plat_scmi_protocol_count_paranoid()); 272 273 return count; 274 } 275 276 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 277 { 278 assert(plat_scmi_protocol_count_paranoid() == 279 (ARRAY_SIZE(plat_protocol_list) - 1)); 280 281 return plat_protocol_list; 282 } 283 284 /* 285 * Platform SCMI clocks 286 */ 287 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 288 unsigned int scmi_id) 289 { 290 const struct channel_resources *resource = find_resource(channel_id); 291 size_t n = 0; 292 293 if (resource) { 294 for (n = 0; n < resource->clock_count; n++) 295 if (n == scmi_id) 296 return &resource->clock[n]; 297 } 298 299 return NULL; 300 } 301 302 size_t plat_scmi_clock_count(unsigned int channel_id) 303 { 304 const struct channel_resources *resource = find_resource(channel_id); 305 306 if (!resource) 307 return 0; 308 309 return resource->clock_count; 310 } 311 312 const char *plat_scmi_clock_get_name(unsigned int channel_id, 313 unsigned int scmi_id) 314 { 315 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 316 317 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 318 return NULL; 319 320 return clock->name; 321 } 322 323 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 324 unsigned int scmi_id, size_t start_index, 325 unsigned long *array, size_t *nb_elts) 326 { 327 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 328 329 if (!clock) 330 return SCMI_NOT_FOUND; 331 332 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 333 return SCMI_DENIED; 334 335 /* Exposed clocks are currently fixed rate clocks */ 336 if (start_index) 337 return SCMI_INVALID_PARAMETERS; 338 339 if (!array) 340 *nb_elts = 1; 341 else if (*nb_elts == 1) 342 *array = clk_get_rate(clock->clk); 343 else 344 return SCMI_GENERIC_ERROR; 345 346 return SCMI_SUCCESS; 347 } 348 349 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 350 unsigned int scmi_id) 351 { 352 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 353 354 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 355 return 0; 356 357 return clk_get_rate(clock->clk); 358 } 359 360 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 361 { 362 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 363 364 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 365 return 0; 366 367 return (int32_t)clock->enabled; 368 } 369 370 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 371 bool enable_not_disable) 372 { 373 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 374 375 if (!clock) 376 return SCMI_NOT_FOUND; 377 378 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 379 return SCMI_DENIED; 380 381 if (enable_not_disable) { 382 if (!clock->enabled) { 383 DMSG("SCMI clock %u enable", scmi_id); 384 clk_enable(clock->clk); 385 clock->enabled = true; 386 } 387 } else { 388 if (clock->enabled) { 389 DMSG("SCMI clock %u disable", scmi_id); 390 clk_disable(clock->clk); 391 clock->enabled = false; 392 } 393 } 394 395 return SCMI_SUCCESS; 396 } 397 398 /* 399 * Platform SCMI reset domains 400 */ 401 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 402 unsigned int scmi_id) 403 { 404 const struct channel_resources *resource = find_resource(channel_id); 405 size_t n = 0; 406 407 if (resource) { 408 for (n = 0; n < resource->rd_count; n++) 409 if (n == scmi_id) 410 return &resource->rd[n]; 411 } 412 413 return NULL; 414 } 415 416 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 417 { 418 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 419 420 if (!rd) 421 return NULL; 422 423 return rd->name; 424 } 425 426 size_t plat_scmi_rd_count(unsigned int channel_id) 427 { 428 const struct channel_resources *resource = find_resource(channel_id); 429 430 if (!resource) 431 return 0; 432 433 return resource->rd_count; 434 } 435 436 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 437 uint32_t state) 438 { 439 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 440 441 if (!rd) 442 return SCMI_NOT_FOUND; 443 444 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 445 return SCMI_DENIED; 446 assert(rd->rstctrl); 447 448 if (rd->reset_id == MCU_HOLD_BOOT_R) 449 return SCMI_NOT_SUPPORTED; 450 451 /* Supports only reset with context loss */ 452 if (state) 453 return SCMI_NOT_SUPPORTED; 454 455 DMSG("SCMI reset %u cycle", scmi_id); 456 457 if (rstctrl_assert_to(rd->rstctrl, TIMEOUT_US_1MS)) 458 return SCMI_HARDWARE_ERROR; 459 460 if (rstctrl_deassert_to(rd->rstctrl, TIMEOUT_US_1MS)) 461 return SCMI_HARDWARE_ERROR; 462 463 return SCMI_SUCCESS; 464 } 465 466 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 467 bool assert_not_deassert) 468 { 469 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 470 TEE_Result res = TEE_ERROR_GENERIC; 471 472 if (!rd) 473 return SCMI_NOT_FOUND; 474 475 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 476 return SCMI_DENIED; 477 assert(rd->rstctrl); 478 479 if (assert_not_deassert) { 480 DMSG("SCMI reset %u set", scmi_id); 481 res = rstctrl_assert(rd->rstctrl); 482 } else { 483 DMSG("SCMI reset %u release", scmi_id); 484 res = rstctrl_deassert(rd->rstctrl); 485 } 486 487 if (res) 488 return SCMI_HARDWARE_ERROR; 489 490 return SCMI_SUCCESS; 491 } 492 493 /* 494 * Platform SCMI voltage domains 495 */ 496 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 497 unsigned int scmi_id) 498 { 499 const struct channel_resources *resource = find_resource(channel_id); 500 size_t n = 0; 501 502 if (resource) { 503 for (n = 0; n < resource->voltd_count; n++) 504 if (n == scmi_id) 505 return &resource->voltd[n]; 506 } 507 508 return NULL; 509 } 510 511 size_t plat_scmi_voltd_count(unsigned int channel_id) 512 { 513 const struct channel_resources *resource = find_resource(channel_id); 514 515 if (!resource) 516 return 0; 517 518 return resource->voltd_count; 519 } 520 521 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 522 unsigned int scmi_id) 523 { 524 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 525 526 /* Currently non-secure is allowed to access all PWR regulators */ 527 if (!voltd) 528 return NULL; 529 530 return voltd->name; 531 } 532 533 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 534 { 535 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 536 return PWR_REG11; 537 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 538 return PWR_REG18; 539 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 540 return PWR_USB33; 541 542 panic(); 543 } 544 545 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 546 { 547 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 548 549 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 550 } 551 552 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 553 { 554 if (level_uv != pwr_get_level(voltd)) 555 return SCMI_INVALID_PARAMETERS; 556 557 return SCMI_SUCCESS; 558 } 559 560 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 561 size_t start_index, long *microvolt, 562 size_t *nb_elts) 563 { 564 if (start_index) 565 return SCMI_INVALID_PARAMETERS; 566 567 if (!microvolt) { 568 *nb_elts = 1; 569 return SCMI_SUCCESS; 570 } 571 572 if (*nb_elts < 1) 573 return SCMI_GENERIC_ERROR; 574 575 *nb_elts = 1; 576 *microvolt = pwr_get_level(voltd); 577 578 return SCMI_SUCCESS; 579 } 580 581 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 582 { 583 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 584 585 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 586 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 587 588 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 589 } 590 591 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 592 { 593 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 594 595 DMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 596 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 597 598 stm32mp1_pwr_regulator_set_state(regu_id, enable); 599 } 600 601 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 602 size_t start_index, long *microvolt, 603 size_t *nb_elts) 604 { 605 const uint16_t *levels = NULL; 606 size_t full_count = 0; 607 size_t out_count = 0; 608 size_t i = 0; 609 610 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 611 return SCMI_DENIED; 612 613 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 614 615 if (!microvolt) { 616 *nb_elts = full_count - start_index; 617 return SCMI_SUCCESS; 618 } 619 620 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 621 return SCMI_GENERIC_ERROR; 622 623 out_count = MIN(out_count, *nb_elts); 624 625 FMSG("%zu levels: start %zu requested %zu output %zu", 626 full_count, start_index, *nb_elts, out_count); 627 628 for (i = 0; i < out_count; i++) 629 microvolt[i] = levels[start_index + i] * 1000; 630 631 *nb_elts = out_count; 632 633 return SCMI_SUCCESS; 634 } 635 636 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 637 { 638 unsigned long level_mv = 0; 639 640 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 641 return 0; 642 643 stm32mp_get_pmic(); 644 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 645 stm32mp_put_pmic(); 646 647 return (long)level_mv * 1000; 648 } 649 650 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 651 { 652 int rc = 0; 653 unsigned int level_mv = 0; 654 655 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 656 return SCMI_DENIED; 657 658 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 659 return SCMI_INVALID_PARAMETERS; 660 661 level_mv = (unsigned int)level_uv / 1000; 662 663 DMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 664 665 stm32mp_get_pmic(); 666 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 667 stm32mp_put_pmic(); 668 669 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 670 } 671 672 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 673 { 674 bool enabled = false; 675 676 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 677 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 678 679 stm32mp_get_pmic(); 680 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 681 stm32mp_put_pmic(); 682 683 if (enabled) 684 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 685 686 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 687 } 688 689 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 690 { 691 int rc = 0; 692 693 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 694 return SCMI_DENIED; 695 696 stm32mp_get_pmic(); 697 698 DMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 699 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 700 701 if (enable) 702 rc = stpmic1_regulator_enable(voltd->priv_id); 703 else 704 rc = stpmic1_regulator_disable(voltd->priv_id); 705 706 stm32mp_put_pmic(); 707 708 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 709 } 710 711 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 712 unsigned int scmi_id, size_t start_index, 713 long *levels, size_t *nb_elts) 714 715 { 716 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 717 718 if (!voltd) 719 return SCMI_NOT_FOUND; 720 721 switch (voltd->priv_dev) { 722 case VOLTD_PWR: 723 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 724 case VOLTD_PMIC: 725 return pmic_describe_levels(voltd, start_index, levels, 726 nb_elts); 727 default: 728 return SCMI_GENERIC_ERROR; 729 } 730 } 731 732 long plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id) 733 { 734 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 735 736 if (!voltd) 737 return 0; 738 739 switch (voltd->priv_dev) { 740 case VOLTD_PWR: 741 return pwr_get_level(voltd); 742 case VOLTD_PMIC: 743 return pmic_get_level(voltd); 744 default: 745 panic(); 746 } 747 } 748 749 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 750 long level) 751 { 752 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 753 754 if (!voltd) 755 return SCMI_NOT_FOUND; 756 757 switch (voltd->priv_dev) { 758 case VOLTD_PWR: 759 return pwr_set_level(voltd, level); 760 case VOLTD_PMIC: 761 return pmic_set_level(voltd, level); 762 default: 763 return SCMI_GENERIC_ERROR; 764 } 765 } 766 767 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 768 unsigned int scmi_id, uint32_t *config) 769 { 770 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 771 772 if (!voltd) 773 return SCMI_NOT_FOUND; 774 775 switch (voltd->priv_dev) { 776 case VOLTD_PWR: 777 *config = pwr_get_state(voltd); 778 break; 779 case VOLTD_PMIC: 780 *config = pmic_get_state(voltd); 781 break; 782 default: 783 return SCMI_GENERIC_ERROR; 784 } 785 786 return SCMI_SUCCESS; 787 } 788 789 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 790 unsigned int scmi_id, uint32_t config) 791 { 792 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 793 int32_t rc = SCMI_SUCCESS; 794 795 if (!voltd) 796 return SCMI_NOT_FOUND; 797 798 switch (voltd->priv_dev) { 799 case VOLTD_PWR: 800 pwr_set_state(voltd, config); 801 break; 802 case VOLTD_PMIC: 803 rc = pmic_set_state(voltd, config); 804 break; 805 default: 806 return SCMI_GENERIC_ERROR; 807 } 808 809 return rc; 810 } 811 812 /* 813 * Initialize platform SCMI resources 814 */ 815 static TEE_Result stm32mp1_init_scmi_server(void) 816 { 817 size_t i = 0; 818 size_t j = 0; 819 820 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 821 const struct channel_resources *res = scmi_channel + i; 822 struct scmi_msg_channel *chan = res->channel; 823 824 /* Enforce non-secure shm mapped as device memory */ 825 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 826 MEM_AREA_IO_NSEC, 1); 827 assert(chan->shm_addr.va); 828 829 scmi_smt_init_agent_channel(chan); 830 831 for (j = 0; j < res->clock_count; j++) { 832 struct stm32_scmi_clk *clk = &res->clock[j]; 833 834 if (!clk->name || 835 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 836 panic("SCMI clock name invalid"); 837 838 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 839 assert(clk->clk); 840 841 /* Sync SCMI clocks with their targeted initial state */ 842 if (clk->enabled && 843 stm32mp_nsec_can_access_clock(clk->clock_id)) 844 clk_enable(clk->clk); 845 } 846 847 for (j = 0; j < res->rd_count; j++) { 848 struct stm32_scmi_rd *rd = &res->rd[j]; 849 struct rstctrl *rstctrl = NULL; 850 851 if (!rd->name || 852 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 853 panic("SCMI reset domain name invalid"); 854 855 if (stm32mp_nsec_can_access_clock(rd->reset_id)) 856 continue; 857 858 rstctrl = stm32mp_rcc_reset_id_to_rstctrl(rd->reset_id); 859 assert(rstctrl); 860 if (rstctrl_get_exclusive(rstctrl)) 861 panic(); 862 rd->rstctrl = rstctrl; 863 } 864 865 for (j = 0; j < res->voltd_count; j++) { 866 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 867 868 if (!voltd->name || 869 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 870 panic("SCMI voltage domain name invalid"); 871 } 872 } 873 874 return TEE_SUCCESS; 875 } 876 877 driver_init_late(stm32mp1_init_scmi_server); 878