| a638030b | 07-Dec-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_bsec: remove unused functions
Removes unused functions stm32_bsec_otp_lock() and
stm32_bsec_shadow_register().
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-o
drivers: stm32_bsec: remove unused functions
Removes unused functions stm32_bsec_otp_lock() and
stm32_bsec_shadow_register().
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 7dfc80ab | 12-Dec-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_bsec: add new generic interfaces
Exports generic functions to retrieve the BSEC state and check
if a fuse can be read depending on the BSEC current state.
Adds some robustness in the
drivers: stm32_bsec: add new generic interfaces
Exports generic functions to retrieve the BSEC state and check
if a fuse can be read depending on the BSEC current state.
Adds some robustness in the driver to enforce security when
trying to access a fuse.
It is a preliminary step for BSEC PTA introduction.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 667e576e | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: physical unclonable function
This driver uses the PLM xilpuf service to deliver the physical
unclonable function (PUF).
The Physical unclonable function (PUF) generates two device
drivers: versal: physical unclonable function
This driver uses the PLM xilpuf service to deliver the physical
unclonable function (PUF).
The Physical unclonable function (PUF) generates two device unique
signatures per die. One signature is used for the key encryption key
(KEK) and one signature is used as an unique identification value.
The Unique ID is fully accessible and its value can be cleared
(hidden) and regenerated.
The KEK is never accessible and only usable from the AES-GCM engine.
https://github.com/Xilinx/embeddedsw
[1] TRM: https://docs.xilinx.com/r/en-US/am011-versal-acap-trm
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 93114f2e | 07-Dec-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_bsec: support NVMEM cell description in device-tree
Support the nvmem cells description in device tree and
add the platform helper function stm32_bsec_find_otp_in_nvmem_layout()
that
drivers: stm32_bsec: support NVMEM cell description in device-tree
Support the nvmem cells description in device tree and
add the platform helper function stm32_bsec_find_otp_in_nvmem_layout()
that allows drivers to find an OTP location (BSEC word number and bit
size) from the OTP string identifier, name of the cell in device tree.
The bsec driver directly reads the nvmem cells sub node of bsec device.
This allow to remove the hardcoded OTP index in platform and is aligned
with linux kernel binding.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 1ff52b85 | 12-Dec-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_bsec: move debug defines to include
Moves definition of DEBUG status macros from driver source file to
its header file to allow other drivers to control the debug level.
Introduces BS
drivers: stm32_bsec: move debug defines to include
Moves definition of DEBUG status macros from driver source file to
its header file to allow other drivers to control the debug level.
Introduces BSEC_DEBUG_ALL that is the default debug configuration.
Removes configuration masking as it has no use.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 8396f62e | 15-Dec-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_bsec: rework and move BITS_PER_WORD
Transforms BITS_PER_WORD to BSEC_BITS_PER_WORD to specify it is
BSEC-related and move it to BSEC driver header file.
Adds BSEC_BYTES_PER_WORD for
drivers: stm32_bsec: rework and move BITS_PER_WORD
Transforms BITS_PER_WORD to BSEC_BITS_PER_WORD to specify it is
BSEC-related and move it to BSEC driver header file.
Adds BSEC_BYTES_PER_WORD for later use.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| de7a768c | 30-Nov-2022 |
Xiaoxu Zeng <zengxiaoxu@huawei.com> |
drivers: implement lpc_uart driver
Support for lpc_uart that is a serial driver.
Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: J
drivers: implement lpc_uart driver
Support for lpc_uart that is a serial driver.
Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 7b84e23d | 06-Dec-2022 |
Jerome Forissier <jerome.forissier@linaro.org> |
drivers: struct serial_ops: make all functions optional except putc()
Many platforms only use the putc() function pointer in struct
serial_ops. Therefore, explicitly make the others optional (flush(
drivers: struct serial_ops: make all functions optional except putc()
Many platforms only use the putc() function pointer in struct
serial_ops. Therefore, explicitly make the others optional (flush(),
have_rx_data() and getchar()) by adding comments to the struct and
making sure the code checks the pointer before using them.
With this it should be clear that drivers do not need to provide
stub functions.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 011c182a | 12-Sep-2022 |
Andrew Mustea <andrew.mustea@microsoft.com> |
core: drivers: nxp: Add LX series SFP driver
- Implement reading and writing to the NXP LX2160-series Security Fuse
Processor (SFP).
- Add the CFG_LS_SFP flag to enable building the SFP driver.
-
core: drivers: nxp: Add LX series SFP driver
- Implement reading and writing to the NXP LX2160-series Security Fuse
Processor (SFP).
- Add the CFG_LS_SFP flag to enable building the SFP driver.
- The SFP driver should be able to:
- Read the entire SFP.
- Read the debug level.
- Read the Intent to Secure (ITS) and Secure Boot (SB) flags.
- Read individual OEM Unique Scratch Pad Fuse (OUID) registers.
- Read individual Super Root Key Hash (SRKH) registers.
- Set the debug level.
- Set the device to permanently program the fuse block by
setting the ITS and SB flags.
- Set individual OUID registers.
- Get the status of the SFP driver itself.
- Update fsl-lx2160a device tree with sfp and gpio nodes.
Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 4502832d | 30-Nov-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: SHA3-384 engine support
Enable the PLM controlled SHA3-384 cryptographic engine for TEE core
usage.
Since the engine does not have the concept of "context", it can't
provide the le
drivers: versal: SHA3-384 engine support
Enable the PLM controlled SHA3-384 cryptographic engine for TEE core
usage.
Since the engine does not have the concept of "context", it can't
provide the level support required by user-space (multiple parallel
contexts) hence why it is being provided just to the core.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| fc5444d8 | 16-Nov-2022 |
Ding Tao <miyatsu@qq.com> |
core: include: Fix simple typo in drivers/stm32_gpio.h
Replace "Configuratioh" with "Configuration".
Signed-off-by: Ding Tao <miyatsu@qq.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.
core: include: Fix simple typo in drivers/stm32_gpio.h
Replace "Configuratioh" with "Configuration".
Signed-off-by: Ding Tao <miyatsu@qq.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 55667e70 | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: non volatile memory (eFuse and BBRAM)
Provide an interface to access the xilnvm service executing in the PLM
firmware running on the Microblaze processor.
Signed-off-by: Jorge Rami
drivers: versal: non volatile memory (eFuse and BBRAM)
Provide an interface to access the xilnvm service executing in the PLM
firmware running on the Microblaze processor.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| a3009556 | 11-Aug-2022 |
Michael Scott <mike@foundries.io> |
plat-stm32mp1: add support for i2c5 bus
This allows stm32_i2c driver to properly initialize and use
i2c5 bus on stm32mp15 SoC.
Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Igor O
plat-stm32mp1: add support for i2c5 bus
This allows stm32_i2c driver to properly initialize and use
i2c5 bus on stm32mp15 SoC.
Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 40e40cd2 | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: PM service
Calls the TF-A exported SiP services or PLM PM APIs.
The programming of the FPGA bitstream is being phased out from the TF-A
so it is no longer supported as such: the re
drivers: versal: PM service
Calls the TF-A exported SiP services or PLM PM APIs.
The programming of the FPGA bitstream is being phased out from the TF-A
so it is no longer supported as such: the recommended interface uses
the MBOX driver to the PLM.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 4b46e0e8 | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: mailbox communication
Mailbox driver to communicate with the PLM firmware executing on the
Microblaze processor.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: J
drivers: versal: mailbox communication
Mailbox driver to communicate with the PLM firmware executing on the
Microblaze processor.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 3a340005 | 12-Sep-2022 |
Andrew Mustea <andrew.mustea@microsoft.com> |
core: drivers: nxp: Add LX2160A-series SecMon driver
- This driver implements reading the entire NXP LX2160-series Security
Monitor (SecMon) module.
- To enable the SecMon driver, the optee-os bui
core: drivers: nxp: Add LX2160A-series SecMon driver
- This driver implements reading the entire NXP LX2160-series Security
Monitor (SecMon) module.
- To enable the SecMon driver, the optee-os build requires the
CFG_LS_SEC_MON flag.
Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 4afbdbdd | 01-Aug-2022 |
Anton Eliasson <anton.eliasson@axis.com> |
drivers: scmi-msg: Propagate errors from platform voltd_get_level
plat_scmi_voltd_get_level is refactored to return an SCMI error code and
retrieve the voltage via an out parameter. This allows erro
drivers: scmi-msg: Propagate errors from platform voltd_get_level
plat_scmi_voltd_get_level is refactored to return an SCMI error code and
retrieve the voltage via an out parameter. This allows errors from the
platform SCMI server implementation to be propagated to the REE.
The implementation for stm32mp1 is updated to handle at least some
possible errors.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Anton Eliasson <anton.eliasson@axis.com>
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| cd495a5a | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: general purpose i/o
Provide access to the GPIO controller on Versal ACAP.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.or
drivers: versal: general purpose i/o
Provide access to the GPIO controller on Versal ACAP.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 9756bcc4 | 24-Feb-2022 |
Clement Faure <clement.faure@nxp.com> |
core: driver: add common i.MX MU driver
Add a common MU driver for i.MX platforms. This MU driver is used to
communicate with external security controllers.
This driver includes a generic part and
core: driver: add common i.MX MU driver
Add a common MU driver for i.MX platforms. This MU driver is used to
communicate with external security controllers.
This driver includes a generic part and an hardware abstraction layer
for low level MU functions.
The MU driver implements the HAL for the following platforms:
- mx8ulpevk
- mx8qmmek/imx8qxpmek
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| dfeed924 | 07-May-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zynqmp_huk: Add AES eFuse and HUK seed support
When AES eFuse is used to encrypt boot loaders and bitstreams then PUF
functionality is not available for use. When AES eFuse based encryption
drivers: zynqmp_huk: Add AES eFuse and HUK seed support
When AES eFuse is used to encrypt boot loaders and bitstreams then PUF
functionality is not available for use. When AES eFuse based encryption is
in use AES eFuse key becomes device key instead of PUF generated key.
In order to re-plenish additional device specific entropy that PUF would
provide utilize selected set of User programmable eFuses.
Selected user eFuses should be programmed during device manufacturing with
cryptographically good random numbers.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 214ee971 | 27-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zymqmp_pm: add USER eFuse support
Adds necessary defines for accessing USER eFuses.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.car
drivers: zymqmp_pm: add USER eFuse support
Adds necessary defines for accessing USER eFuses.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 6e96536e | 30-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zynqmp_pm: Add eFuse programming support
Add support to program eFuses utiling functionality found in PMU firmware.
If eFuse programming functionality has been disabled in PMU firmware the
drivers: zynqmp_pm: Add eFuse programming support
Add support to program eFuses utiling functionality found in PMU firmware.
If eFuse programming functionality has been disabled in PMU firmware then
programming will fail.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 97558570 | 29-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zynqmp_pm: fix cache alignment for eFuse operation
Allocate cache aligned temporary memory for both eFuse operation request
and data buffer to make sure that operation is always cache align
drivers: zynqmp_pm: fix cache alignment for eFuse operation
Allocate cache aligned temporary memory for both eFuse operation request
and data buffer to make sure that operation is always cache aligned and to
make usage easier.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 48ca91ed | 31-Mar-2021 |
Vahid Dukandar <vahidd@microsoft.com> |
drivers: bcm_sotp: add sotp write support
- Added write support for bcm secure one time programmable fuses.
- bcm_iproc_sotp_mem_read() now takes in a bool value for sotp_add_ecc
instead of an int
drivers: bcm_sotp: add sotp write support
- Added write support for bcm secure one time programmable fuses.
- bcm_iproc_sotp_mem_read() now takes in a bool value for sotp_add_ecc
instead of an int to denote if error checking memory is supported.
- Updated debug and error messages to return TEE_result codes.
Signed-off-by: Vahid Dukandar <vahidd@microsoft.com>
Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| dc357ecd | 06-Jul-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp1: scmi_server update for STM32MP13
Update the SCMI server to support STM32MP13 and its SCMI domains: clock,
reset and voltage.
This change also remove the '0' index to the SCMI domains
plat-stm32mp1: scmi_server update for STM32MP13
Update the SCMI server to support STM32MP13 and its SCMI domains: clock,
reset and voltage.
This change also remove the '0' index to the SCMI domains in order to
align with Linux kernel.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
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