1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 3flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 4flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 5flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 6 7flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) 8 9flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 10 11flavorlist-cryp-1G = $(flavor_dts_file-157C_ED1) \ 12 $(flavor_dts_file-157C_EV1) 13 14flavorlist-no_cryp = $(flavorlist-no_cryp-512M) 15 16flavorlist-512M = $(flavorlist-cryp-512M) \ 17 $(flavorlist-no_cryp-512M) 18 19flavorlist-1G = $(flavorlist-cryp-1G) 20 21ifneq ($(PLATFORM_FLAVOR),) 22ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 23$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 24endif 25CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 26endif 27 28ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 29$(call force,CFG_STM32_CRYP,n) 30endif 31 32include core/arch/arm/cpu/cortex-a7.mk 33 34$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 35$(call force,CFG_DRIVERS_CLK,y) 36$(call force,CFG_DRIVERS_CLK_FIXED,n) 37$(call force,CFG_GIC,y) 38$(call force,CFG_INIT_CNTVOFF,y) 39$(call force,CFG_PSCI_ARM32,y) 40$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 41$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 42$(call force,CFG_SM_PLATFORM_HANDLER,y) 43$(call force,CFG_STM32_SHARED_IO,y) 44$(call force,CFG_WITH_SOFTWARE_PRNG,y) 45 46CFG_TEE_CORE_NB_CORE ?= 2 47CFG_WITH_PAGER ?= y 48CFG_WITH_LPAE ?= y 49CFG_MMAP_REGIONS ?= 23 50CFG_DTB_MAX_SIZE ?= (256 * 1024) 51CFG_CORE_ASLR ?= n 52 53ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),) 54# Some drivers mandate DT support 55$(call force,CFG_DRIVERS_CLK_DT,n) 56$(call force,CFG_STM32_CRYP,n) 57$(call force,CFG_STM32_GPIO,n) 58$(call force,CFG_STM32_I2C,n) 59$(call force,CFG_STM32_IWDG,n) 60$(call force,CFG_STM32_TAMP,n) 61$(call force,CFG_STPMIC1,n) 62$(call force,CFG_STM32MP1_SCMI_SIP,n) 63$(call force,CFG_SCMI_PTA,n) 64else 65$(call force,CFG_DRIVERS_CLK_DT,y) 66endif 67 68ifeq ($(CFG_STM32MP13),y) 69$(call force,CFG_CORE_RESERVED_SHM,n) 70$(call force,CFG_STM32MP15,n) 71$(call force,CFG_STM32MP_CLK_CORE,y) 72$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 73$(call force,CFG_STM32MP13_CLK,y) 74$(call force,CFG_STM32MP15_CLK,n) 75CFG_STM32MP_OPP_COUNT ?= 2 76else 77$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 78CFG_CORE_RESERVED_SHM ?= y 79$(call force,CFG_STM32MP15,y) 80$(call force,CFG_STM32MP15_CLK,y) 81endif 82 83ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 84CFG_TZDRAM_START ?= 0xde000000 85CFG_DRAM_SIZE ?= 0x20000000 86endif 87 88CFG_DRAM_BASE ?= 0xc0000000 89CFG_DRAM_SIZE ?= 0x40000000 90CFG_TZSRAM_START ?= 0x2ffc0000 91CFG_TZSRAM_SIZE ?= 0x0003f000 92CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 93CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 94ifeq ($(CFG_STM32MP15),y) 95CFG_TZDRAM_START ?= 0xfe000000 96CFG_TZDRAM_SIZE ?= 0x01e00000 97ifeq ($(CFG_CORE_RESERVED_SHM),y) 98CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 99CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 100endif 101else 102CFG_TZDRAM_SIZE ?= 0x02000000 103CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 104endif #CFG_STM32MP15 105 106CFG_STM32_BSEC ?= y 107CFG_STM32_CRYP ?= y 108CFG_STM32_ETZPC ?= y 109CFG_STM32_GPIO ?= y 110CFG_STM32_I2C ?= y 111CFG_STM32_IWDG ?= y 112CFG_STM32_RNG ?= y 113CFG_STM32_RSTCTRL ?= y 114CFG_STM32_TAMP ?= y 115CFG_STM32_UART ?= y 116CFG_STPMIC1 ?= y 117CFG_TZC400 ?= y 118 119ifeq ($(CFG_STPMIC1),y) 120$(call force,CFG_STM32_I2C,y) 121$(call force,CFG_STM32_GPIO,y) 122endif 123 124# if any crypto driver is enabled, enable the crypto-framework layer 125ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 126$(call force,CFG_STM32_CRYPTO_DRIVER,y) 127endif 128 129CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 130$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 131 132CFG_WDT ?= $(CFG_STM32_IWDG) 133 134# Platform specific configuration 135CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 136 137# SiP/OEM service for non-secure world 138CFG_STM32_BSEC_SIP ?= y 139CFG_STM32MP1_SCMI_SIP ?= n 140ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 141$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 142$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 143$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 144endif 145 146# Default enable SCMI PTA support 147CFG_SCMI_PTA ?= y 148ifeq ($(CFG_SCMI_PTA),y) 149$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 150$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 151CFG_SCMI_MSG_SHM_MSG ?= y 152CFG_SCMI_MSG_SMT ?= y 153endif 154 155CFG_SCMI_MSG_DRIVERS ?= n 156ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 157$(call force,CFG_SCMI_MSG_CLOCK,y) 158$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 159CFG_SCMI_MSG_SHM_MSG ?= y 160CFG_SCMI_MSG_SMT ?= y 161CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 162$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 163endif 164 165# Provision enough threads to pass xtest 166ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 167ifeq ($(CFG_WITH_PAGER),y) 168CFG_NUM_THREADS ?= 3 169else 170CFG_NUM_THREADS ?= 10 171endif 172endif 173 174# Default enable some test facitilites 175CFG_ENABLE_EMBEDDED_TESTS ?= y 176CFG_WITH_STATS ?= y 177 178# Enable to allow debug 179CFG_STM32_BSEC_WRITE ?= $(CFG_TEE_CORE_DEBUG) 180 181# Default disable some support for pager memory size constraint 182ifeq ($(CFG_WITH_PAGER),y) 183CFG_TEE_CORE_DEBUG ?= n 184CFG_UNWIND ?= n 185CFG_LOCKDEP ?= n 186CFG_TA_BGET_TEST ?= n 187# Default disable early TA compression to support a smaller HEAP size 188CFG_EARLY_TA_COMPRESS ?= n 189CFG_CORE_HEAP_SIZE ?= 49152 190endif 191 192# Non-secure UART and GPIO/pinctrl for the output console 193CFG_WITH_NSEC_GPIOS ?= y 194CFG_WITH_NSEC_UARTS ?= y 195# UART instance used for early console (0 disables early console) 196CFG_STM32_EARLY_CONSOLE_UART ?= 4 197