stm32_bsec: OTP driver for stm32mp platforms

BSEC is a one time programmable (OTP) memory interface for stm32mp
SoCs. OTPs are grouped into 32bit words identified by a incremental ID
starting from 0

stm32_bsec: OTP driver for stm32mp platforms

BSEC is a one time programmable (OTP) memory interface for stm32mp
SoCs. OTPs are grouped into 32bit words identified by a incremental ID
starting from 0. Shadowed OTPs are loaded in a volatile memory yet
used as OTP values by the software.

The platform shall implement stm32mp_get_bsec_static_cfg() to
provide BSEC driver some information as the BSEC memory size and
its lower/upper threshold ID that split non-secure from secure OTPs.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Christophe Montaud <christophe.montaud@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: GICv3: Configure native secure interrupt

OP-TEE dispatcher registers with TF-A to handle EL1S interrupts
by design. OP-TEE should own the G1S interrupts in GICv3.
-gic_it_add() should resul

drivers: GICv3: Configure native secure interrupt

OP-TEE dispatcher registers with TF-A to handle EL1S interrupts
by design. OP-TEE should own the G1S interrupts in GICv3.
-gic_it_add() should result in configuring a given interrupt to
G1S instead of G0 for GICv3.
-G1S interrupts to be enabled at distributor interface.
-system interface register ICC_IGRPEN1_EL1 to be used to enable
G1S interrupts.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Reviewed-by: Soby Mathew <soby.mathew@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: upgrade from write32() to io_write32() and friends

Replace use of readX() and writeX() with io_readX() and io_writeX().
The former function are about to be deprecated in favor to the later.

T

core: upgrade from write32() to io_write32() and friends

Replace use of readX() and writeX() with io_readX() and io_writeX().
The former function are about to be deprecated in favor to the later.

This change upgrades core generic code and drivers.
At some place, io_clrbitsX(), io_setbitsX() and io_clrsetbitsX()
replace the writeX(readX() ...) operations when obvious.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity

Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LP

core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity

Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LPAE). This is not
needed and possibly incorrect for SoCs that define I/O memory maps with
regions aligned on a small page (4 KiB), because using a larger
granularity could result in overlaps between secure and non-secure
mappings. This could cause issues depending on the type of memory
firewall used by the SoC and its configuration. In any case, memory
types other than MEM_AREA_IO_{SEC,NSEC} *can* be mapped with small page
granularity using register_phys_mem(), so the situation is a bit
inconsistent.

This commit removes the rounding by default and provides a new macro:
register_phys_mem_pgdir(). Platforms that still need to use PGDIR_SIZE
granularity (typically because it consumes less page table space) need
to replace register_phys_mem() by register_phys_mem_pgdir().

In order to avoid any functional change in platform code, all calls to
register_phys_mem() with device memory are replaced with
register_phys_mem_pgdir(). In addition, CORE_MMU_DEVICE_SIZE is removed
and replaced with CORE_MMU_PGDIR_SIZE since there is no unique mapping
size for device memory anymore.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: change io_{clr|set|clrset}bits32() address argument type

Change API for io_clrbits32(), io_setbits32() and io_clrsetbits32() to
have a vaddr_t type address argument, rather than uintptr_t as
p

core: change io_{clr|set|clrset}bits32() address argument type

Change API for io_clrbits32(), io_setbits32() and io_clrsetbits32() to
have a vaddr_t type address argument, rather than uintptr_t as
previously.

This change updates accordingly the callers of these functions
that cover only stm32mp1 related resources.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32_gpio: driver for GPIO and pin control

Driver is embedded upon CFG_STM32_GPIO=y.

STM32 GPIO driver API main functions:
- stm32_gpio_set_output_level() sets target output GPIO level,
- stm32_gp

stm32_gpio: driver for GPIO and pin control

Driver is embedded upon CFG_STM32_GPIO=y.

STM32 GPIO driver API main functions:
- stm32_gpio_set_output_level() sets target output GPIO level,
- stm32_gpio_get_input_level() returns target input GPIO level,
- stm32_pinctrl_load_active_cfg() loads interface pin mux active state,
- stm32_pinctrl_load_standby_cfg() loads interface pin mux standby state,
- stm32_pinctrl_fdt_get_pinctrl() save pin configuration from DT content,
- stm32_gpio_set_secure_cfg() sets secure state for target GPIO/pin mux.

GPIO driver does not register to PM framework. It is the GPIO/pin owner
responsibility to call stm32_pinctrl_load_{active|standby}_cfg() on
peripherals power state transitions.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32_etzpc: STM32 Extended TrustZone Protection Controller

ETZPC is a hardware instance that control access permissions to
some stm32mp SoC peripheral interfaces and internal memories.

This change

stm32_etzpc: STM32 Extended TrustZone Protection Controller

ETZPC is a hardware instance that control access permissions to
some stm32mp SoC peripheral interfaces and internal memories.

This change introduce the stm32_etzpc driver. It is embedded upon
build directive CFG_STM32_ETZPC=y.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Mathieu BELOU <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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pl011.c: use nex_malloc allocator

pl011 driver is a core code, so it should use nexus memory allocator.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.w

pl011.c: use nex_malloc allocator

pl011 driver is a core code, so it should use nexus memory allocator.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32_uart: API to init console bus from a DTB

Introduce stm32_uart_init_from_dt_node() that initializes an UART
device from the given DT node. The function returns the reference
to the created UART

stm32_uart: API to init console bus from a DTB

Introduce stm32_uart_init_from_dt_node() that initializes an UART
device from the given DT node. The function returns the reference
to the created UART instance.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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stm32_uart: rename exported structure and add secure flag

Rename structure console_pdata into stm32_uart_pdata as it will
be exported over the platform and should not use such a generic
naming.

Thi

stm32_uart: rename exported structure and add secure flag

Rename structure console_pdata into stm32_uart_pdata as it will
be exported over the platform and should not use such a generic
naming.

This change adds a secure flag to the UART device instance for
used to get the appropriate virtual address when required.
An UART bus could be used by the secure world in secure mode or
in non-secure mode. A bus to a secure element likely mandates
secure hardening of the UART. A debug console over a non-secure
UART link may require the UART resources to be assigned to the
non-secure world.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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probe_max_it overwrite the value of GICD_ISENABLER

probe_max_it save the original value of GICD_ISENABLER
and write 0xffffffff into GICD_ISENABLER to probe
the largest interrupt number.

Instead of

probe_max_it overwrite the value of GICD_ISENABLER

probe_max_it save the original value of GICD_ISENABLER
and write 0xffffffff into GICD_ISENABLER to probe
the largest interrupt number.

Instead of writing the original GICD_ISENABLER value
into GICD_ISENABLER, probe_max_it write the value into GICD_ICENABLER
and cause the original GICD_ISENABLER value bit flipping.

Signed-off-by: Lin Huang-Sen <r94922102@gmail.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32_uart: timeout to escape waiting loops

Add a timeout in output console waiting loops. This is useful if
the secure world relies on a non-secure UART that may be suspended
or disabled from the n

stm32_uart: timeout to escape waiting loops

Add a timeout in output console waiting loops. This is useful if
the secure world relies on a non-secure UART that may be suspended
or disabled from the non-secure world.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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imx: wdog: Introduce CFG_IMX_WDOG_EXT_RESET for non-DTB mode

When resetting a system that has not booted up with a full DTB in memory
the value ext_reset will always be false.

This patch introduces

imx: wdog: Introduce CFG_IMX_WDOG_EXT_RESET for non-DTB mode

When resetting a system that has not booted up with a full DTB in memory
the value ext_reset will always be false.

This patch introduces a platform define to tell the watchdog driver to
drive ext_reset.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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imx: wdog: Skip DTB wdog init on DTB overlay

When OPTEE is providing a DTB overlay to a subsequent boot stage CFG_DT
will be true as will CFG_EXTERNAL_DTB_OVERLAY.

In this case there will be no DTB

imx: wdog: Skip DTB wdog init on DTB overlay

When OPTEE is providing a DTB overlay to a subsequent boot stage CFG_DT
will be true as will CFG_EXTERNAL_DTB_OVERLAY.

In this case there will be no DTB for the imx watchdog driver to consume so
do not try to do so.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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core: rename get_dt_blob() into get_dt()

Rename get_dt_blob() into get_dt() to get some consistency in `dt`,
`dtb`, `fdt` labelling in generic_boot.c

Signed-off-by: Etienne Carriere <etienne.carrie

core: rename get_dt_blob() into get_dt()

Rename get_dt_blob() into get_dt() to get some consistency in `dt`,
`dtb`, `fdt` labelling in generic_boot.c

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: serial8250_uart_dev_init(): use calloc()

Allocate pl011_data with calloc() instead of malloc() get initialized
memory.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Fixes: d2769

core: serial8250_uart_dev_init(): use calloc()

Allocate pl011_data with calloc() instead of malloc() get initialized
memory.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Fixes: d276907c8c4f ("core: drivers: serial8250_uart: Add DT support")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pl011_dev_alloc(): use calloc()

Allocate pl011_data with calloc() instead of malloc() get initialized
memory.

Without this could pd->base.va contain garbage when pl011_init() is
called.

Revi

core: pl011_dev_alloc(): use calloc()

Allocate pl011_data with calloc() instead of malloc() get initialized
memory.

Without this could pd->base.va contain garbage when pl011_init() is
called.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Fixes: ddf45954360c ("pl011: dt: Add DT support")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: GICv3: Handle group 1 secure interrupts

As per GICv3 architecture specification (Section 4.6 Interrupt grouping),
secure EL1 (Trusted OS) handles secure group 1 physical interrupts and
EL3

drivers: GICv3: Handle group 1 secure interrupts

As per GICv3 architecture specification (Section 4.6 Interrupt grouping),
secure EL1 (Trusted OS) handles secure group 1 physical interrupts and
EL3 handles group 0 physical interrupts which are considered as FIQs
(foreign interrupt) for Trusted OS.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (FVP)
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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drivers: imx_uart: avoid hang if UART is disabled

Avoid indefinite hangs by not writing to the UART if it's disabled.
If the UART is disabled, the write and flush routines will hang
indefinitely whi

drivers: imx_uart: avoid hang if UART is disabled

Avoid indefinite hangs by not writing to the UART if it's disabled.
If the UART is disabled, the write and flush routines will hang
indefinitely which can be difficult to debug.

Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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drivers: imx_uart: ensure space in TX UART before writing

Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

plat-imx: add mx7dclsom platform flavor

Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

core: correct unpaged constraint on GIC driver

Release of secondary boot cores on 32bit machine use SMC that
issue a SGI on secondary core. Since the interrupt is raised
from the monitor mode, the r

core: correct unpaged constraint on GIC driver

Release of secondary boot cores on 32bit machine use SMC that
issue a SGI on secondary core. Since the interrupt is raised
from the monitor mode, the related GIC driver resources must be
tagged as unpaged.

This change costs around 300 bytes of unpaged resident memory.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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imx: wdog: correct wdog_path

The prefix `0` is removed in Linux Kernel upstream code,
so let's drop it to let wdog work.

Linux Kernel commit 67b8d5c7081221efa252("Linux 4.17-rc5")

Signed-off-by: P

imx: wdog: correct wdog_path

The prefix `0` is removed in Linux Kernel upstream code,
so let's drop it to let wdog work.

Linux Kernel commit 67b8d5c7081221efa252("Linux 4.17-rc5")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: hi16xx_rng: replace mutex with spinlock

The mutex in hw_get_random_byte() protects a very short section of code.
A spinlock is more lightweight and therefore better suited to the task.

Sig

drivers: hi16xx_rng: replace mutex with spinlock

The mutex in hw_get_random_byte() protects a very short section of code.
A spinlock is more lightweight and therefore better suited to the task.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: imx_wdog driver cleanup

use WDT_WCR defined in watchdog specific imx_wdog.h
instead of WCR_OFF defined in the platform imx-regs.h

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>

drivers: imx_wdog driver cleanup

use WDT_WCR defined in watchdog specific imx_wdog.h
instead of WCR_OFF defined in the platform imx-regs.h

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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