1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_I2C_H 7 #define __STM32_I2C_H 8 9 #include <drivers/stm32_gpio.h> 10 #include <mm/core_memprot.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <util.h> 14 #include <types_ext.h> 15 16 /* 17 * Initialization configuration structure for the STM32 I2C bus. 18 * Refer to the SoC Reference Manual for more details on configuration items. 19 * 20 * @pbase: I2C interface base address 21 * @clock: I2C bus/interface clock 22 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode 23 * @own_address1: 7-bit or 10-bit first device own address. 24 * @dual_address_mode: True if enabling Dual-Addressing mode 25 * @own_address2: 7-bit second device own address (Dual-Addressing mode) 26 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode) 27 * @general_call_mode: True if enbling General-Call mode 28 * @no_stretch_mode: If enabling the No-Stretch mode 29 * @rise_time: SCL clock pin rising time in nanoseconds 30 * @fall_time: SCL clock pin falling time in nanoseconds 31 * @speed_mode: I2C clock source frequency mode 32 * @analog_filter: True if enabling analog filter 33 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX) 34 */ 35 struct stm32_i2c_init_s { 36 paddr_t pbase; 37 unsigned int clock; 38 bool addr_mode_10b_not_7b; 39 uint32_t own_address1; 40 bool dual_address_mode; 41 uint32_t own_address2; 42 uint32_t own_address2_masks; 43 bool general_call_mode; 44 bool no_stretch_mode; 45 uint32_t rise_time; 46 uint32_t fall_time; 47 enum i2c_speed_e speed_mode; 48 bool analog_filter; 49 uint8_t digital_filter_coef; 50 }; 51 52 enum i2c_state_e { 53 I2C_STATE_RESET, /* Not yet initialized */ 54 I2C_STATE_READY, /* Ready for use */ 55 I2C_STATE_BUSY, /* Internal process ongoing */ 56 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */ 57 I2C_STATE_BUSY_RX, /* Data Reception ongoing */ 58 I2C_STATE_SUSPENDED, /* Bus is supended */ 59 }; 60 61 enum i2c_mode_e { 62 I2C_MODE_NONE, /* No active communication */ 63 I2C_MODE_MASTER, /* Communication in Master Mode */ 64 I2C_MODE_SLAVE, /* Communication in Slave Mode */ 65 I2C_MODE_MEM, /* Communication in Memory Mode */ 66 }; 67 68 #define I2C_ERROR_NONE 0x0 69 #define I2C_ERROR_BERR BIT(0) 70 #define I2C_ERROR_ARLO BIT(1) 71 #define I2C_ERROR_ACKF BIT(2) 72 #define I2C_ERROR_OVR BIT(3) 73 #define I2C_ERROR_DMA BIT(4) 74 #define I2C_ERROR_TIMEOUT BIT(5) 75 #define I2C_ERROR_SIZE BIT(6) 76 77 /* I2C interface registers state */ 78 struct i2c_cfg { 79 uint32_t timingr; 80 uint32_t oar1; 81 uint32_t oar2; 82 uint32_t cr1; 83 uint32_t cr2; 84 }; 85 86 /* 87 * I2C bus device 88 * @base: I2C SoC registers base address 89 * @clock: clock ID 90 * @i2c_state: Driver state ID I2C_STATE_* 91 * @i2c_err: Last error code I2C_ERROR_* 92 * @sec_cfg: I2C regsiters configuration storage 93 * @pinctrl: PINCTRLs configuration for the I2C PINs 94 * @pinctrl_count: Number of PINCTRLs elements 95 */ 96 struct i2c_handle_s { 97 struct io_pa_va base; 98 unsigned long clock; 99 enum i2c_state_e i2c_state; 100 uint32_t i2c_err; 101 struct i2c_cfg sec_cfg; 102 struct stm32_pinctrl *pinctrl; 103 size_t pinctrl_count; 104 }; 105 106 /* STM32 specific defines */ 107 #define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD 108 #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ 109 #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ 110 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 111 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 112 #define STM32_I2C_DIGITAL_FILTER_MAX 16 113 114 /* 115 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 116 * 117 * @fdt: Reference to DT 118 * @node: Target I2C node in the DT 119 * @init: Output stm32_i2c_init_s structure 120 * @pinctrl: Reference to output pinctrl array 121 * @pinctrl_count: Input @pinctrl array size, output expected size 122 * Return 0 on success else a negative value 123 */ 124 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 125 struct stm32_i2c_init_s *init, 126 struct stm32_pinctrl **pinctrl, 127 size_t *pinctrl_count); 128 129 /* 130 * Initialize I2C bus handle from input configuration directives 131 * 132 * @hi2c: Reference to I2C bus handle structure 133 * @init_data: Input stm32_i2c_init_s structure 134 * Return 0 on success else a negative value 135 */ 136 int stm32_i2c_init(struct i2c_handle_s *hi2c, 137 struct stm32_i2c_init_s *init_data); 138 139 /* 140 * Send a memory write request in the I2C bus 141 * 142 * @hi2c: Reference to I2C bus handle structure 143 * @dev_addr: Target device I2C address 144 * @mem_addr: Target device memory address 145 * @mem_addr_size: Byte size of internal memory address 146 * @p_data: Data to be written 147 * @size: Byte size of the data to be written 148 * @timeout_ms: Timeout value in milliseconds 149 * Return 0 on success else a negative value 150 */ 151 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 152 uint32_t mem_addr, uint32_t mem_addr_size, 153 uint8_t *p_data, size_t size, unsigned int timeout_ms); 154 155 /* 156 * Send a memory read request in the I2C bus 157 * 158 * @hi2c: Reference to I2C bus handle structure 159 * @dev_addr: Target device I2C address 160 * @mem_addr: Target device memory address 161 * @mem_addr_size: Byte size of internal memory address 162 * @p_data: Data to be read 163 * @size: Byte size of the data to be read 164 * @timeout_ms: Timeout value in milliseconds 165 * Return 0 on success else a negative value 166 */ 167 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 168 uint32_t mem_addr, uint32_t mem_addr_size, 169 uint8_t *p_data, size_t size, unsigned int timeout_ms); 170 171 /* 172 * Send a data buffer in master mode on the I2C bus 173 * 174 * @hi2c: Reference to I2C bus handle structure 175 * @dev_addr: Target device I2C address 176 * @p_data: Data to be sent 177 * @size: Byte size of the data to be sent 178 * @timeout_ms: Timeout value in milliseconds 179 * Return 0 on success else a negative value 180 */ 181 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 182 uint8_t *p_data, size_t size, 183 unsigned int timeout_ms); 184 185 /* 186 * Receive a data buffer in master mode on the I2C bus 187 * 188 * @hi2c: Reference to I2C bus handle structure 189 * @dev_addr: Target device I2C address 190 * @p_data: Buffer for the received data 191 * @size: Byte size of the data to be received 192 * @timeout_ms: Timeout value in milliseconds 193 * Return 0 on success else a negative value 194 */ 195 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 196 uint8_t *p_data, size_t size, 197 unsigned int timeout_ms); 198 199 /* 200 * Check link with the I2C device 201 * 202 * @hi2c: Reference to I2C bus handle structure 203 * @dev_addr: Target device I2C address 204 * @trials: Number of attempts of I2C request 205 * @timeout_ms: Timeout value in milliseconds for each I2C request 206 * Return 0 on success else a negative value 207 */ 208 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 209 unsigned int trials, unsigned int timeout_ms); 210 211 /* 212 * Suspend I2C bus. 213 * Bus owner is reponsible for calling stm32_i2c_suspend(). 214 * 215 * @hi2c: Reference to I2C bus handle structure 216 */ 217 void stm32_i2c_suspend(struct i2c_handle_s *hi2c); 218 219 /* 220 * Resume I2C bus. 221 * Bus owner is reponsible for calling stm32_i2c_resume(). 222 * 223 * @hi2c: Reference to I2C bus handle structure 224 */ 225 void stm32_i2c_resume(struct i2c_handle_s *hi2c); 226 227 #endif /* __STM32_I2C_H */ 228