| 3b4c661f | 09-Oct-2019 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
plat-rockchip: make hardcoded uart optional
Rockchip SoCs can obviously use multiple uarts and while there is always
a uart used on the reference designs and hence on most boards, some boards
may wa
plat-rockchip: make hardcoded uart optional
Rockchip SoCs can obviously use multiple uarts and while there is always
a uart used on the reference designs and hence on most boards, some boards
may want to use a different uart.
OP-TEE can already initialize the uart from a chosen node from devicetree
and only needs the hardcoded uart for really early logs which will only
be needed during development.
So make the hard-coded uart optional and make it configurable via
the newly introduced CFG_EARLY_CONSOLE config settings.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Acked-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 08ede025 | 09-Oct-2019 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
plat-rockchip: setup thread_handlers when working with Trusted Firmware
Most Rockchip platforms will use Trusted Firmware. All Aarch64 SoCs will
do so, but also the rk3288 has TF-A support and could
plat-rockchip: setup thread_handlers when working with Trusted Firmware
Most Rockchip platforms will use Trusted Firmware. All Aarch64 SoCs will
do so, but also the rk3288 has TF-A support and could use OP-TEE as secure
payload, with the RK322x SoC being the exception.
Therefore setup the thread_handlers in a way to work for both cases.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 0ec6631d | 09-Oct-2019 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
plat-rockchip: make gic init handle both GICv2 and GICv3
For a gic-v3 the setup is slightly different, so make sure the
gic init handles both correctly for future platform-flavours.
Signed-off-by:
plat-rockchip: make gic init handle both GICv2 and GICv3
For a gic-v3 the setup is slightly different, so make sure the
gic init handles both correctly for future platform-flavours.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Acked-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| a557db0a | 09-Oct-2019 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
plat-rockchip: map io peripherals individually
Most Rockchip platforms will generally only need a very minimal subset
of a SoCs peripherals, so there is no need to map the whole io area
and instead
plat-rockchip: map io peripherals individually
Most Rockchip platforms will generally only need a very minimal subset
of a SoCs peripherals, so there is no need to map the whole io area
and instead we should only map the relevant devices.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Acked-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 9fece2d8 | 09-Oct-2019 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
plat-rockchip: move memory layout from platform_config to conf.mk
Makes it easier to integrate additional flavours later on.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Ack
plat-rockchip: move memory layout from platform_config to conf.mk
Makes it easier to integrate additional flavours later on.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Acked-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 890d6751 | 09-Oct-2019 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
plat-rockchip: remove boilerplate license blocks
All Rockchip platform files do have SPDX tags denoting the files licenses,
so there is no need to keep the now duplicate license boilerplate around.
plat-rockchip: remove boilerplate license blocks
All Rockchip platform files do have SPDX tags denoting the files licenses,
so there is no need to keep the now duplicate license boilerplate around.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| bfabce22 | 28-Oct-2019 |
Rouven Czerwinski <r.czerwinski@pengutronix.de> |
core: imx: disable CAAM for all i.MX6/7 flavors
Currently, using an upstream kernel with i.MX6/7 devices and OP-TEE
results in OP-TEE stalling during the loading of trusted applications.
OP-TEE trie
core: imx: disable CAAM for all i.MX6/7 flavors
Currently, using an upstream kernel with i.MX6/7 devices and OP-TEE
results in OP-TEE stalling during the loading of trusted applications.
OP-TEE tries to use the CAAM for verification, unfortunately the
upstream kernel will turn off the clocks for the CAAM, resulting in the
bus transaction stalling on the bus and the processor requiring a hard
reset. Disable the NXP CAAM driver until the clock issues are resolved.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>
show more ...
|
| cf1879b1 | 29-Oct-2019 |
Renê de Souza Pinto <Rene.deSouzaPinto@opensynergy.com> |
hikey: Move console_data to __nex_bss
Move console data into __nex_bss section for hikey platform
to work properly when virtualization is enabled.
Signed-off-by: Renê de Souza Pinto <Rene.deSouzaPi
hikey: Move console_data to __nex_bss
Move console data into __nex_bss section for hikey platform
to work properly when virtualization is enabled.
Signed-off-by: Renê de Souza Pinto <Rene.deSouzaPinto@opensynergy.com>
Acked-by: Michalis Pappas <mpp@opensynergy.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| d5147581 | 24-Oct-2019 |
Michalis Pappas <mpp@opensynergy.com> |
core: Fix value of OPTEE_SMC_SEC_CAP_VIRTUALIZATION
Update the value of OPTEE_SEC_CAP_VIRTUALIZATION as it currently conflicts
with OPTEE_SEC_CAP_DYNAMIC_SHM
Signed-off-by: Michalis Pappas <mpp@ope
core: Fix value of OPTEE_SMC_SEC_CAP_VIRTUALIZATION
Update the value of OPTEE_SEC_CAP_VIRTUALIZATION as it currently conflicts
with OPTEE_SEC_CAP_DYNAMIC_SHM
Signed-off-by: Michalis Pappas <mpp@opensynergy.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
show more ...
|
| 099918f6 | 05-Sep-2019 |
Sumit Garg <sumit.garg@linaro.org> |
ftrace: Add support for syscall function tracer
This patch adds support for syscall tracing in TEE core. It complements
existing ftrace support for user TAs via adding trace for syscalls that
are in
ftrace: Add support for syscall function tracer
This patch adds support for syscall tracing in TEE core. It complements
existing ftrace support for user TAs via adding trace for syscalls that
are invoked by user TAs into the TEE core.
And after this patch ftrace will cover both TA and TEE core code. So lets
rename config option from CFG_TA_FTRACE_SUPPORT to CFG_FTRACE_SUPPORT.
It is optional to enable syscall trace via CFG_SYSCALL_FTRACE=y config
option in addition to CFG_FTRACE_SUPPORT=y config option.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| 8be2de1a | 23-Sep-2019 |
Imre Kis <imre.kis@arm.com> |
core: Add support for multi-threaded MPIDR values
If the MT bit is set the affinities are shifted in the MPIDR register
so the get_core_pos_mpidr function needs to be modified accordingly.
This is n
core: Add support for multi-threaded MPIDR values
If the MT bit is set the affinities are shifted in the MPIDR register
so the get_core_pos_mpidr function needs to be modified accordingly.
This is necessary to make OP-TEE to be able to run on multi-threaded
systems. The number of threads/core can be modified by the
CFG_CORE_THREAD_SHIFT makefile parameter. The default value is the
existing single threaded mode.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| d2242b1a | 07-Oct-2019 |
Daniel McIlvaney <damcilva@microsoft.com> |
core: early_ta: fix tag hash calculation
Previously correct output due to the order of execution (tag is
calculated before any reads) and crypto_hash_final taking the minimum
of digest length and bu
core: early_ta: fix tag hash calculation
Previously correct output due to the order of execution (tag is
calculated before any reads) and crypto_hash_final taking the minimum
of digest length and buffer length, but this will be more reliable.
Signed-off-by: Daniel McIlvaney <damcilva@microsoft.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 318b762e | 07-Oct-2019 |
Jerome Forissier <jerome@forissier.org> |
hikey, hikey960: set CFG_TEE_RAM_VA_SIZE to 2 MiB
Commit 8fd4d26f6e22 ("plat-hikey: support generic RAM layout") has
inadvertently removed the platform-specific definition of
TEE_RAM_VA_SIZE for HiK
hikey, hikey960: set CFG_TEE_RAM_VA_SIZE to 2 MiB
Commit 8fd4d26f6e22 ("plat-hikey: support generic RAM layout") has
inadvertently removed the platform-specific definition of
TEE_RAM_VA_SIZE for HiKey platforms. It was 2 MiB before, and became
1 MiB (the default). This commit restores the proper value.
Fixes the following panic on boot (HiKey960, 32-bit TEE core with pager
enabled):
I/TC: Pager is enabled. Hashes: 1824 bytes
I/TC: Pager pool size: 252kB
I/TC: OP-TEE version: 3.6.0-182-g2d7a8964df-dev (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11)) #5 Mon 07 Oct 2019 08:22:21 AM UTC arm
E/TC:0 0 Panic at core/lib/libtomcrypt/mpi_desc.c:39 <get_mp_scratch_memory_pool>
E/TC:0 0 Call stack:
E/TC:0 0 0x3f003a4d
Fixes: 8fd4d26f6e22 ("plat-hikey: support generic RAM layout")
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 2d7a8964 | 06-Aug-2019 |
Cedric Neveux <cedric.neveux@nxp.com> |
driver: implement CAAM driver
Add the NXP CAAM drivers:
- Random generator (instantiation and random generation)
- Hash
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Etienne Ca
driver: implement CAAM driver
Add the NXP CAAM drivers:
- Random generator (instantiation and random generation)
- Hash
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 0f68a8c3 | 04-Sep-2019 |
Clement Faure <clement.faure@nxp.com> |
core: imx: add imx7ulp CRM registers
Add imx7ulp CRM registers in a header file.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> |
| 38f4260c | 17-Sep-2019 |
Jerome Forissier <jerome@forissier.org> |
TA dev kit: Clang support
Updates ta/mk/ta_dev_kit.mk and other makefiles so that the COMPILER
variable can be used when building TAs: make COMPILER=clang ...
Signed-off-by: Jerome Forissier <jerom
TA dev kit: Clang support
Updates ta/mk/ta_dev_kit.mk and other makefiles so that the COMPILER
variable can be used when building TAs: make COMPILER=clang ...
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 98d863a5 | 05-Jul-2019 |
Jerome Forissier <jerome@forissier.org> |
Experimental Clang support
Allows building with Clang with "make COMPILER=clang [other flags...]".
The clang command has to be in the $PATH, as well as the associated
tools (clang-cpp, ld.lld, llvm-
Experimental Clang support
Allows building with Clang with "make COMPILER=clang [other flags...]".
The clang command has to be in the $PATH, as well as the associated
tools (clang-cpp, ld.lld, llvm-ar, llvm-nm, llvm-objcopy and
llvm-readelf).
Tested with Clang built from the master branch of [1] (development
version for 9.0):
mkdir build; cd build
cmake -G Ninja -DCMAKE_BUILD_TYPE=Release \
-DCMAKE_INSTALL_PREFIX=~/llvm-install \
-DLLVM_ENABLE_PROJECTS="clang;lld" \
-DLLVM_TARGETS_TO_BUILD="AArch64;ARM" \
~/llvm-project/llvm
ninja && ninja install
Limitations:
- CFG_CORE_SANITIZE_KADDRESS=y is not supported.
- CFG_WITH_PAGER is supported, but requires that the TEE core be
linked with the GNU linker. The reason is documented in
mk/clang.mk.
Bug:
- ldelf assertion failure in xtest 1019 when CFG_ULIBS_SHARED=y (QEMU)
E/LD: assertion 'maps[map_idx].sz == sz' failed at ldelf/ta_elf.c:1114 in ta_elf_print_mappings()
Prevents ldelf from displaying the TA mappings on abort or panic, but
does not seem to cause any other problem.
Link: [1] https://github.com/llvm/llvm-project/commits/8351c327647
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Tested-by: Jerome Forissier <jerome@forissier.org> (QEMU pager/no pager)
Tested-by: Jerome Forissier <jerome@forissier.org> (QEMUv8, pager/no pager)
Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey960, 32/64, GP)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 179c8fe8 | 26-Mar-2019 |
Volodymyr Babchuk <vlad.babchuk@gmail.com> |
plat/rcar: fix core numbering for M3 flavor
R-car Gen3 SoCs have consistent core numbering across all
variations: CA57 cluster have core numbers 0-3 and CA53 have
numbers 4-7.
M3 flavor have 6 core
plat/rcar: fix core numbering for M3 flavor
R-car Gen3 SoCs have consistent core numbering across all
variations: CA57 cluster have core numbers 0-3 and CA53 have
numbers 4-7.
M3 flavor have 6 cores: two CA57s and four CA53s. Taking
into account consistent numbering, M3 will have the following
core ids: 0, 1, 3, 5, 6, 7. To fix this, we need to set
CFG_CORE_CLUSTER_SHIFT to 1.
This somewhat abuses implementation of get_core_pos_mpidr(),
but it is not expected, that it will change in the future.
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 8744ddb3 | 26-Sep-2019 |
Jerome Forissier <jerome@forissier.org> |
Revert "hikey: increase core heap size to 192 kB"
This reverts commit 28c75dbebc49 ("hikey: increase core heap size to
192 kB") which increased the core heap size in order to pass the AOSP
VTS. Unfo
Revert "hikey: increase core heap size to 192 kB"
This reverts commit 28c75dbebc49 ("hikey: increase core heap size to
192 kB") which increased the core heap size in order to pass the AOSP
VTS. Unfortunately, this bigger value does not work well when the pager
is enabled: it causes lots of page faults and a massive slowdown (for
instance, 'xtest 1013' on HiKey620 completes in ~ 1.7 s with the
default heap size of 64 kB but takes ~ 53 s with 192 kB).
Therefore, revert to the previous configuration. A bigger value can
always be set on the command line or by other means when building for
AOSP.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 28c75dbe | 17-Sep-2019 |
Victor Chong <victor.chong@linaro.org> |
hikey: increase core heap size to 192 kB
To pass VTS in AOSP builds.
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org> |
| 6e9e277f | 13-Sep-2019 |
Jerome Forissier <jerome@forissier.org> |
core: move sockets PTA to core/tee
The sockets pseudo-TA is architecture-independent. Move it to
core/tee and drop the pta_ prefix which is not really useful.
Signed-off-by: Jerome Forissier <jerom
core: move sockets PTA to core/tee
The sockets pseudo-TA is architecture-independent. Move it to
core/tee and drop the pta_ prefix which is not really useful.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 5843bb75 | 13-Sep-2019 |
Jerome Forissier <jerome@forissier.org> |
core: move PTAs from core/arch/arm/pta to core/pta
All pseudo-TAs in core/arch/arm/pta are not architecture-
specific so move them out of the arch directory.
sdp_pta.c is renamed sdp.c since _pta i
core: move PTAs from core/arch/arm/pta to core/pta
All pseudo-TAs in core/arch/arm/pta are not architecture-
specific so move them out of the arch directory.
sdp_pta.c is renamed sdp.c since _pta is redundant.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 963051aa | 13-Sep-2019 |
Jerome Forissier <jerome@forissier.org> |
core: move test PTAs to core/pta/tests
Moves the test PTAs out of the arch-dependent tree into core/pta/tests.
File names are shortened a bit since the full paths make the purpose
clear.
Signed-off
core: move test PTAs to core/pta/tests
Moves the test PTAs out of the arch-dependent tree into core/pta/tests.
File names are shortened a bit since the full paths make the purpose
clear.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 4b054074 | 13-Sep-2019 |
Jerome Forissier <jerome@forissier.org> |
core: pta/gprof.c: remove <arm.h> include
The gprof pseudo-TA does not need <arm.h> so remove it.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@
core: pta/gprof.c: remove <arm.h> include
The gprof pseudo-TA does not need <arm.h> so remove it.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 27e19499 | 10-Sep-2019 |
Jerome Forissier <jerome@forissier.org> |
core: ltc: force alignment of A32 assembler functions to 4 bytes
The Clang assembler will not align all the functions containing A32
code (as opposed to thumb) on 4-byte boundaries, contrary to GCC.
core: ltc: force alignment of A32 assembler functions to 4 bytes
The Clang assembler will not align all the functions containing A32
code (as opposed to thumb) on 4-byte boundaries, contrary to GCC.
This can cause a runtime exception (undef-abort).
Add a ".balign 4" to the ENTRY macro to fix that.
See also commit ff7c2da6d14b ("Force alignment of assembler functions
(FUNC and LOCAL_FUNC) to 4 bytes") [1].
Link: [1] https://github.com/OP-TEE/optee_os/commit/ff7c2da6d14b
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|