plat-vexpress: add QEMU sbsa-ref platform

Add support for the QEMU sbsa-ref platform. This platform is similar to
the QEMU virt platform, but with different memory configuration and
device addresses

plat-vexpress: add QEMU sbsa-ref platform

Add support for the QEMU sbsa-ref platform. This platform is similar to
the QEMU virt platform, but with different memory configuration and
device addresses.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: qemu-v8: fix CFG_CORE_CLUSTER_SHIFT

QEMU virt puts 8 or 16 CPUs in each cluster, depending on the GIC
configuration [1]. So set CFG_CORE_CLUSTER_SHIFT to match the GIC
configuration t

plat-vexpress: qemu-v8: fix CFG_CORE_CLUSTER_SHIFT

QEMU virt puts 8 or 16 CPUs in each cluster, depending on the GIC
configuration [1]. So set CFG_CORE_CLUSTER_SHIFT to match the GIC
configuration to calculate core position correctly for more than 16
CPUs.

Link: https://gitlab.com/qemu-project/qemu/-/blob/v10.0.0/hw/arm/virt.c?ref_type=tags#L1785-1789 [1]
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)

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core: panic: allow core halting on SGI in other cases than panic()

There may be cases where we want to halt several cores outside of a
panic() sequence.

Therefore, add CFG_MULTI_CORE_HALTING switch

core: panic: allow core halting on SGI in other cases than panic()

There may be cases where we want to halt several cores outside of a
panic() sequence.

Therefore, add CFG_MULTI_CORE_HALTING switch that allows to register
an interrupt handler for the CFG_HALT_CORES_SGI that is dedicated to
halt other cores.

This reduces the scope of CFG_HALT_CORES_ON_PANIC that is now used only
for halting other cores in a panic() sequence.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: qemu_v8: support EL1 physical timer interrupt

Add support to configure the timer callout service based on interrupt
from the EL1 physical timer when configuration with SPMC at S-EL2
(

plat-vexpress: qemu_v8: support EL1 physical timer interrupt

Add support to configure the timer callout service based on interrupt
from the EL1 physical timer when configuration with SPMC at S-EL2
(CFG_CORE_SEL2_SPMC=y).

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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vexpress-qemu_armv8a: increase CFG_CORE_TZSRAM_EMUL_SIZE

Increase the emulated TrustZone SRAM size from 512 to 640 KB for the
vexpress-qemu_armv8a. This drastically improves the execution speed when

vexpress-qemu_armv8a: increase CFG_CORE_TZSRAM_EMUL_SIZE

Increase the emulated TrustZone SRAM size from 512 to 640 KB for the
vexpress-qemu_armv8a. This drastically improves the execution speed when
pager is enabled. For example, without this change the command
"time xtest regression_1006" takes around 3 minutes on my build machine,
but it takes only 9 seconds with the increased TZSRAM. Similarly, the
same test on the GitHub CI runners needs 10 minutes before the change
and only 15 seconds after.

This is related to commit 46fdfeea761f ("vexpress-qemu_armv8a: increase
CFG_CORE_HEAP_SIZE to 131072") and commit b4ed37a8c754 ("plat-vexpress:
increase QEMU heap size") which effectively took away 64K + 64KB from
the pager.

This is expected to solve the occasional timeouts that we see occurring
with the QEMUv8_check1 CI job.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: increase QEMU heap size

The core heap usage is increased by around 20kB with fTPM enabled so it
makes sense if this has to be compensated.

Increase heap size for the QEMU variants:
-

plat-vexpress: increase QEMU heap size

The core heap usage is increased by around 20kB with fTPM enabled so it
makes sense if this has to be compensated.

Increase heap size for the QEMU variants:
- QEMU v7 from 64kB to 96kB
- QEMU v8 from 128kB to 192kB

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-vexpress: conf: default enable CFG_PKCS11_TA_RSA_X_509

Default enable PKCS#11 TA config switch CFG_PKCS11_TA_RSA_X_509 to
embed this feature in the TA test environment. Raw RSA is no more
a rec

plat-vexpress: conf: default enable CFG_PKCS11_TA_RSA_X_509

Default enable PKCS#11 TA config switch CFG_PKCS11_TA_RSA_X_509 to
embed this feature in the TA test environment. Raw RSA is no more
a recommended feature but can be required for some TLS v1.2
feature support. Therefore CFG_PKCS11_TA_RSA_X_509 has been disable
in PKCS#11 TA default configuration but should still be supported
hence we enable it in vexpress platforms that are intended to
test and development environments.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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vexpress-qemu_armv8a: increase CFG_CORE_TZSRAM_EMUL_SIZE to 512 kB

Set the default emulated SRAM to 512 kB since the default 448 kB isn't
enough to build with CFG_CORE_ASLR=y with a margin.

Signed-

vexpress-qemu_armv8a: increase CFG_CORE_TZSRAM_EMUL_SIZE to 512 kB

Set the default emulated SRAM to 512 kB since the default 448 kB isn't
enough to build with CFG_CORE_ASLR=y with a margin.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: bottom half uart driver with non-secure virtualization

Enable the bottom half uart driver with FF-A and non-secure
virtualization enabled.

The console struct itr_handler and struct n

plat-vexpress: bottom half uart driver with non-secure virtualization

Enable the bottom half uart driver with FF-A and non-secure
virtualization enabled.

The console struct itr_handler and struct notif_driver are moved into
nexus memory as needed.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core/scmi: export sub.mk files in SCP-firmware

In order to ease the update of makefile when C or Header files of
SCP-firmware project changes, we integrate them in the optee subdirectory
of SCP-firm

core/scmi: export sub.mk files in SCP-firmware

In order to ease the update of makefile when C or Header files of
SCP-firmware project changes, we integrate them in the optee subdirectory
of SCP-firmware.

sub-optee-fvp.mk and sub-optee-stm32mp1.mk are moved unchanged in their
product directories of SCP-repository.

scmi-server/sub.mk is split:
- macro and compilation flags stay in optee-os
- srcs and incdirs are moved in product/optee directory

All modules and products related to optee are located in the
product/optee directory in the SCP-firmware repository, adding an "optee-"
prefix in the product name is useless. Remove it.

the ci will temporary point to the sha1 of the merged MR branch of
SCP-firmware. This will be replaced with next SCP-firmware tag v2.15.0
once released.

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: Add FFA_CONSOLE based console driver for log

This console driver uses FFA_CONSOLE ABI to write the trace logs.

If CFG_FFA_CONSOLE is enabled, OP-TEE will try to initialize the console
driv

drivers: Add FFA_CONSOLE based console driver for log

This console driver uses FFA_CONSOLE ABI to write the trace logs.

If CFG_FFA_CONSOLE is enabled, OP-TEE will try to initialize the console
driver that uses FFA interface to print trace logs.

Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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vexpress-qemu_armv8a: increase CFG_CORE_HEAP_SIZE to 131072

Set the default core heap size for QEMUv8 to 128K because 64K is not
enough to complete the "make check" test with CFG_RPMB_FS=y
CFG_RPMB_

vexpress-qemu_armv8a: increase CFG_CORE_HEAP_SIZE to 131072

Set the default core heap size for QEMUv8 to 128K because 64K is not
enough to complete the "make check" test with CFG_RPMB_FS=y
CFG_RPMB_WRITE_KEY=y.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add CFG_CALLOUT

Add CFG_CALLOUT with a default value assigned from CFG_CORE_ASYNC_NOTIF
to control if the callout service should be enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@lina

core: add CFG_CALLOUT

Add CFG_CALLOUT with a default value assigned from CFG_CORE_ASYNC_NOTIF
to control if the callout service should be enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMER

Define the interrupt ID of the secure physical timer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome

plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMER

Define the interrupt ID of the secure physical timer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: initialize callout service

If physical timer interrupt is defined, IT_SEC_PHY_TIMER, and OP-TEE
isn't virtualized, CFG_CORE_SEL2_SPMC isn't defined, initialize the
callout service usi

plat-vexpress: initialize callout service

If physical timer interrupt is defined, IT_SEC_PHY_TIMER, and OP-TEE
isn't virtualized, CFG_CORE_SEL2_SPMC isn't defined, initialize the
callout service using that interrupt ID.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: disable PL011-specific code when CFG_SEMIHOSTING_CONSOLE=y

When the semihosting console is enabled (with CFG_SEMIHOSTING=y
CFG_SEMIHOSTING_CONSOLE=y) then some code in plat-vexpress/m

plat-vexpress: disable PL011-specific code when CFG_SEMIHOSTING_CONSOLE=y

When the semihosting console is enabled (with CFG_SEMIHOSTING=y
CFG_SEMIHOSTING_CONSOLE=y) then some code in plat-vexpress/main.c
doesn't make sense and needs to be disabled.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console

core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console drivers (e.g., semihosting console).

If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: use serial callbacks rx_intr_{en,dis}able()

Use the serial callbacks rx_intr_enable() and rx_intr_disable() to
enable and disable interrupts from the console.

Signed-off-by: Jens Wik

plat-vexpress: use serial callbacks rx_intr_{en,dis}able()

Use the serial callbacks rx_intr_enable() and rx_intr_disable() to
enable and disable interrupts from the console.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-vexpress: remove unnecessary includes

Remove unnecessary includes.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens

plat-vexpress: remove unnecessary includes

Remove unnecessary includes.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: configure CFG_CORE_ASYNC_NOTIF_GIC_INTID

When compiled for SPMC at S-EL1 (CFG_CORE_SEL1_SPMC=y), configure
CFG_CORE_ASYNC_NOTIF_GIC_INTID to an unused secure SGI that can be
donated t

plat-vexpress: configure CFG_CORE_ASYNC_NOTIF_GIC_INTID

When compiled for SPMC at S-EL1 (CFG_CORE_SEL1_SPMC=y), configure
CFG_CORE_ASYNC_NOTIF_GIC_INTID to an unused secure SGI that can be
donated to the normal world.

In boot_primary_init_intc(), only donate the interrupt id if it's in the
predefined secure SGI range.

Fixes: 462028ede02d ("qemu_armv8a: add GIC v3 redistributor base address")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: fvp: configure GIC redistributor base address

Configure GIC redistributor base address needed with GICv3.

Fixes: 462028ede02d ("qemu_armv8a: add GIC v3 redistributor base address")
S

plat-vexpress: fvp: configure GIC redistributor base address

Configure GIC redistributor base address needed with GICv3.

Fixes: 462028ede02d ("qemu_armv8a: add GIC v3 redistributor base address")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: use CFG_AUTO_MAX_PA_BITS on virtual platforms

By default set CFG_AUTO_MAX_PA_BITS=y on the virtual platforms fvp and
qemu_armv8a to allow automatic configuration of the maximal suppor

plat-vexpress: use CFG_AUTO_MAX_PA_BITS on virtual platforms

By default set CFG_AUTO_MAX_PA_BITS=y on the virtual platforms fvp and
qemu_armv8a to allow automatic configuration of the maximal supported
physical address.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: donate a secure SGI to normal world

With OP-TEE acting as SPMC in S-EL1 donate a secure SGI to normal world
to be used to signal asynchronous notifications for FF-A.

Signed-off-by: J

plat-vexpress: donate a secure SGI to normal world

With OP-TEE acting as SPMC in S-EL1 donate a secure SGI to normal world
to be used to signal asynchronous notifications for FF-A.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: use gic_init_per_cpu()

Calls gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere

plat-vexpress: use gic_init_per_cpu()

Calls gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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qemu_armv8a: add GIC v3 redistributor base address

Adds and configures the GIC v3 redistributor base address.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <e

qemu_armv8a: add GIC v3 redistributor base address

Adds and configures the GIC v3 redistributor base address.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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