1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2020, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/hfic.h> 11 #include <drivers/pl011.h> 12 #include <drivers/tzc400.h> 13 #include <initcall.h> 14 #include <keep.h> 15 #include <kernel/boot.h> 16 #include <kernel/interrupt.h> 17 #include <kernel/misc.h> 18 #include <kernel/notif.h> 19 #include <kernel/panic.h> 20 #include <kernel/spinlock.h> 21 #include <kernel/tee_time.h> 22 #include <mm/core_memprot.h> 23 #include <mm/core_mmu.h> 24 #include <platform_config.h> 25 #include <sm/psci.h> 26 #include <stdint.h> 27 #include <string.h> 28 #include <trace.h> 29 30 static struct pl011_data console_data __nex_bss; 31 32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 33 #if defined(PLATFORM_FLAVOR_fvp) 34 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 35 #endif 36 #if defined(PLATFORM_FLAVOR_qemu_virt) 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 38 #endif 39 #ifdef DRAM0_BASE 40 register_ddr(DRAM0_BASE, DRAM0_SIZE); 41 #endif 42 #ifdef DRAM1_BASE 43 register_ddr(DRAM1_BASE, DRAM1_SIZE); 44 #endif 45 46 #ifdef CFG_GIC 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 49 #ifdef GIC_REDIST_BASE 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_REDIST_BASE, GIC_REDIST_SIZE); 51 #endif 52 53 void boot_primary_init_intc(void) 54 { 55 #ifdef GIC_REDIST_BASE 56 gic_init_v3(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET, 57 GIC_REDIST_BASE); 58 #else 59 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 60 #endif 61 } 62 63 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 64 void boot_secondary_init_intc(void) 65 { 66 gic_cpu_init(); 67 } 68 #endif 69 #endif /*CFG_GIC*/ 70 71 #ifdef CFG_CORE_HAFNIUM_INTC 72 void boot_primary_init_intc(void) 73 { 74 hfic_init(); 75 } 76 #endif 77 78 void console_init(void) 79 { 80 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 81 CONSOLE_BAUDRATE); 82 register_serial_console(&console_data.chip); 83 } 84 85 #if (defined(CFG_GIC) || defined(CFG_CORE_HAFNIUM_INTC)) && \ 86 defined(IT_CONSOLE_UART) && \ 87 !defined(CFG_NS_VIRTUALIZATION) && \ 88 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 89 /* 90 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 91 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 92 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 93 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 94 * will hang in EL3 since the interrupt will just be delivered again and 95 * again. 96 */ 97 98 static void read_console(void) 99 { 100 struct serial_chip *cons = &console_data.chip; 101 102 if (!cons->ops->getchar || !cons->ops->have_rx_data) 103 return; 104 105 while (cons->ops->have_rx_data(cons)) { 106 int ch __maybe_unused = cons->ops->getchar(cons); 107 108 DMSG("got 0x%x", ch); 109 } 110 } 111 112 static enum itr_return console_itr_cb(struct itr_handler *hdl) 113 { 114 if (notif_async_is_started()) { 115 /* 116 * Asynchronous notifications are enabled, lets read from 117 * uart in the bottom half instead. 118 */ 119 interrupt_disable(hdl->chip, hdl->it); 120 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 121 } else { 122 read_console(); 123 } 124 return ITRR_HANDLED; 125 } 126 127 static struct itr_handler console_itr = { 128 .it = IT_CONSOLE_UART, 129 .flags = ITRF_TRIGGER_LEVEL, 130 .handler = console_itr_cb, 131 }; 132 DECLARE_KEEP_PAGER(console_itr); 133 134 static void atomic_console_notif(struct notif_driver *ndrv __unused, 135 enum notif_event ev __maybe_unused) 136 { 137 DMSG("Asynchronous notifications started, event %d", (int)ev); 138 } 139 DECLARE_KEEP_PAGER(atomic_console_notif); 140 141 static void yielding_console_notif(struct notif_driver *ndrv __unused, 142 enum notif_event ev) 143 { 144 switch (ev) { 145 case NOTIF_EVENT_DO_BOTTOM_HALF: 146 read_console(); 147 interrupt_enable(console_itr.chip, console_itr.it); 148 break; 149 case NOTIF_EVENT_STOPPED: 150 DMSG("Asynchronous notifications stopped"); 151 interrupt_enable(console_itr.chip, console_itr.it); 152 break; 153 default: 154 EMSG("Unknown event %d", (int)ev); 155 } 156 } 157 158 struct notif_driver console_notif = { 159 .atomic_cb = atomic_console_notif, 160 .yielding_cb = yielding_console_notif, 161 }; 162 163 static TEE_Result init_console_itr(void) 164 { 165 TEE_Result res = TEE_ERROR_GENERIC; 166 167 res = interrupt_add_handler_with_chip(interrupt_get_main_chip(), 168 &console_itr); 169 if (res) 170 return res; 171 172 interrupt_enable(console_itr.chip, console_itr.it); 173 174 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) 175 notif_register_driver(&console_notif); 176 return TEE_SUCCESS; 177 } 178 driver_init(init_console_itr); 179 #endif 180 181 #ifdef CFG_TZC400 182 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 183 184 static TEE_Result init_tzc400(void) 185 { 186 void *va; 187 188 DMSG("Initializing TZC400"); 189 190 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 191 if (!va) { 192 EMSG("TZC400 not mapped"); 193 panic(); 194 } 195 196 tzc_init((vaddr_t)va); 197 tzc_dump_state(); 198 199 return TEE_SUCCESS; 200 } 201 202 service_init(init_tzc400); 203 #endif /*CFG_TZC400*/ 204 205 #if defined(PLATFORM_FLAVOR_qemu_virt) 206 static void release_secondary_early_hpen(size_t pos) 207 { 208 struct mailbox { 209 uint64_t ep; 210 uint64_t hpen[]; 211 } *mailbox; 212 213 if (cpu_mmu_enabled()) 214 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 215 SECRAM_COHERENT_SIZE); 216 else 217 mailbox = (void *)SECRAM_BASE; 218 219 if (!mailbox) 220 panic(); 221 222 mailbox->ep = TEE_LOAD_ADDR; 223 dsb_ishst(); 224 mailbox->hpen[pos] = 1; 225 dsb_ishst(); 226 sev(); 227 } 228 229 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 230 { 231 size_t pos = get_core_pos_mpidr(core_id); 232 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 233 234 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 235 return PSCI_RET_INVALID_PARAMETERS; 236 237 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 238 239 if (core_is_released[pos]) { 240 EMSG("core %zu already released", pos); 241 return PSCI_RET_DENIED; 242 } 243 core_is_released[pos] = true; 244 245 boot_set_core_ns_entry(pos, entry, context_id); 246 release_secondary_early_hpen(pos); 247 248 return PSCI_RET_SUCCESS; 249 } 250 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 251