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Searched refs:__BIT6 (Results 1 – 25 of 101) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DregHWI2C.h150 #define CHIP_REG_HWI2C_MIIC1_CLK_XTAL (__BIT6)
152 #define CHIP_REG_HWI2C_MIIC1_CLK_54M (__BIT6 | __BIT7)
153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
175 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
220 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
258 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
303 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DregHWI2C.h150 #define CHIP_REG_HWI2C_MIIC1_CLK_XTAL (__BIT6)
152 #define CHIP_REG_HWI2C_MIIC1_CLK_54M (__BIT6 | __BIT7)
153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
175 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
220 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
258 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
303 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DregHWI2C.h150 #define CHIP_REG_HWI2C_MIIC1_CLK_XTAL (__BIT6)
152 #define CHIP_REG_HWI2C_MIIC1_CLK_54M (__BIT6 | __BIT7)
153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
175 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
220 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
258 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
303 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DregHWI2C.h150 #define CHIP_REG_HWI2C_MIIC1_CLK_XTAL (__BIT6)
152 #define CHIP_REG_HWI2C_MIIC1_CLK_54M (__BIT6 | __BIT7)
153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
175 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
220 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
258 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
303 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregEMMflt.h112 #define __BIT6 __BIT(6) macro
232 #define EMM_SKIP_ADDR_EN __BIT6
256 #define REG_PKT192_EN __BIT6
272 #define REG_EXT_SYNC_SEL2 __BIT6
H A DregNSK2.h112 #define __BIT6 __BIT(6) macro
162 #define NSK2_INT_KTE_VALID __BIT6
276 #define NI_CLOCK_HALT_DETECT __BIT6
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DregEMMflt.h112 #define __BIT6 __BIT(6) macro
232 #define EMM_SKIP_ADDR_EN __BIT6
256 #define REG_PKT192_EN __BIT6
272 #define REG_EXT_SYNC_SEL2 __BIT6
H A DregNSK2.h112 #define __BIT6 __BIT(6) macro
160 #define NSK2_INT_KTE_VALID __BIT6
271 #define NI_CLOCK_HALT_DETECT __BIT6
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregEMMflt.h112 #define __BIT6 __BIT(6) macro
232 #define EMM_SKIP_ADDR_EN __BIT6
256 #define REG_PKT192_EN __BIT6
272 #define REG_EXT_SYNC_SEL2 __BIT6
H A DregNSK2.h112 #define __BIT6 __BIT(6) macro
162 #define NSK2_INT_KTE_VALID __BIT6
276 #define NI_CLOCK_HALT_DETECT __BIT6
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregEMMflt.h112 #define __BIT6 __BIT(6) macro
232 #define EMM_SKIP_ADDR_EN __BIT6
256 #define REG_PKT192_EN __BIT6
272 #define REG_EXT_SYNC_SEL2 __BIT6
H A DregNSK2.h112 #define __BIT6 __BIT(6) macro
162 #define NSK2_INT_KTE_VALID __BIT6
276 #define NI_CLOCK_HALT_DETECT __BIT6
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregEMMflt.h112 #define __BIT6 __BIT(6) macro
232 #define EMM_SKIP_ADDR_EN __BIT6
256 #define REG_PKT192_EN __BIT6
272 #define REG_EXT_SYNC_SEL2 __BIT6
H A DregNSK2.h112 #define __BIT6 __BIT(6) macro
161 #define NSK2_INT_KTE_VALID __BIT6
275 #define NI_CLOCK_HALT_DETECT __BIT6
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h172 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
215 #define _ADV_CLK_STRETCH_OEN (__BIT6)
236 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h172 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
215 #define _ADV_CLK_STRETCH_OEN (__BIT6)
236 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DregHWI2C.h172 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
215 #define _ADV_CLK_STRETCH_OEN (__BIT6)
236 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DregHWI2C.h172 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
215 #define _ADV_CLK_STRETCH_OEN (__BIT6)
236 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DregHWI2C.h172 #define _MIIC_CFG_EN_PUSH1T (__BIT6)
215 #define _ADV_CLK_STRETCH_OEN (__BIT6)
236 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/ir_tx/hal/k6lite/ir_tx/
H A Dreg_IR_TX.h8 #define __BIT6 __BIT(6UL) macro
113 #define IR_TX_Unit03_H __BIT6
130 #define IR_TX_Unit11_H __BIT6
/utopia/UTPA2-700.0.x/modules/pm/hal/curry/pm/
H A DregPM.h112 #define __BIT6 __BIT(6) macro
127 #define CHIP_CFG_MIPS_VAL __BIT6
/utopia/UTPA2-700.0.x/modules/pm/hal/kano/pm/
H A DregPM.h112 #define __BIT6 __BIT(6) macro
128 #define CHIP_CFG_MIPS_VAL __BIT6
/utopia/UTPA2-700.0.x/modules/pm/hal/k6/pm/
H A DregPM.h112 #define __BIT6 __BIT(6) macro
128 #define CHIP_CFG_MIPS_VAL __BIT6
/utopia/UTPA2-700.0.x/modules/pm/hal/k6lite/pm/
H A DregPM.h112 #define __BIT6 __BIT(6) macro
128 #define CHIP_CFG_MIPS_VAL __BIT6
/utopia/UTPA2-700.0.x/modules/pm/hal/manhattan/pm/
H A DregPM.h112 #define __BIT6 __BIT(6) macro
131 #define CHIP_CFG_MIPS_VAL __BIT6

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