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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 //////////////////////////////////////////////////////////////////////////////// 93 94 #ifndef _REGNSK2_H_ 95 #define _REGNSK2_H_ 96 97 //////////////////////////////////////////////////////////////////////////////// 98 // Header Files 99 //////////////////////////////////////////////////////////////////////////////// 100 101 //////////////////////////////////////////////////////////////////////////////// 102 // Define & data type 103 //////////////////////////////////////////////////////////////////////////////// 104 //v: value n: shift n bits 105 #define __BIT(x) ((MS_U32)(1 << (x))) 106 #define __BIT0 __BIT(0) 107 #define __BIT1 __BIT(1) 108 #define __BIT2 __BIT(2) 109 #define __BIT3 __BIT(3) 110 #define __BIT4 __BIT(4) 111 #define __BIT5 __BIT(5) 112 #define __BIT6 __BIT(6) 113 #define __BIT7 __BIT(7) 114 #define __BIT8 __BIT(8) 115 #define __BIT9 __BIT(9) 116 #define __BITA __BIT(0xA) 117 #define __BITB __BIT(0xB) 118 #define __BITC __BIT(0xC) 119 #define __BITD __BIT(0xD) 120 #define __BITE __BIT(0xE) 121 #define __BITF __BIT(0xF) 122 123 #define __BIT21 __BIT(21) 124 #define __BIT31 __BIT(31) 125 126 //#define BMASK(_bits_) (__BIT(((1)?_bits_)+1)-__BIT(((0)?_bits_))) 127 128 #define BYTE0 0xFF 129 #define BYTE1 (0xFF<<8) 130 #define BYTE0_MASK 0x00FF 131 #define BYTE1_MASK 0xFF00 132 133 134 #define REG_CLKGEN0_BASE (0x100B00<<1) 135 #define REG_NSK2_BASE (0x180000<<1) 136 #define REG_OTP_BASE (0x190000<<1) 137 #define REG_OTP_CTRL_BASE (0x1A1300<<1) 138 #define REG_NI_BASE (0x1A1800<<1) 139 #define REG_RSA_BASE (0x1A1200<<1) 140 141 #define REG_KEY_TABLE_BASE (0x1A0C00<<1) 142 #define REG_JTAG_PWD_BASE (0x170300<<1) //check!! 143 #define REG_CIPHER_CH0_BASE (0x1A0700<<1) 144 145 #define REG_CRYPTO_DMA_BASE (0x1A0B00<<1) //x32_CryptoDMA0 146 147 148 #define REG_NSK2_ACPU_CMD 0xFC00 149 #define NSK2_ACPU_CMD 0xFF 150 151 #define REG_NSK2_ACPU_WARNING 0xFC04 152 #define NSK2_ACPU_BUSY __BIT31 153 154 #define REG_NSK2_ACPU_INT 0xFC08 155 #define NSK2_INT_CMD_EXIT __BIT0 156 #define NSK2_INT_ASYNC_EVENT __BIT1 157 #define NSK2_INT_ILLEGAL_CMD __BIT2 158 #define NSK2_INT_ILLEGAL_ACCESS __BIT3 159 #define NSK2_INT_RESET __BIT4 160 #define NSK2_INT_HANG __BIT5 161 #define NSK2_INT_KTE_VALID __BIT6 162 #define NSK2_INT_MASK_CLEAR __BIT31 163 164 165 #define REG_NSK2_ACPU_CTRL_BLOCK 0xFC0C 166 167 168 #define REG_NSK2_ACPU_ERROR 0xFC10 169 170 #define REG_NSK2_KTE_SWITCH_1 0xFC40 171 #define REG_NSK2_KTE_SWITCH_2 0xFC44 172 #define REG_NSK2_KTE_SWITCH_3 0xFC48 173 174 #define REG_NSK2_KTE_VALID 0xFC4C 175 #define NSK2_KTE_VALID_TRUE __BIT0 176 177 #define REG_NSK2_GENOUT_LOW 0xFC50 178 179 #define REG_NSK2_VEN_VERSION 0xFC70 180 181 #define REG_NSK2_GENOUT_HIGH 0xFDFC 182 183 184 #define REG_NI_NSK2_CTRL 0x0 185 #define NI_TS2NSK_ENABLE 0x1 186 #define NI_TS2NSK_RATE BMASK(3:1) 187 #define NI_TEST_RC_FREQ_MAP BMASK(7:4) 188 #define NI_N2ROM_PD __BIT8 189 #define NI_NO_RST_DELAY __BITD 190 #define NI_NSK2_CLK_ENABLE __BITE 191 #define NI_NSK2_RESET_DISABLE __BITF 192 193 #define REG_NI_NSK2_FREERUN 0x1 194 #define NI_NSK2_FREERUN_ENABLE __BIT2 195 #define NI_NSK2_RANDOM_FREERUN __BIT4 196 #define NI_NSK2_RANDOM_ONEBYONE __BIT5 197 198 #define REG_NI_SW_SET_RNG 0x5 199 #define NI_SW_RNG_MASK BMASK(15:0) 200 201 #define REG_NI_COMMAND 0x6 202 #define NI_COMMAND_START 0x1 203 204 #define NI_KIW_OID_MASK BMASK(3:3) 205 #define NI_KIW_OID_SHIFT 3 206 207 #define NI_KIW_CMD_MASK BMASK(15:8) 208 #define NI_KIW_CMD_SHIFT 8 209 #define NI_NopNop 0x0 210 211 #define NI_OTP_ACK_NSK2 (1<<1) 212 #define NI_ERR_INVALID_SLOT (1<<2) 213 #define NI_NSKBIComplete (1<<NI_KIW_CMD_SHIFT) 214 #define NI_DriveAck (2<<NI_KIW_CMD_SHIFT) 215 #define NI_InvalidateCmChannel (4<<NI_KIW_CMD_SHIFT) 216 #define NI_InvalidateM2M (5<<NI_KIW_CMD_SHIFT) 217 #define NI_ConfigureCmChannel (6<<NI_KIW_CMD_SHIFT) 218 #define NI_WriteTransportKey (8<<NI_KIW_CMD_SHIFT) 219 #define NI_WriteM2MKey (9<<NI_KIW_CMD_SHIFT) 220 #define NI_WriteMDEMKey (10<<NI_KIW_CMD_SHIFT) 221 #define NI_WriteJTAGKey (12<<NI_KIW_CMD_SHIFT) 222 #define NI_WriteSCPUKey (13<<NI_KIW_CMD_SHIFT) 223 #define NI_WriteReservedKey (14<<NI_KIW_CMD_SHIFT) 224 #define NI_WriteRandomValue (15<<NI_KIW_CMD_SHIFT) 225 #define NI_WriteOTPKey (16<<NI_KIW_CMD_SHIFT) 226 #define NI_IncrementNvCounter (17<<NI_KIW_CMD_SHIFT) 227 228 229 #define NI_KIW_PidNo_MASK BMASK(23:16) 230 #define NI_WriteTKey_PidNo_Shift 16 231 #define NI_WriteTransportKey_PidNo BMASK(23:16) 232 #define NI_WriteTKey_SCB_Shift 24 233 #define NI_WriteTKey_SCB_MASK BMASK(25:24) 234 #define NI_WriteTKey_FSCB_Shift 26 235 #define NI_WriteTKey_FSCB_MASK BMASK(27:26) 236 237 #define NI_WriteESA 0x2 238 #define NI_JTAG_PasswordWriteSCPUKey 0x8 239 #define NI_CearWKResp 0xC 240 241 242 #define REG_NI_DSCMB_ALGO 0x7 243 244 #define NI_KIW_LSAD_ALGO_MASK BMASK(4:0) 245 #define NI_KIW_ESA_ALGO_SHIFT 8 246 #define NI_KIW_ESA_ALGO_MASK BMASK(12:8) 247 #define NI_KIW_LSAS_ALGO_SHIFT 16 248 #define NI_KIW_LSAS_ALGO_MASK BMASK(20:16) 249 250 #define NI_WriteESA_PidNo BMASK(7:0) 251 #define NI_WriteESA_ESASubSel_Shift 16 252 #define NI_WriteESA_ESASubSel_MASK BMASK(18:16) 253 #define NI_WriteESA_ESASel_Shift 19 254 #define NI_WriteESA_ESASel_MASK BMASK(22:19) 255 256 #define NI_WriteM2MKey_Shift 16 257 #define NI_WriteM2MKey_MASK BMASK(19:16) 258 259 #define REG_NI_IV_31_00 0x8 260 #define REG_NI_IV_63_31 0x9 261 #define REG_NI_IV_95_64 0xA 262 #define REG_NI_IV_127_96 0xB 263 264 #define REG_NI_STATUS 0xC 265 #define NI_NSK_BUSY __BIT0 266 #define NI_SKB_BUSY __BIT1 267 #define NI_AIW_BUSY __BIT2 268 #define NI_KIW_BUSY __BIT3 269 270 #define REG_NI_KTE_STATUS 0xD 271 #define NI_KTE_DEST_MASK BMASK(2:0) 272 #define NI_KTE_VALID __BIT3 273 #define NI_NSK2_FREQ_OKAY __BIT4 274 #define NI_SLOW_CLOCK_DETECT __BIT5 275 #define NI_CLOCK_HALT_DETECT __BIT6 276 277 #define REG_NI_COMPARE_GENOUT_L 0x17 278 #define NSK2_IS_BUSY __BIT(21) 279 #define NSK2_KTE_DEST BMASK(20:17) 280 #define NSK2_CON_CUR __BIT(16) 281 #define NSK2_CSA2VAR_EN __BIT(15) 282 #define NSK2_CSA3VAR_EN __BIT(14) 283 #define NSK2_CPNR __BIT(1) //Content Protection Not Required 284 #define NSK2_OTPPWD __BIT(0) //OTP Program Password Accepted 285 286 #define REG_NI_COMPARE_GENOUT_H 0x18 287 #define NI_GENOUT_H_MASK BMASK(5:0) 288 289 #define REG_NI_NSK2_TRNG_VALID 0x19 290 #define NI_NSK2_TRNG_VALID_MASK BMASK(0:0) 291 292 #define REG_NI_NSK2_PWD_ON 0x1B 293 #define N2_JTAGPWD0_ON __BIT(0) 294 #define N2_JTAGPWD1_ON __BIT(1) 295 #define N2_SCANPWD_ON __BIT(2) 296 #define N2_MBISTPWD_ON __BIT(3) 297 #define N2_M2MKEY_ON __BIT(4) 298 #define N2_SCPUKEY0_ON __BIT(5) 299 #define N2_SCPUKEY1_ON __BIT(6) 300 #define N2_RNGVALUE0_ON __BIT(8) 301 #define N2_RNGVALUE1_ON __BIT(9) 302 303 304 #define REG_NI_NSK2_TRNG_DATA 0x1A 305 306 #define REG_NI_NSK2_KTE_RESP 0x1C 307 308 309 #define REG_NI_NSK2_CLK_CSA 0x24 310 #define NSK2_PUSH_SLOW_CLK __BIT(0) 311 #define NSK2_EN_CSA_VAR __BIT(4) 312 313 #define REG_KT_KEYS_START_FPGA 0x28 314 #define REG_KT_KEYS_END_FPGA 0x36 315 316 317 #define REG_NI_NSK2_KTE_VALID_FPGA 0x37 318 #define NI_NSK2_KTE_VALID_FPGA __BIT0 319 320 #define REG_NI_NSK21_GENIN 0x40 321 322 #define REG_NI_NSK21_CONCURR_PROT_EN 0x41 323 324 #define REG_NI_NSK21_CONCURR_SET 0x42 325 326 #define REG_NI_NSK21_GEN_SHOT 0x43 327 328 #define REG_NI_NSK2_REG_GENIN 0x44 329 330 #define REG_NI_NSK21_GET_NVCOUNTER 0x78 331 332 #define REG_RSA_CLK_ENABLE 0x1 333 #define RSA_PM_NSKCLK_ENABLE __BIT1 334 335 #define REG_RSA_SECRANGE_START(_a_) (REG_RSA_BASE + (0x05 + (_a_)* 2) * 4 ) //0~5 336 #define REG_RSA_SECRANGE_END(_a_) (REG_RSA_BASE + (0x06 + (_a_)* 2) * 4 ) //0~5 337 #define REG_RSA_SECRANGE_SET 0x6 338 #define REG_RSA_SECRANGE_ENABLE 0xFFFEFFFF 339 #define RSA_SECRANGE_MASK 0x0000FFFF 340 #define REG_RSA_SECRANGE_MASK (REG_RSA_BASE + (0x13 << 2)) 341 342 343 #endif //_REGNSK2_H_ 344 345