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Searched refs:__BIT1 (Results 1 – 25 of 86) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DregHWI2C.h119 #define CHIP_MIIC0_PAD_2 (__BIT1)
120 #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1)
121 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
138 #define REG_HWI2C_MIIC_VER_V3 (__BIT1|__BIT0)
139 #define REG_HWI2C_MIIC_VER_MSK (__BIT1|__BIT0)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
170 #define _MIIC_CFG_EN_DMA (__BIT1)
187 #define _RDATA_CFG_ACKBIT (__BIT1)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
194 #define _INT_STOPDET (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DregHWI2C.h119 #define CHIP_MIIC0_PAD_2 (__BIT1)
120 #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1)
121 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
138 #define REG_HWI2C_MIIC_VER_V3 (__BIT1|__BIT0)
139 #define REG_HWI2C_MIIC_VER_MSK (__BIT1|__BIT0)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
170 #define _MIIC_CFG_EN_DMA (__BIT1)
187 #define _RDATA_CFG_ACKBIT (__BIT1)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
194 #define _INT_STOPDET (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DregHWI2C.h119 #define CHIP_MIIC0_PAD_2 (__BIT1)
120 #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1)
121 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
138 #define REG_HWI2C_MIIC_VER_V3 (__BIT1|__BIT0)
139 #define REG_HWI2C_MIIC_VER_MSK (__BIT1|__BIT0)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
170 #define _MIIC_CFG_EN_DMA (__BIT1)
187 #define _RDATA_CFG_ACKBIT (__BIT1)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
194 #define _INT_STOPDET (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DregHWI2C.h119 #define CHIP_MIIC0_PAD_2 (__BIT1)
120 #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1)
121 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
138 #define REG_HWI2C_MIIC_VER_V3 (__BIT1|__BIT0)
139 #define REG_HWI2C_MIIC_VER_MSK (__BIT1|__BIT0)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
170 #define _MIIC_CFG_EN_DMA (__BIT1)
187 #define _RDATA_CFG_ACKBIT (__BIT1)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
194 #define _INT_STOPDET (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h121 #define CHIP_MIIC1_PAD_1 (__BIT1)
122 #define CHIP_MIIC1_PAD_MSK (__BIT1)
133 #define CHIP_DDCR_PAD_1 (__BIT1)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
138 #define CHIP_MIIC3_PAD_1 (__BIT1)
139 #define CHIP_MIIC3_PAD_MSK (__BIT1|__BIT2)
150 #define CHIP_MIIC5_PAD_1 (__BIT1) //PAD_GPIO32/PAD_GPIO33
151 #define CHIP_MIIC5_PAD_MSK (__BIT1)
167 #define _MIIC_CFG_EN_DMA (__BIT1)
184 #define _RDATA_CFG_ACKBIT (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DregHWI2C.h121 #define CHIP_MIIC1_PAD_1 (__BIT1)
122 #define CHIP_MIIC1_PAD_MSK (__BIT1)
133 #define CHIP_DDCR_PAD_1 (__BIT1)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
138 #define CHIP_MIIC3_PAD_1 (__BIT1)
139 #define CHIP_MIIC3_PAD_MSK (__BIT1|__BIT2)
150 #define CHIP_MIIC5_PAD_1 (__BIT1) //PAD_GPIO32/PAD_GPIO33
151 #define CHIP_MIIC5_PAD_MSK (__BIT1)
167 #define _MIIC_CFG_EN_DMA (__BIT1)
184 #define _RDATA_CFG_ACKBIT (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DregHWI2C.h121 #define CHIP_MIIC1_PAD_1 (__BIT1)
122 #define CHIP_MIIC1_PAD_MSK (__BIT1)
133 #define CHIP_DDCR_PAD_1 (__BIT1)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
138 #define CHIP_MIIC3_PAD_1 (__BIT1)
139 #define CHIP_MIIC3_PAD_MSK (__BIT1|__BIT2)
150 #define CHIP_MIIC5_PAD_1 (__BIT1) //PAD_GPIO32/PAD_GPIO33
151 #define CHIP_MIIC5_PAD_MSK (__BIT1)
167 #define _MIIC_CFG_EN_DMA (__BIT1)
184 #define _RDATA_CFG_ACKBIT (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DregHWI2C.h121 #define CHIP_MIIC1_PAD_1 (__BIT1)
122 #define CHIP_MIIC1_PAD_MSK (__BIT1)
133 #define CHIP_DDCR_PAD_1 (__BIT1)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
138 #define CHIP_MIIC3_PAD_1 (__BIT1)
139 #define CHIP_MIIC3_PAD_MSK (__BIT1|__BIT2)
150 #define CHIP_MIIC5_PAD_1 (__BIT1) //PAD_GPIO32/PAD_GPIO33
151 #define CHIP_MIIC5_PAD_MSK (__BIT1)
167 #define _MIIC_CFG_EN_DMA (__BIT1)
184 #define _RDATA_CFG_ACKBIT (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mooney/hwi2c/
H A DregHWI2C.h121 #define CHIP_MIIC1_PAD_1 (__BIT1)
122 #define CHIP_MIIC1_PAD_MSK (__BIT1)
133 #define CHIP_DDCR_PAD_1 (__BIT1)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
150 #define CHIP_MIIC5_PAD_1 (__BIT1) //PAD_GPIO32/PAD_GPIO33
151 #define CHIP_MIIC5_PAD_MSK (__BIT1)
167 #define _MIIC_CFG_EN_DMA (__BIT1)
184 #define _RDATA_CFG_ACKBIT (__BIT1)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
191 #define _INT_STOPDET (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/messi/hwi2c/
H A DregHWI2C.h121 #define CHIP_MIIC1_PAD_1 (__BIT1)
122 #define CHIP_MIIC1_PAD_MSK (__BIT1)
133 #define CHIP_DDCR_PAD_1 (__BIT1)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
150 #define CHIP_MIIC5_PAD_1 (__BIT1) //PAD_GPIO32/PAD_GPIO33
151 #define CHIP_MIIC5_PAD_MSK (__BIT1)
167 #define _MIIC_CFG_EN_DMA (__BIT1)
184 #define _RDATA_CFG_ACKBIT (__BIT1)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
191 #define _INT_STOPDET (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/macan/hwi2c/
H A DregHWI2C.h121 #define CHIP_MIIC1_PAD_1 (__BIT1)
122 #define CHIP_MIIC1_PAD_MSK (__BIT1)
133 #define CHIP_DDCR_PAD_1 (__BIT1)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
150 #define CHIP_MIIC5_PAD_1 (__BIT1) //PAD_GPIO32/PAD_GPIO33
151 #define CHIP_MIIC5_PAD_MSK (__BIT1)
167 #define _MIIC_CFG_EN_DMA (__BIT1)
184 #define _RDATA_CFG_ACKBIT (__BIT1)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
191 #define _INT_STOPDET (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h121 #define CHIP_MIIC1_PAD_1 (__BIT1)
122 #define CHIP_MIIC1_PAD_MSK (__BIT1)
133 #define CHIP_DDCR_PAD_1 (__BIT1)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
150 #define CHIP_MIIC5_PAD_1 (__BIT1) //PAD_GPIO32/PAD_GPIO33
151 #define CHIP_MIIC5_PAD_MSK (__BIT1)
167 #define _MIIC_CFG_EN_DMA (__BIT1)
184 #define _RDATA_CFG_ACKBIT (__BIT1)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
191 #define _INT_STOPDET (__BIT1)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mainz/hwi2c/
H A DregHWI2C.h128 #define CHIP_MIIC2_PAD_1 (__BIT1)
129 #define CHIP_MIIC2_PAD_MSK (__BIT1|__BIT0)
145 #define _MIIC_CFG_EN_DMA (__BIT1)
162 #define _RDATA_CFG_ACKBIT (__BIT1)
166 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
169 #define _INT_STOPDET (__BIT1)
182 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
187 #define _DMA_CFG_RESET (__BIT1)
209 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mustang/hwi2c/
H A DregHWI2C.h116 #define CHIP_MIIC0_PAD_2 (__BIT1)
117 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
165 #define _MIIC_CFG_EN_DMA (__BIT1)
182 #define _RDATA_CFG_ACKBIT (__BIT1)
186 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
189 #define _INT_STOPDET (__BIT1)
202 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
207 #define _DMA_CFG_RESET (__BIT1)
229 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maldives/hwi2c/
H A DregHWI2C.h116 #define CHIP_MIIC0_PAD_2 (__BIT1)
117 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
165 #define _MIIC_CFG_EN_DMA (__BIT1)
182 #define _RDATA_CFG_ACKBIT (__BIT1)
186 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
189 #define _INT_STOPDET (__BIT1)
202 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
207 #define _DMA_CFG_RESET (__BIT1)
229 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregEMMflt.h107 #define __BIT1 __BIT(1) macro
167 #define EMM_ONEPAKCET_INT __BIT1
207 #define EMM_PVR_EN __BIT1
227 #define EMM_STR2MIU_EN __BIT1
251 #define REG_MIU_HIGH_PRI __BIT1
267 #define REG_TS_DATA2_SWAP __BIT1
287 #define REG_TSIF_LOSE_LOCKED_CNT_INC __BIT1
H A DregNSK2.h107 #define __BIT1 __BIT(1) macro
157 #define NSK2_INT_ASYNC_EVENT __BIT1
267 #define NI_SKB_BUSY __BIT1
334 #define RSA_PM_NSKCLK_ENABLE __BIT1
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DregEMMflt.h107 #define __BIT1 __BIT(1) macro
167 #define EMM_ONEPAKCET_INT __BIT1
207 #define EMM_PVR_EN __BIT1
227 #define EMM_STR2MIU_EN __BIT1
251 #define REG_MIU_HIGH_PRI __BIT1
267 #define REG_TS_DATA2_SWAP __BIT1
287 #define REG_TSIF_LOSE_LOCKED_CNT_INC __BIT1
H A DregNSK2.h107 #define __BIT1 __BIT(1) macro
155 #define NSK2_INT_ASYNC_EVENT __BIT1
262 #define NI_SKB_BUSY __BIT1
316 #define RSA_PM_NSKCLK_ENABLE __BIT1
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregEMMflt.h107 #define __BIT1 __BIT(1) macro
167 #define EMM_ONEPAKCET_INT __BIT1
207 #define EMM_PVR_EN __BIT1
227 #define EMM_STR2MIU_EN __BIT1
251 #define REG_MIU_HIGH_PRI __BIT1
267 #define REG_TS_DATA2_SWAP __BIT1
287 #define REG_TSIF_LOSE_LOCKED_CNT_INC __BIT1
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregEMMflt.h107 #define __BIT1 __BIT(1) macro
167 #define EMM_ONEPAKCET_INT __BIT1
207 #define EMM_PVR_EN __BIT1
227 #define EMM_STR2MIU_EN __BIT1
251 #define REG_MIU_HIGH_PRI __BIT1
267 #define REG_TS_DATA2_SWAP __BIT1
287 #define REG_TSIF_LOSE_LOCKED_CNT_INC __BIT1
H A DregNSK2.h107 #define __BIT1 __BIT(1) macro
157 #define NSK2_INT_ASYNC_EVENT __BIT1
267 #define NI_SKB_BUSY __BIT1
334 #define RSA_PM_NSKCLK_ENABLE __BIT1
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregEMMflt.h107 #define __BIT1 __BIT(1) macro
167 #define EMM_ONEPAKCET_INT __BIT1
207 #define EMM_PVR_EN __BIT1
227 #define EMM_STR2MIU_EN __BIT1
251 #define REG_MIU_HIGH_PRI __BIT1
267 #define REG_TS_DATA2_SWAP __BIT1
287 #define REG_TSIF_LOSE_LOCKED_CNT_INC __BIT1
H A DregNSK2.h107 #define __BIT1 __BIT(1) macro
156 #define NSK2_INT_ASYNC_EVENT __BIT1
266 #define NI_SKB_BUSY __BIT1
333 #define RSA_PM_NSKCLK_ENABLE __BIT1
/utopia/UTPA2-700.0.x/modules/ir_tx/hal/k6lite/ir_tx/
H A Dreg_IR_TX.h3 #define __BIT1 __BIT(1UL) macro
79 #define IR_TX_RESET __BIT1
108 #define IR_TX_Unit00_L __BIT1
125 #define IR_TX_Unit08_L __BIT1

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