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Searched refs:WRITE_BYTE (Results 1 – 25 of 303) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/sc/hal/maserati/sc/
H A DregSC.h129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)…
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)…
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/M7621/sc/
H A DregSC.h129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)…
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)…
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/maldives/sc/
H A DregSC.h129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1…
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)…
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/mainz/sc/
H A DregSC.h129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)…
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)…
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/mustang/sc/
H A DregSC.h129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1…
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)…
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/messi/sc/
H A DregSC.h129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)…
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)…
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/manhattan/sc/
H A DregSC.h129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)…
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)…
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/macan/sc/
H A DregSC.h129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)…
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)…
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/M7821/sc/
H A DregSC.h129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)…
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)…
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/maxim/sc/
H A DregSC.h129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)…
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)…
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/curry/sc/
H A DregSC.h130 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1…
131 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1…
136 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
137 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/kano/sc/
H A DregSC.h130 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1…
131 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1…
136 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
137 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/k6lite/sc/
H A DregSC.h130 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1…
131 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1…
136 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
137 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/sc/hal/k6/sc/
H A DregSC.h130 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1…
131 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1…
136 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val))
137 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val))
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dxc_hwreg_utility2.h130 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _XC_RIU_BASE + (addr), val) }
136 #define PM_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _PM_RIU_BASE + (addr), val) }
142 #define HDCP_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _HDCP_RIU_BASE + (addr), val) }
148 #define DDC_RIU_WRITE_1BYTE(addr, val) { WRITE_BYTE( _HDCP_RIU_BASE + (addr), val) }
675 …(WRITE_BYTE(_PM_RIU_BASE + (u32Addr << 1) - (u32Addr & 1), (PM_R1BYTE(u32Addr, 7:0) & ~BMASK(u8mas…
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/vbi/
H A DhalVBI.c121 …(WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Addr) << 1) - ((Addr) & 1), (R1BYTE(Addr, 0xFF) & ~(u8mask)) | …
126 (WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Reg) << 1) - ((Reg) & 1), u8Val)); \
136 …(WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Reg) << 1) - ((Reg) & 1), (R1BYTE((Reg), 0xFF) & ~(u8Mask)) | (…
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/vbi/
H A DhalVBI.c121 …(WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Addr) << 1) - ((Addr) & 1), (R1BYTE(Addr, 0xFF) & ~(u8mask)) | …
126 (WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Reg) << 1) - ((Reg) & 1), u8Val)); \
136 …(WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Reg) << 1) - ((Reg) & 1), (R1BYTE((Reg), 0xFF) & ~(u8Mask)) | (…
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/vbi/
H A DhalVBI.c121 …(WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Addr) << 1) - ((Addr) & 1), (R1BYTE(Addr, 0xFF) & ~(u8mask)) | …
126 (WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Reg) << 1) - ((Reg) & 1), u8Val)); \
136 …(WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Reg) << 1) - ((Reg) & 1), (R1BYTE((Reg), 0xFF) & ~(u8Mask)) | (…
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/vbi/
H A DhalVBI.c122 …(WRITE_BYTE(_u32VBIRiuBaseAddr + ((u32Addr) << 1) - ((u32Addr) & 1), (R1BYTE(u32Addr, 0xFF) & ~(u8…
127 (WRITE_BYTE(_u32VBIRiuBaseAddr + ((u32Reg) << 1) - ((u32Reg) & 1), u8Val)); \
137 …(WRITE_BYTE(_u32VBIRiuBaseAddr + ((u32Reg) << 1) - ((u32Reg) & 1), (R1BYTE((u32Reg), 0xFF) & ~(u8M…
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/vbi/
H A DhalVBI.c122 …(WRITE_BYTE(_u32VBIRiuBaseAddr + ((u32Addr) << 1) - ((u32Addr) & 1), (R1BYTE(u32Addr, 0xFF) & ~(u8…
127 (WRITE_BYTE(_u32VBIRiuBaseAddr + ((u32Reg) << 1) - ((u32Reg) & 1), u8Val)); \
137 …(WRITE_BYTE(_u32VBIRiuBaseAddr + ((u32Reg) << 1) - ((u32Reg) & 1), (R1BYTE((u32Reg), 0xFF) & ~(u8M…
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/vbi/
H A DhalVBI.c121 …(WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Addr) << 1) - ((Addr) & 1), (R1BYTE(Addr, 0xFF) & ~(u8mask)) | …
126 (WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Reg) << 1) - ((Reg) & 1), u8Val)); \
136 …(WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Reg) << 1) - ((Reg) & 1), (R1BYTE((Reg), 0xFF) & ~(u8Mask)) | (…
/utopia/UTPA2-700.0.x/modules/hdmi/drv/mhl/
H A Dmhl_hwreg_utility2.h115 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( MHL_XC_RIU_BASE + (addr), val) }
121 #define PM_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( MHL_PM_RIU_BASE + (addr), val) }
/utopia/UTPA2-700.0.x/modules/audio/hal/manhattan/audio/
H A DhalAUDIO.h143 …(WRITE_BYTE((MS_VIRT)_gMIO_MapBase + ((u32Addr) << 1) - ((u32Addr) & 1), (R1BYTE(u32Addr, 0xFF) & …
156 (WRITE_BYTE((MS_VIRT)_gMIO_MapBase + ((u32Reg) << 1) - ((u32Reg) & 1), u8Val)); \
166 …(WRITE_BYTE((MS_VIRT)_gMIO_MapBase + ((u32Reg) << 1) - ((u32Reg) & 1), (R1BYTE((u32Reg), 0xFF) & ~…
/utopia/UTPA2-700.0.x/modules/audio/hal/maxim/audio/
H A DhalAUDIO.h145 …(WRITE_BYTE((MS_VIRT)_gMIO_MapBase + ((u32Addr) << 1) - ((u32Addr) & 1), (R1BYTE(u32Addr, 0xFF) & …
158 (WRITE_BYTE((MS_VIRT)_gMIO_MapBase + ((u32Reg) << 1) - ((u32Reg) & 1), u8Val)); \
168 …(WRITE_BYTE((MS_VIRT)_gMIO_MapBase + ((u32Reg) << 1) - ((u32Reg) & 1), (R1BYTE((u32Reg), 0xFF) & ~…
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/vbi/
H A DhalVBI.c121 …(WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Addr) << 1) - ((Addr) & 1), (R1BYTE(Addr, 0xFF) & ~(u8mask)) | …
126 (WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Reg) << 1) - ((Reg) & 1), u8Val)); \
136 …(WRITE_BYTE(_ptrVBIRiuBaseAddr + ((Reg) << 1) - ((Reg) & 1), (R1BYTE((Reg), 0xFF) & ~(u8Mask)) | (…

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