1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 #ifndef _HWREG_UTILITY_H_ 95 #define _HWREG_UTILITY_H_ 96 97 98 #include "MsCommon.h" 99 100 //!! Do not include this header in driver or api level 101 102 //------------------------------------------------------------------------------------------------- 103 // Driver Compiler Options 104 //------------------------------------------------------------------------------------------------- 105 #define XC_MUTEX 106 #define XC_MUTEX_DBG 0 107 #define SETWINDOW_MUTEX 108 #define SETWINDOW_MUTEX_DBG 0 109 #define XC_SEMAPHORE_DBG 0 110 //------------------------------------------------------------------------------------------------- 111 // Macro and Define 112 //------------------------------------------------------------------------------------------------- 113 extern MS_VIRT _XC_RIU_BASE; // This should be inited before XC library starting. 114 extern MS_VIRT _PM_RIU_BASE; // This should be inited before XC library starting. 115 116 extern MS_VIRT _HDCP_RIU_BASE; 117 extern MS_VIRT _DDC_RIU_BASE; 118 119 #define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) 120 #define BITMASK(x) _BITMASK(1?x, 0?x) 121 #define HBMASK 0xFF00 122 #define LBMASK 0x00FF 123 124 #define RIU_MACRO_START do { 125 #define RIU_MACRO_END } while (0) 126 127 // Address bus of RIU is 16 bits. 128 #define RIU_READ_BYTE(addr) ( READ_BYTE( _XC_RIU_BASE + (addr) ) ) 129 #define RIU_READ_2BYTE(addr) ( READ_WORD( _XC_RIU_BASE + (addr) ) ) 130 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _XC_RIU_BASE + (addr), val) } 131 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _XC_RIU_BASE + (addr), val) } 132 133 // Address bus of RIU is 16 bits for PM //alex_tung 134 #define PM_RIU_READ_BYTEM(addr) ( READ_BYTE( _PM_RIU_BASE + (addr) ) ) 135 #define PM_RIU_READ_2BYTE(addr) ( READ_WORD( _PM_RIU_BASE + (addr) ) ) 136 #define PM_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _PM_RIU_BASE + (addr), val) } 137 #define PM_RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _PM_RIU_BASE + (addr), val) } 138 139 //Address bus of RIU for HDCP for T3 140 #define HDCP_RIU_READ_BYTE(addr) ( READ_BYTE( _HDCP_RIU_BASE + (addr) ) ) 141 #define HDCP_RIU_READ_2BYTE(addr) ( READ_WORD( _HDCP_RIU_BASE + (addr) ) ) 142 #define HDCP_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _HDCP_RIU_BASE + (addr), val) } 143 #define HDCP_RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _HDCP_RIU_BASE + (addr), val) } 144 145 //Address bus of RIU for DDC for T3 146 #define DDC_RIU_READ_1BYTE(addr) ( READ_BYTE( _HDCP_RIU_BASE + (addr) ) ) 147 #define DDC_RIU_READ_2BYTE(addr) ( READ_WORD( _HDCP_RIU_BASE + (addr) ) ) 148 #define DDC_RIU_WRITE_1BYTE(addr, val) { WRITE_BYTE( _HDCP_RIU_BASE + (addr), val) } 149 #define DDC_RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _HDCP_RIU_BASE + (addr), val) } 150 151 //Address bus of RIU for GOP 152 #define GOP_RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _GOP_RIU_BASE + (addr), val) } 153 154 155 #define _XC_SELECT_INTERNAL_VARIABLE(INST_ID) MDrv_XC_Resource_Mapping(INST_ID,E_XC_POOL_ID_INTERNAL_VARIABLE) 156 #define _XC_SELECT_INTERNAL_REGISTER(INST_ID) MDrv_XC_Resource_Mapping(INST_ID,E_XC_POOL_ID_INTERNAL_REGISTER) 157 #define _XC_SELECT_INTERNAL_MENULOAD(INST_ID) MDrv_XC_Resource_Mapping(INST_ID,E_XC_POOL_ID_INTERNAL_MENULOAD) 158 #define _XC_SELECT_INTERNAL_DS(INST_ID) MDrv_XC_Resource_Mapping(INST_ID,E_XC_POOL_ID_INTERNAL_DS) 159 160 #define _dbg_semaphore E_XC_ID_VAR 161 // if anyone wants to see log inside android, 162 // please replace the "printf" with "ALOGE" so that it can be printed in android process 163 #if (XC_SEMAPHORE_DBG) 164 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB 165 #define _XC_SEMAPHORE_ENTRY(pInstance,eID_TYPE) \ 166 if (eID_TYPE == _dbg_semaphore) \ 167 printf("1 [%s,%5d]==========================Prepare to get semaphore, ID = %d\n",__func__,__LINE__,eID_TYPE); \ 168 if(MDrv_XC_Get_Semaphore(g_pDevice0Instance,eID_TYPE) != UTOPIA_STATUS_SUCCESS) \ 169 { \ 170 printf("[%s,%5d] Get XC Semaphore device0 failed\n",__FUNCTION__,__LINE__); \ 171 } \ 172 if(MDrv_XC_Get_Semaphore(g_pDevice1Instance,eID_TYPE) != UTOPIA_STATUS_SUCCESS) \ 173 { \ 174 printf("[%s,%5d] Get XC Semaphore device1 failed\n",__FUNCTION__,__LINE__); \ 175 } \ 176 if (eID_TYPE == _dbg_semaphore) \ 177 printf("[%s,%5d]Semaphore Got\n\n",__func__,__LINE__); 178 179 #define _XC_SEMAPHORE_RETURN(pInstance,eID_TYPE) \ 180 if (eID_TYPE == _dbg_semaphore) \ 181 printf("0 [%s,%5d]==========================prepare to release semaphore, ID = %d\n",__func__,__LINE__,eID_TYPE); \ 182 MDrv_XC_Release_Semaphore(g_pDevice0Instance,eID_TYPE); \ 183 MDrv_XC_Release_Semaphore(g_pDevice1Instance,eID_TYPE); \ 184 if (eID_TYPE == _dbg_semaphore) \ 185 printf("[%s,%5d]Semaphore Returned\n\n",__func__,__LINE__); 186 187 #else 188 #define _XC_SEMAPHORE_ENTRY(pInstance,eID_TYPE) \ 189 if (eID_TYPE == _dbg_semaphore) \ 190 printf("1 [%s,%5d]==========================Prepare to get semaphore, ID = %d\n",__func__,__LINE__,eID_TYPE); \ 191 if(MDrv_XC_Get_Semaphore(pInstance,eID_TYPE) != UTOPIA_STATUS_SUCCESS) \ 192 { \ 193 printf("[%s,%5d] Get XC Semaphore failed\n",__FUNCTION__,__LINE__); \ 194 } \ 195 if (eID_TYPE == _dbg_semaphore) \ 196 printf("[%s,%5d]Semaphore Got\n\n",__func__,__LINE__); 197 198 #define _XC_SEMAPHORE_RETURN(pInstance,eID_TYPE) \ 199 if (eID_TYPE == _dbg_semaphore) \ 200 printf("0 [%s,%5d]==========================prepare to release semaphore, ID = %d\n",__func__,__LINE__,eID_TYPE); \ 201 MDrv_XC_Release_Semaphore(pInstance,eID_TYPE); \ 202 if (eID_TYPE == _dbg_semaphore) \ 203 printf("[%s,%5d]Semaphore Returned\n\n",__func__,__LINE__); 204 #endif 205 206 #else 207 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB 208 #define _XC_SEMAPHORE_ENTRY(pInstance,eID_TYPE) \ 209 if(MDrv_XC_Get_Semaphore(g_pDevice0Instance,eID_TYPE) != UTOPIA_STATUS_SUCCESS) \ 210 { } \ 211 if(MDrv_XC_Get_Semaphore(g_pDevice1Instance,eID_TYPE) != UTOPIA_STATUS_SUCCESS) \ 212 { } 213 214 215 216 #define _XC_SEMAPHORE_RETURN(pInstance,eID_TYPE) \ 217 MDrv_XC_Release_Semaphore(g_pDevice0Instance,eID_TYPE); \ 218 MDrv_XC_Release_Semaphore(g_pDevice1Instance,eID_TYPE); 219 #else 220 #define _XC_SEMAPHORE_ENTRY(pInstance,eID_TYPE) \ 221 if(MDrv_XC_Get_Semaphore(pInstance,eID_TYPE) != UTOPIA_STATUS_SUCCESS) \ 222 { } 223 224 #define _XC_SEMAPHORE_RETURN(pInstance,eID_TYPE) \ 225 MDrv_XC_Release_Semaphore(pInstance,eID_TYPE); 226 #endif 227 #endif 228 229 #define _XC_MUTEX_TIME_OUT MSOS_WAIT_FOREVER 230 231 // Mutex function 232 #define _XC_ENTRY(pInstance) _XC_ENTRY_MUTEX(pInstance,_XC_Mutex) 233 #define _XC_RETURN(pInstance) _XC_RETURN_MUTEX(pInstance,_XC_Mutex) 234 235 #ifdef XC_MUTEX 236 #if(XC_MUTEX_DBG) 237 #define _XC_ENTRY_MUTEX(pInstance,_mutex_) \ 238 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_REG); \ 239 printf("1,==========================Prepare to get mutex\n"); \ 240 printf("[%s][%s][%06d]\n",__FILE__,__FUNCTION__,__LINE__); \ 241 if(!MsOS_ObtainMutex(_mutex_, _XC_MUTEX_TIME_OUT)) \ 242 { \ 243 printf("==========================\n"); \ 244 printf("[%s][%s][%06d] Mutex taking timeout\n",__FILE__,__FUNCTION__,__LINE__); \ 245 } 246 #define _XC_RETURN_MUTEX(pInstance,_mutex_) \ 247 printf("0,==========================prepare to release mutex\n"); \ 248 printf("[%s][%s][%06d] \n",__FILE__,__FUNCTION__,__LINE__); \ 249 MsOS_ReleaseMutex(_mutex_); \ 250 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_REG); 251 //return _ret; 252 #else 253 #define _XC_ENTRY_MUTEX(pInstance,_mutex_) \ 254 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_REG); \ 255 if(!MsOS_ObtainMutex(_mutex_, _XC_MUTEX_TIME_OUT)) \ 256 { \ 257 } 258 #define _XC_RETURN_MUTEX(pInstance,_mutex_) \ 259 MsOS_ReleaseMutex(_mutex_); \ 260 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_REG); 261 //return _ret; 262 #endif 263 #else // #if not def XC_MUTEX 264 #define _XC_ENTRY_MUTEX(_mutex_) while(0) 265 #define _XC_RETURN_MUTEX(_mutex_) while(0) 266 #endif // #ifdef _XC_MUTEX 267 268 #define _SETWINDOW_MUTEX_TIME_OUT MSOS_WAIT_FOREVER 269 270 // Mutex function 271 #define _SETWINDOW_ENTRY() _SETWINDOW_ENTRY_MUTEX(_SetWindow_Mutex) 272 #define _SETWINDOW_RETURN() _SETWINDOW_RETURN_MUTEX(_SetWindow_Mutex) 273 274 #ifdef SETWINDOW_MUTEX 275 #if(SETWINDOW_MUTEX_DBG) 276 #define _SETWINDOW_ENTRY_MUTEX(_mutex_) \ 277 printf("1,==========================\n"); \ 278 printf("[%s][%s][%06d]\n",__FILE__,__FUNCTION__,__LINE__); \ 279 if(!MsOS_ObtainMutex(_mutex_, _SETWINDOW_MUTEX_TIME_OUT)) \ 280 { \ 281 printf("==========================\n"); \ 282 printf("[%s][%s][%06d] Mutex taking timeout\n",__FILE__,__FUNCTION__,__LINE__); \ 283 } 284 #define _SETWINDOW_RETURN_MUTEX(_mutex_) \ 285 printf("0,==========================\n"); \ 286 printf("[%s][%s][%06d] \n",__FILE__,__FUNCTION__,__LINE__); \ 287 MsOS_ReleaseMutex(_mutex_); 288 //return _ret; 289 #else 290 #define _SETWINDOW_ENTRY_MUTEX(_mutex_) \ 291 if(!MsOS_ObtainMutex(_mutex_, _SETWINDOW_MUTEX_TIME_OUT)) \ 292 { \ 293 } 294 #define _SETWINDOW_RETURN_MUTEX(_mutex_) MsOS_ReleaseMutex(_mutex_); 295 //return _ret; 296 #endif 297 #else // #if not def SETWINDOW_MUTEX 298 #define _SETWINDOW_ENTRY_MUTEX(_mutex_) while(0) 299 #define _SETWINDOW_RETURN_MUTEX(_mutex_) while(0) 300 #endif // #ifdef _SETWINDOW_MUTEX 301 302 //------------------------------------------------------------------------------------------------- 303 // Function and Variable 304 //------------------------------------------------------------------------------------------------- 305 #ifdef MVIDEO_C 306 #define INTERFACE 307 INTERFACE MS_S32 _XC_Mutex = -1; 308 INTERFACE MS_S32 _XC_ISR_Mutex = -1; 309 INTERFACE MS_S32 _SetWindow_Mutex = -1; 310 #ifdef MSOS_TYPE_LINUX_KERNEL 311 INTERFACE wait_queue_head_t _XC_EventQueue; 312 INTERFACE MS_U32 _XC_EventFlag = 0; 313 INTERFACE MS_BOOL _XC_VSyncRun = FALSE; 314 INTERFACE MS_U32 _XC_VSyncCount = 0; 315 INTERFACE MS_U32 _XC_VSyncMax = 0; 316 #endif 317 #else 318 #define INTERFACE extern 319 INTERFACE MS_S32 _XC_Mutex; 320 INTERFACE MS_S32 _XC_ISR_Mutex; 321 INTERFACE MS_S32 _SetWindow_Mutex; 322 #ifdef MSOS_TYPE_LINUX_KERNEL 323 INTERFACE wait_queue_head_t _XC_EventQueue; 324 INTERFACE MS_U32 _XC_EventFlag; 325 INTERFACE MS_BOOL _XC_VSyncRun; 326 INTERFACE MS_U32 _XC_VSyncCount; 327 INTERFACE MS_U32 _XC_VSyncMax; 328 #endif 329 #endif 330 331 INTERFACE MS_U32 _XC_Device_Offset[2];//MAX_XC_DEVICE_NUM 332 333 //============================================================= 334 // Standard Form 335 336 #define MDrv_ReadByte( u32Reg ) RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1)) 337 338 #define MDrv_Read2Byte( u32Reg ) (RIU_READ_2BYTE((u32Reg)<<1)) 339 340 #define MDrv_Read4Byte( u32Reg ) ( (MS_U32)RIU_READ_2BYTE((u32Reg)<<1) | ((MS_U32)RIU_READ_2BYTE(((u32Reg)+2)<<1)<<16 ) ) 341 342 #define MDrv_ReadRegBit( u32Reg, u8Mask ) (RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask)) 343 344 #define MDrv_WriteRegBit( u32Reg, bEnable, u8Mask ) \ 345 RIU_MACRO_START \ 346 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \ 347 (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \ 348 RIU_MACRO_END 349 350 #define MDrv_WriteByte( u32Reg, u8Val ) \ 351 RIU_MACRO_START \ 352 RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \ 353 RIU_MACRO_END 354 355 #define MDrv_Write2ByteMask( u32Reg, u16Val, u16Mask) \ 356 RIU_MACRO_START \ 357 RIU_WRITE_2BYTE(u32Reg<<1, (RIU_READ_2BYTE(u32Reg<<1) & ~(u16Mask)) | (u16Val & u16Mask)) \ 358 RIU_MACRO_END 359 360 #define MDrv_Write2Byte( u32Reg, u16Val ) \ 361 RIU_MACRO_START \ 362 if ( ((u32Reg) & 0x01) ) \ 363 { \ 364 RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ 365 RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ 366 } \ 367 else \ 368 { \ 369 RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \ 370 } \ 371 RIU_MACRO_END 372 373 #define MDrv_Write3Byte( u32Reg, u32Val ) \ 374 RIU_MACRO_START \ 375 if ((u32Reg) & 0x01) \ 376 { \ 377 RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ 378 RIU_WRITE_2BYTE( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ 379 } \ 380 else \ 381 { \ 382 RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ 383 RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ 384 } \ 385 RIU_MACRO_END 386 387 #define MDrv_Write4Byte( u32Reg, u32Val ) \ 388 RIU_MACRO_START \ 389 if ((u32Reg) & 0x01) \ 390 { \ 391 RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ 392 RIU_WRITE_2BYTE( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ 393 RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ 394 } \ 395 else \ 396 { \ 397 RIU_WRITE_2BYTE( (u32Reg) <<1 , u32Val); \ 398 RIU_WRITE_2BYTE( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ 399 } \ 400 RIU_MACRO_END 401 402 #define MDrv_WriteByteMask( u32Reg, u8Val, u8Msk ) \ 403 RIU_MACRO_START \ 404 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 405 RIU_MACRO_END 406 407 408 409 410 //============================================================= 411 // Just for Scaler 412 #if ENABLE_REGISTER_SPREAD 413 414 #define SC_W2BYTE( u32Id, u32Reg, u16Val)\ 415 CHECK_XC_SWDS_ENABLE_START\ 416 ({if((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 417 {\ 418 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF)) << 1 , u16Val ) ; \ 419 }\ 420 else\ 421 {\ 422 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) ) << 1 , u16Val ) ; \ 423 }})\ 424 CHECK_XC_SWDS_ENABLE_END 425 426 #define SC_R2BYTE( u32Id, u32Reg ) \ 427 ( { ((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 428 ? RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1 ) \ 429 : RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) ) << 1 ); } ) 430 431 #define SC_W4BYTE( u32Id, u32Reg, u32Val)\ 432 CHECK_XC_SWDS_ENABLE_START\ 433 ({if((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 434 {\ 435 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) <<1, (MS_U16)((u32Val) & 0x0000FFFF) ) ; \ 436 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + 2 ) << 1, (MS_U16)(((u32Val) >> 16) & 0x0000FFFF) );\ 437 }\ 438 else\ 439 {\ 440 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) ) <<1, (MS_U16)((u32Val) & 0x0000FFFF) ) ; \ 441 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) + 2 ) << 1, (MS_U16)(((u32Val) >> 16) & 0x0000FFFF) );\ 442 }})\ 443 CHECK_XC_SWDS_ENABLE_END 444 445 #define SC_R4BYTE( u32Id, u32Reg )\ 446 ( { ((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 447 ? RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF)) << 1 ) | (MS_U32)(RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + 2 ) << 1 )) << 16 \ 448 : RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) ) << 1 ) | (MS_U32)(RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) + 2 ) << 1 )) << 16 ; } ) 449 450 #define SC_R2BYTEMSK( u32Id, u32Reg, u16mask)\ 451 ( { ((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 452 ? RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1 ) & (u16mask)\ 453 : RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) ) << 1 ) & (u16mask) ; } ) 454 455 #define SC_W2BYTEMSK( u32Id, u32Reg, u16Val, u16Mask)\ 456 CHECK_XC_SWDS_ENABLE_START\ 457 ({if((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 458 {\ 459 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1, (RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1) & ~(u16Mask) ) | ((u16Val) & (u16Mask)) ) ;\ 460 }\ 461 else\ 462 {\ 463 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) ) << 1, (RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) ) << 1) & ~(u16Mask) ) | ((u16Val) & (u16Mask)) ) ; \ 464 }})\ 465 CHECK_XC_SWDS_ENABLE_END 466 467 468 #define GOP_R2BYTEMSK(u32Reg, u16mask)\ 469 ( { RIU_READ_2BYTE( (REG_GOP_BASE + ((u32Reg) & 0xFFFF) ) << 1) & (u16mask) ; } ) 470 471 #define GOP_W2BYTEMSK(u32Reg, u16Val, u16Mask)\ 472 ( { RIU_WRITE_2BYTE( (REG_GOP_BASE + ((u32Reg) & 0xFFFF) ) << 1, (RIU_READ_2BYTE( (REG_GOP_BASE + ((u32Reg) & 0xFFFF) ) << 1) & ~(u16Mask) ) | ((u16Val) & (u16Mask)) ) ; }) 473 474 475 #else 476 #define SC_W2BYTE( u32Id, u32Reg, u16Val)\ 477 CHECK_XC_SWDS_ENABLE_START\ 478 ({if((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 479 {\ 480 RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, ((u32Reg) >> 8) & 0x00FF ) ; \ 481 RIU_WRITE_2BYTE( (REG_SCALER_BASE +((u32Reg) & 0xFF) ) << 1 , u16Val ) ;\ 482 }\ 483 else\ 484 {\ 485 RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, (((u32Reg) >> 8) & 0x00FF) + _XC_Device_Offset[u32Id] ) ; \ 486 RIU_WRITE_2BYTE( (REG_SCALER_BASE +((u32Reg) & 0xFF) ) << 1 , u16Val ) ;\ 487 }})\ 488 CHECK_XC_SWDS_ENABLE_END 489 490 #define SC_R2BYTE( u32Id, u32Reg ) \ 491 ({if((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 492 {\ 493 RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, ( (u32Reg) >> 8) & 0x00FF ) ; \ 494 }\ 495 else\ 496 {\ 497 RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, (( (u32Reg) >> 8) & 0x00FF) + _XC_Device_Offset[u32Id] ) ; \ 498 }\ 499 RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) )<<1 ) ; } ) 500 501 #define SC_W4BYTE( u32Id, u32Reg, u32Val)\ 502 CHECK_XC_SWDS_ENABLE_START\ 503 ({if((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 504 {\ 505 RIU_WRITE_2BYTE(REG_SCALER_BASE<<1, ((u32Reg) >> 8) & 0x00FF) ; \ 506 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) <<1, (MS_U16)((u32Val) & 0x0000FFFF) ) ; \ 507 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) + 2 ) << 1, (MS_U16)(((u32Val) >> 16) & 0x0000FFFF) );\ 508 }\ 509 else\ 510 {\ 511 RIU_WRITE_2BYTE(REG_SCALER_BASE<<1, (((u32Reg) >> 8) & 0x00FF) + _XC_Device_Offset[u32Id] ) ; \ 512 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) <<1, (MS_U16)((u32Val) & 0x0000FFFF) ) ; \ 513 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) + 2 ) << 1, (MS_U16)(((u32Val) >> 16) & 0x0000FFFF) );\ 514 }})\ 515 CHECK_XC_SWDS_ENABLE_END 516 517 #define SC_R4BYTE( u32Id, u32Reg )\ 518 ({if((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 519 {\ 520 RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, ((u32Reg) >> 8) & 0x00FF ) ; \ 521 }\ 522 else\ 523 {\ 524 RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, (((u32Reg) >> 8) & 0x00FF) + _XC_Device_Offset[u32Id] ) ; \ 525 }\ 526 RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) << 1 ) | (MS_U32)(RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) + 2 ) << 1 )) << 16; } ) 527 528 #define SC_R2BYTEMSK( u32Id, u32Reg, u16mask)\ 529 ({if((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 530 {\ 531 RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, ((u32Reg) >> 8) & 0x00FF ) ; \ 532 }\ 533 else\ 534 {\ 535 RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, (((u32Reg) >> 8) & 0x00FF) + _XC_Device_Offset[u32Id] ) ; \ 536 }\ 537 RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask) ; } ) 538 539 #define SC_W2BYTEMSK( u32Id, u32Reg, u16Val, u16Mask)\ 540 CHECK_XC_SWDS_ENABLE_START\ 541 ({if((((u32Reg) & 0xFFFF) >> 8) >= _XC_Device_Offset[1])\ 542 {\ 543 RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, ((u32Reg) >> 8) & 0x00FF ) ; \ 544 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) << 1, (RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) << 1) & ~(u16Mask) ) | ((u16Val) & (u16Mask)) ) ;\ 545 }\ 546 else\ 547 {\ 548 RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, (((u32Reg) >> 8) & 0x00FF) + _XC_Device_Offset[u32Id] ) ; \ 549 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) << 1, (RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) << 1) & ~(u16Mask) ) | ((u16Val) & (u16Mask)) ) ;\ 550 }})\ 551 CHECK_XC_SWDS_ENABLE_END 552 553 #endif 554 555 //============================================================= 556 // Just for MOD 557 558 #if ENABLE_REGISTER_SPREAD 559 #define MOD_W2BYTE( u32Reg, u16Val)\ 560 ( { RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFFFF)) << 1 , u16Val ) ; } ) 561 562 #define MOD_R2BYTE( u32Reg ) \ 563 ( { RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFFFF)) <<1 ) ; } ) 564 565 #define MOD_R2BYTEMSK( u32Reg, u16mask)\ 566 ( { RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFFFF)) << 1) & (u16mask) ; } ) 567 568 #define MOD_W2BYTEMSK( u32Reg, u16Val, u16Mask)\ 569 ( { RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFFFF)) << 1, (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFFFF) ) << 1) & ~(u16Mask) ) | ((u16Val) & (u16Mask)) ) ; }) 570 571 #define PWM_R2BYTEMSK( u32Reg, u16mask)\ 572 ( { RIU_READ_2BYTE( (REG_PWM_BASE + ((u32Reg) & 0xFFFF)) << 1) & (u16mask) ; } ) 573 574 #else 575 #define MOD_W2BYTE( u32Reg, u16Val)\ 576 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \ 577 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } ) 578 579 #define MOD_R2BYTE( u32Reg ) \ 580 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \ 581 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } ) 582 583 #define MOD_R2BYTEMSK( u32Reg, u16mask)\ 584 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \ 585 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); }) 586 587 #define MOD_W2BYTEMSK( u32Reg, u16Val, u16Mask)\ 588 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \ 589 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1 ) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ); } ) 590 #endif 591 /// new MOD bank for MOD_A, and original is fo MOD_D, from Monaco 592 #define MOD_A_W2BYTE( u32Reg, u16Val)\ 593 ( { RIU_WRITE_2BYTE( (REG_MOD_A_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } ) 594 595 #define MOD_A_R2BYTE( u32Reg ) \ 596 ( { RIU_READ_2BYTE( (REG_MOD_A_BASE + ((u32Reg) & 0xFF) ) << 1) ; } ) 597 598 #define MOD_A_R2BYTEMSK( u32Reg, u16mask)\ 599 ( { RIU_READ_2BYTE( (REG_MOD_A_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); }) 600 601 #define MOD_A_W2BYTEMSK( u32Reg, u16Val, u16Mask)\ 602 ( { RIU_WRITE_2BYTE( (REG_MOD_A_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_A_BASE + ((u32Reg) & 0xFF) ) << 1 ) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ); } ) 603 604 /// VMark banks 605 #define VMARK_W2BYTE( u32Id, u32Reg, u16Val)\ 606 RIU_MACRO_START\ 607 if (u32Id == 0)\ 608 { RIU_WRITE_2BYTE( (REG_VMARK0_BASE+ ((u32Reg) & 0xFF) ) << 1, u16Val )}\ 609 else\ 610 { RIU_WRITE_2BYTE( (REG_VMARK1_BASE+ ((u32Reg) & 0xFF) ) << 1, u16Val )}\ 611 RIU_MACRO_END 612 #define VMARK_R2BYTE( u32Id, u32Reg ) \ 613 (u32Id == 0)? RIU_READ_2BYTE( (REG_VMARK0_BASE + ((u32Reg) & 0xFF) ) << 1): RIU_READ_2BYTE( (REG_VMARK1_BASE + ((u32Reg) & 0xFF) ) << 1); 614 #define VMARK_R2BYTEMSK( u32Id, u32Reg, u16mask)\ 615 (u32Id == 0)? (RIU_READ_2BYTE( (REG_VMARK0_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask)): (RIU_READ_2BYTE( (REG_VMARK1_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask)); 616 #define VMARK_W2BYTEMSK( u32Id, u32Reg, u16Val, u16Mask)\ 617 RIU_MACRO_START\ 618 if (u32Id == 0)\ 619 { RIU_WRITE_2BYTE( (REG_VMARK0_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_VMARK0_BASE + ((u32Reg) & 0xFF) ) << 1 ) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ); }\ 620 else\ 621 { RIU_WRITE_2BYTE( (REG_VMARK1_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_VMARK1_BASE + ((u32Reg) & 0xFF) ) << 1 ) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ); }\ 622 RIU_MACRO_END 623 624 //============================================================= 625 //General ( Make sure u32Reg is not ODD 626 #define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) 627 628 629 #define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) 630 631 #define W4BYTE( u32Reg, u32Val)\ 632 ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ 633 RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) 634 635 #define R4BYTE( u32Reg )\ 636 ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) 637 638 #define R2BYTEMSK( u32Reg, u16mask)\ 639 ( { RIU_READ_2BYTE( (u32Reg)<< 1) & (u16mask) ; } ) 640 641 #define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ 642 ( { RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ; } ) 643 644 #define W3BYTE( u32Reg, u32Val)\ 645 ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ 646 RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) 647 648 649 //============================================================= 650 // Just for PM registers 651 652 /* 653 R/W register forced to use 8 bit address, everytime need to r/w 2 bytes with mask 654 655 32bit address 16 bit address 8 bit address 656 0 0 0 657 1 x 1 658 2 659 3 660 4 1 2 661 5 x 3 662 6 663 7 664 8 2 4 665 9 x 5 666 A 667 B */ 668 669 // to read 0x2F03[3], please use R1BYTE(0x2F03, 3:3) 670 #define PM_R1BYTE(u32Addr, u8mask) \ 671 (READ_BYTE (_PM_RIU_BASE + (u32Addr << 1) - (u32Addr & 1)) & BMASK(u8mask)) 672 673 // to write 0x2F02[4:3] with 2'b10, please use W1BYTE(0x2F02, 0x02, 4:3) 674 #define PM_W1BYTE(u32Addr, u8Val, u8mask) \ 675 (WRITE_BYTE(_PM_RIU_BASE + (u32Addr << 1) - (u32Addr & 1), (PM_R1BYTE(u32Addr, 7:0) & ~BMASK(u8mask)) | (BITS(u8mask, u8Val) & BMASK(u8mask)))) 676 #if 1//alex_tung 677 // access PM registers 678 // u32Addr must be 16bit aligned 679 #define PM_R2BYTE( u32Reg, u16mask)\ 680 ( PM_RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) 681 // u32Addr must be 16bit aligned 682 #define PM_W2BYTE( u32Reg, u16Val, u16Mask)\ 683 ( PM_RIU_WRITE_2BYTE( (u32Reg)<< 1 , (PM_RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ) 684 #else 685 // u32Addr must be 16bit aligned 686 #define PM_R2BYTE(u32Addr, u16mask) \ 687 (READ_WORD (_PM_RIU_BASE + (u32Addr << 1)) & BMASK(u16mask)) 688 689 // u32Addr must be 16bit aligned 690 #define PM_W2BYTE(u32Addr, u16Val, u16mask) \ 691 (WRITE_WORD(_PM_RIU_BASE + (u32Addr << 1), (PM_R2BYTE(u32Addr, 15:0) & ~BMASK(u16mask)) | (BITS(u16mask, u16Val) & BMASK(u16mask)))) 692 #endif 693 //============================================================= 694 // Just for HDCP registers for T3 695 #define HDCP_W2BYTE( u32Reg, u16Val) HDCP_RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) 696 697 #define HDCP_R2BYTE( u32Reg ) HDCP_RIU_READ_2BYTE( (u32Reg) << 1) 698 699 #define HDCP_R2BYTEMSK( u32Reg, u16mask)\ 700 ( { HDCP_RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ; } ) 701 702 #define HDCP_W2BYTEMSK( u32Reg, u16Val, u16Mask)\ 703 ( { HDCP_RIU_WRITE_2BYTE( (u32Reg)<< 1 , (HDCP_RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask))) ; } ) 704 705 //============================================================= 706 //for DDC registers for T3 707 708 #define DDC_WRITE( u32Reg, u16Val) DDC_RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) 709 710 #define DDC_READ( u32Reg ) DDC_RIU_READ_2BYTE( (u32Reg) << 1) 711 #define DDC_READ_MASK( u32Reg, u16mask)\ 712 ( { DDC_RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ; } ) 713 #define DDC_WRITE_MASK( u32Reg, u16Val, u16Mask)\ 714 ( { DDC_RIU_WRITE_2BYTE( (u32Reg)<< 1 , (DDC_RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask))) ; } ) 715 716 717 718 //------------------------------------------------------------------------------------------------- 719 // Type and Structure 720 //------------------------------------------------------------------------------------------------- 721 722 723 //------------------------------------------------------------------------------------------------- 724 // Function and Variable 725 //------------------------------------------------------------------------------------------------- 726 727 728 729 730 731 732 #undef INTERFACE 733 734 #endif 735 736