1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 #ifndef _HWREG_UTILITY_H_ 95 #define _HWREG_UTILITY_H_ 96 97 98 #include "MsCommon.h" 99 100 //!! Do not include this header in driver or api level 101 102 //------------------------------------------------------------------------------------------------- 103 // Driver Compiler Options 104 //------------------------------------------------------------------------------------------------- 105 106 //------------------------------------------------------------------------------------------------- 107 // Macro and Define 108 //------------------------------------------------------------------------------------------------- 109 extern MS_VIRT MHL_XC_RIU_BASE; // This should be inited before XC library starting. 110 extern MS_VIRT MHL_PM_RIU_BASE; // This should be inited before XC library starting. 111 112 // Address bus of RIU is 16 bits. 113 #define RIU_READ_BYTE(addr) ( READ_BYTE( MHL_XC_RIU_BASE + (addr) ) ) 114 #define RIU_READ_2BYTE(addr) ( READ_WORD( MHL_XC_RIU_BASE + (addr) ) ) 115 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( MHL_XC_RIU_BASE + (addr), val) } 116 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( MHL_XC_RIU_BASE + (addr), val) } 117 118 // Address bus of RIU is 16 bits for PM //alex_tung 119 #define PM_RIU_READ_BYTEM(addr) ( READ_BYTE( MHL_PM_RIU_BASE + (addr) ) ) 120 #define PM_RIU_READ_2BYTE(addr) ( READ_WORD( MHL_PM_RIU_BASE + (addr) ) ) 121 #define PM_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( MHL_PM_RIU_BASE + (addr), val) } 122 #define PM_RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( MHL_PM_RIU_BASE + (addr), val) } 123 124 //============================================================= 125 //General ( Make sure u32Reg is not ODD 126 #define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) 127 128 129 #define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) 130 131 #define W4BYTE( u32Reg, u32Val)\ 132 ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ 133 RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) 134 135 #define R4BYTE( u32Reg )\ 136 ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) 137 138 #define R2BYTEMSK( u32Reg, u16mask)\ 139 ( { RIU_READ_2BYTE( (u32Reg)<< 1) & (u16mask) ; } ) 140 141 #define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ 142 ( { RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ; } ) 143 144 #define W3BYTE( u32Reg, u32Val)\ 145 ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ 146 RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) 147 148 #endif 149 150