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Searched refs:SEAL_TZPC_NONPM (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/seal/hal/mooney/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x00023900UL) macro
163 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02UL)
164 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20UL)
166 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80UL)
167 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61UL)
168 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60UL)
171 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0UL)
172 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4UL)
175 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8UL)
/utopia/UTPA2-700.0.x/modules/seal/hal/maxim/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x00023900UL) macro
163 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02UL)
164 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20UL)
166 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80UL)
167 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61UL)
168 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60UL)
171 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0UL)
172 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4UL)
175 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8UL)
/utopia/UTPA2-700.0.x/modules/seal/hal/mustang/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x23900) macro
160 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02)
161 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20)
163 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80)
164 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61)
165 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60)
168 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0)
169 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4)
172 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xE8)
H A DhalSEAL.c1889 u32RegAddr = SEAL_TZPC_NONPM + u32RegOffset; in HAL_SEAL_POWER_SUSPEND()
1938 u32RegAddr = SEAL_TZPC_NONPM + u32RegOffset; in HAL_SEAL_POWER_RESUME()
/utopia/UTPA2-700.0.x/modules/seal/hal/M7621/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x00023900UL) macro
162 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02UL)
163 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20UL)
165 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80UL)
166 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61UL)
167 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60UL)
170 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0UL)
171 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4UL)
174 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8UL)
/utopia/UTPA2-700.0.x/modules/seal/hal/k6lite/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x23900) macro
163 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02)
164 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20)
166 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61)
167 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60)
170 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0)
171 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4)
174 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8)
180 #define REG_TZPC_MASK (SEAL_TZPC_NONPM+0xFC)
/utopia/UTPA2-700.0.x/modules/seal/hal/k6/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x23900) macro
163 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02)
164 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20)
166 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61)
167 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60)
170 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0)
171 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4)
174 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8)
180 #define REG_TZPC_MASK (SEAL_TZPC_NONPM+0xFC)
/utopia/UTPA2-700.0.x/modules/seal/hal/curry/seal/
H A DregSEAL.h118 #define SEAL_TZPC_NONPM (0x23900) macro
175 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02)
176 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20)
178 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61)
179 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60)
182 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0)
183 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4)
186 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8)
192 #define REG_TZPC_MASK (SEAL_TZPC_NONPM+0xFC)
/utopia/UTPA2-700.0.x/modules/seal/hal/maldives/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x23900) macro
210 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02)
211 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20)
213 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80)
214 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61)
215 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60)
218 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0)
219 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4)
222 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xE8)
/utopia/UTPA2-700.0.x/modules/seal/hal/macan/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x00023900UL) macro
218 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02UL)
219 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20UL)
221 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80UL)
222 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61UL)
223 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60UL)
226 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0UL)
227 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4UL)
230 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xE8UL)
/utopia/UTPA2-700.0.x/modules/seal/hal/messi/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x00023900UL) macro
218 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02UL)
219 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20UL)
221 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80UL)
222 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61UL)
223 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60UL)
226 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0UL)
227 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4UL)
230 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xE8UL)
/utopia/UTPA2-700.0.x/modules/seal/hal/mainz/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x00023900UL) macro
226 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02UL)
227 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20UL)
229 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80UL)
230 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61UL)
231 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60UL)
234 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0UL)
235 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4UL)
238 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8UL)
/utopia/UTPA2-700.0.x/modules/seal/hal/kano/seal/
H A DregSEAL.h119 #define SEAL_TZPC_NONPM (0x23900) macro
214 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02)
215 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20)
217 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61)
218 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60)
221 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0)
222 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4)
225 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8)
231 #define REG_TZPC_MASK (SEAL_TZPC_NONPM+0xFC)
/utopia/UTPA2-700.0.x/modules/seal/hal/M7821/seal/
H A DregSEAL.h120 #define SEAL_TZPC_NONPM (0x00023900UL) macro
259 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02UL)
260 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20UL)
262 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80UL)
263 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61UL)
264 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60UL)
267 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0UL)
268 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4UL)
271 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8UL)
H A DhalSEAL.c2706 u32RegAddr = SEAL_TZPC_NONPM + u32RegOffset; in HAL_SEAL_POWER_SUSPEND()
2754 u32RegAddr = SEAL_TZPC_NONPM + u32RegOffset; in HAL_SEAL_POWER_RESUME()
/utopia/UTPA2-700.0.x/modules/seal/hal/maserati/seal/
H A DregSEAL.h120 #define SEAL_TZPC_NONPM (0x00023900UL) macro
259 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02UL)
260 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20UL)
262 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80UL)
263 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61UL)
264 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60UL)
267 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0UL)
268 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4UL)
271 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8UL)
H A DhalSEAL.c2757 u32RegAddr = SEAL_TZPC_NONPM + u32RegOffset; in HAL_SEAL_POWER_SUSPEND()
2805 u32RegAddr = SEAL_TZPC_NONPM + u32RegOffset; in HAL_SEAL_POWER_RESUME()
/utopia/UTPA2-700.0.x/modules/seal/hal/manhattan/seal/
H A DregSEAL.h120 #define SEAL_TZPC_NONPM (0x00023900UL) macro
253 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02UL)
254 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20UL)
256 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80UL)
257 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61UL)
258 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60UL)
261 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0UL)
262 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4UL)
265 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xE8UL)