xref: /utopia/UTPA2-700.0.x/modules/seal/hal/k6lite/seal/regSEAL.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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///////////////////////////////////////////////////////////////////////////////////////////////////
///
/// file    regSEAL.h
/// @brief  SEAL Control Register Definition
/// @author MStar Semiconductor Inc.
///////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _REG_SEAL_H_
#define _REG_SEAL_H_


//-------------------------------------------------------------------------------------------------
//  Hardware Capability
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Macro and Define
//-------------------------------------------------------------------------------------------------
#define BITS_RANGE(range)                       (BIT(((1)?range)+1) - BIT((0)?range))
#define BITS_RANGE_VAL(x, range)                ((x & BITS_RANGE(range)) >> ((0)?range))

#define SEAL_SECURE0_RANGE0                     (0x23700)
#define SEAL_SECURE1_RANGE0                     (0x23800)
#define SEAL_TZPC_NONPM                         (0x23900)
#define SEAL_TZPC_PM                            (0x3900)
#define SEAL_TZPC_NONPM_MIU                     (0x22700)
#define SEAL_TZPC_NONPM_MIU1                    (0x22800)

#define RANGE_ADDR_OFFSET   (0x08UL)

// MIU0 secure range
#define REG_SECURE0_RANGE0_START_ADDR           (SEAL_SECURE0_RANGE0+0x00)
#define REG_SECURE0_RANGE0_END_ADDR             (SEAL_SECURE0_RANGE0+0x04)
#define REG_SECURE0_RANGE0_ATTRIBUTE            (SEAL_SECURE0_RANGE0+0x06)

#define REG_SECURE0_DETECT_ENABLE               (SEAL_SECURE0_RANGE0+0xEC)

// MIU1 secure range
#define REG_SECURE1_RANGE0_START_ADDR           (SEAL_SECURE1_RANGE0+0x00)
#define REG_SECURE1_RANGE0_END_ADDR             (SEAL_SECURE1_RANGE0+0x04)
#define REG_SECURE1_RANGE0_ATTRIBUTE            (SEAL_SECURE1_RANGE0+0x06)

#define REG_SECURE1_DETECT_ENABLE               (SEAL_SECURE1_RANGE0+0xEC)

#define SECURE_RANGE_ADDR_DYN_CH             (BIT15)

//Secure range hitted log
#define REG_SECURE0_HITTED_STATUS              (SEAL_SECURE0_RANGE0+0xE0)
#define REG_SECURE1_HITTED_STATUS              (SEAL_SECURE1_RANGE0+0xE0)
#define REG_SECURE0_HITTED_ADDR                (SEAL_SECURE0_RANGE0+0xE2)
#define REG_SECURE1_HITTED_ADDR                (SEAL_SECURE1_RANGE0+0xE2)
#define REG_SECURE0_HITTED_RANGE_ID            (SEAL_SECURE0_RANGE0+0xEE)
#define REG_SECURE1_HITTED_RANGE_ID            (SEAL_SECURE1_RANGE0+0xEE)
#define REG_SECURE_HITTED_LOG_CLR              (BIT0)
#define REG_SECURE_HITTED_IRQ_MASK             (BIT1)
#define REG_SECURE_HITTED_FALG                 (BIT2)
#define REG_SECURE_HITTED_IS_WRITE             (BIT15)
#define REG_SECURE_HITTED_CLIENT_ID            14:8
#define REG_SECURE_HITTED_RANGE_ID             4:0
#define GET_HIT_RANGE_ID(regval)               BITS_RANGE_VAL(regval, REG_SECURE_HITTED_RANGE_ID)
#define GET_HIT_CLIENT_ID(regval)              BITS_RANGE_VAL(regval, REG_SECURE_HITTED_CLIENT_ID)

//Secure range lock
#define REG_SECURE0_LOCK                       (SEAL_SECURE0_RANGE0+0xFE)
#define REG_SECURE1_LOCK                       (SEAL_SECURE1_RANGE0+0xFE)

//Non secure processor
#define REG_TZPC_NONSECURE_PROCESSOR           (SEAL_TZPC_NONPM+0x02)
#define REG_TZPC_NONPM_SECURE_SLAVE            (SEAL_TZPC_NONPM+0x20)
#define REG_TZPC_PM_SECURE_SLAVE               (SEAL_TZPC_PM+0x20)
#define REG_TZPC_NONSECURE_HEMCU               (SEAL_TZPC_NONPM+0x61)
#define REG_TZPC_PROTECT_CTL                   (SEAL_TZPC_NONPM+0x60)

//IMI secure range
#define REG_IMI_RANGE_START_ADDR               (SEAL_TZPC_NONPM+0xE0)
#define REG_IMI_RANGE_END_ADDR                 (SEAL_TZPC_NONPM+0xE4)

//Buffer lock
#define REG_TZPC_BUFFER_LOCK                   (SEAL_TZPC_NONPM+0xC8)

//Hitted adress offset
#define HITTED_ADDRESS_OFFSET                  (7)

//Mask control
#define REG_TZPC_MASK                          (SEAL_TZPC_NONPM+0xFC)
#define REG_TZPC_RESP_MASK_MIU                 (BIT1)
#define REG_TZPC_RESP_MASK_RIU                 (BIT2)
#define REG_TZPC_RESP_MASK_UNDEF               (BIT3)

//NS Sram control
#define REG_TZPC_MIU0_CTL                      (SEAL_TZPC_NONPM_MIU+0x24)
#define REG_TZPC_MIU1_CTL                      (SEAL_TZPC_NONPM_MIU1+0x24)
#define REG_TZPC_MIU_TOP_EN                    BIT0
#define REG_TZPC_MIU0_ID0                      (SEAL_TZPC_NONPM_MIU+0x38)
#define REG_TZPC_MIU1_ID0                      (SEAL_TZPC_NONPM_MIU1+0x38)
#define REG_TZPC_MIU_ID_ENABLE                 BIT12
#define REG_TZPC_MIU0_BASE_ADDR_LOW            (SEAL_TZPC_NONPM_MIU+0x2E)
#define REG_TZPC_MIU0_BASE_ADDR_HIGH           (SEAL_TZPC_NONPM_MIU+0x30)
#define REG_TZPC_MIU1_BASE_ADDR_LOW            (SEAL_TZPC_NONPM_MIU1+0x2E)
#define REG_TZPC_MIU1_BASE_ADDR_HIGH           (SEAL_TZPC_NONPM_MIU1+0x30)

#endif // _REG_SEAL_H_