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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regSEAL.h 98 /// @brief SEAL Control Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_SEAL_H_ 103 #define _REG_SEAL_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 #define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) 115 #define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) 116 117 #define SEAL_SECURE0_RANGE0 (0x23700) 118 #define SEAL_SECURE1_RANGE0 (0x23800) 119 #define SEAL_TZPC_NONPM (0x23900) 120 #define SEAL_TZPC_PM (0x3900) 121 #define SEAL_TZPC_NONPM_MIU (0x22700) 122 #define SEAL_TZPC_NONPM_MIU1 (0x22800) 123 124 #define RANGE_ADDR_OFFSET (0x08UL) 125 126 // MIU0 secure range 127 #define REG_SECURE0_RANGE0_START_ADDR (SEAL_SECURE0_RANGE0+0x00) 128 #define REG_SECURE0_RANGE0_END_ADDR (SEAL_SECURE0_RANGE0+0x04) 129 #define REG_SECURE0_RANGE0_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x06) 130 131 #define REG_SECURE0_DETECT_ENABLE (SEAL_SECURE0_RANGE0+0xEC) 132 133 // MIU1 secure range 134 #define REG_SECURE1_RANGE0_START_ADDR (SEAL_SECURE1_RANGE0+0x00) 135 #define REG_SECURE1_RANGE0_END_ADDR (SEAL_SECURE1_RANGE0+0x04) 136 #define REG_SECURE1_RANGE0_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x06) 137 138 #define REG_SECURE1_DETECT_ENABLE (SEAL_SECURE1_RANGE0+0xEC) 139 140 #define SECURE_RANGE_ADDR_DYN_CH (BIT15) 141 142 //Secure range hitted log 143 #define REG_SECURE0_HITTED_STATUS (SEAL_SECURE0_RANGE0+0xE0) 144 #define REG_SECURE1_HITTED_STATUS (SEAL_SECURE1_RANGE0+0xE0) 145 #define REG_SECURE0_HITTED_ADDR (SEAL_SECURE0_RANGE0+0xE2) 146 #define REG_SECURE1_HITTED_ADDR (SEAL_SECURE1_RANGE0+0xE2) 147 #define REG_SECURE0_HITTED_RANGE_ID (SEAL_SECURE0_RANGE0+0xEE) 148 #define REG_SECURE1_HITTED_RANGE_ID (SEAL_SECURE1_RANGE0+0xEE) 149 #define REG_SECURE_HITTED_LOG_CLR (BIT0) 150 #define REG_SECURE_HITTED_IRQ_MASK (BIT1) 151 #define REG_SECURE_HITTED_FALG (BIT2) 152 #define REG_SECURE_HITTED_IS_WRITE (BIT15) 153 #define REG_SECURE_HITTED_CLIENT_ID 14:8 154 #define REG_SECURE_HITTED_RANGE_ID 4:0 155 #define GET_HIT_RANGE_ID(regval) BITS_RANGE_VAL(regval, REG_SECURE_HITTED_RANGE_ID) 156 #define GET_HIT_CLIENT_ID(regval) BITS_RANGE_VAL(regval, REG_SECURE_HITTED_CLIENT_ID) 157 158 //Secure range lock 159 #define REG_SECURE0_LOCK (SEAL_SECURE0_RANGE0+0xFE) 160 #define REG_SECURE1_LOCK (SEAL_SECURE1_RANGE0+0xFE) 161 162 //Non secure processor 163 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02) 164 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20) 165 #define REG_TZPC_PM_SECURE_SLAVE (SEAL_TZPC_PM+0x20) 166 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61) 167 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60) 168 169 //IMI secure range 170 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0) 171 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4) 172 173 //Buffer lock 174 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8) 175 176 //Hitted adress offset 177 #define HITTED_ADDRESS_OFFSET (7) 178 179 //Mask control 180 #define REG_TZPC_MASK (SEAL_TZPC_NONPM+0xFC) 181 #define REG_TZPC_RESP_MASK_MIU (BIT1) 182 #define REG_TZPC_RESP_MASK_RIU (BIT2) 183 #define REG_TZPC_RESP_MASK_UNDEF (BIT3) 184 185 //NS Sram control 186 #define REG_TZPC_MIU0_CTL (SEAL_TZPC_NONPM_MIU+0x24) 187 #define REG_TZPC_MIU1_CTL (SEAL_TZPC_NONPM_MIU1+0x24) 188 #define REG_TZPC_MIU_TOP_EN BIT0 189 #define REG_TZPC_MIU0_ID0 (SEAL_TZPC_NONPM_MIU+0x38) 190 #define REG_TZPC_MIU1_ID0 (SEAL_TZPC_NONPM_MIU1+0x38) 191 #define REG_TZPC_MIU_ID_ENABLE BIT12 192 #define REG_TZPC_MIU0_BASE_ADDR_LOW (SEAL_TZPC_NONPM_MIU+0x2E) 193 #define REG_TZPC_MIU0_BASE_ADDR_HIGH (SEAL_TZPC_NONPM_MIU+0x30) 194 #define REG_TZPC_MIU1_BASE_ADDR_LOW (SEAL_TZPC_NONPM_MIU1+0x2E) 195 #define REG_TZPC_MIU1_BASE_ADDR_HIGH (SEAL_TZPC_NONPM_MIU1+0x30) 196 197 #endif // _REG_SEAL_H_ 198