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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regSEAL.h 98 /// @brief SEAL Control Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_SEAL_H_ 103 #define _REG_SEAL_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 #define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) 115 #define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) 116 117 #define SEAL_SECURE0_RANGE0 (0x23700) 118 #define SEAL_TZPC_NONPM (0x23900) 119 #define SEAL_TZPC_PM (0x3900) 120 #define SEAL_TZPC_NONPM_MIU (0x22F00) 121 122 #define RANGE_ADDR_OFFSET (0x10UL) 123 124 //Secure0 range 125 #define REG_SECURE0_RANGE0_START_ADDR (SEAL_SECURE0_RANGE0+0x00) 126 #define REG_SECURE0_RANGE0_END_ADDR (SEAL_SECURE0_RANGE0+0x08) 127 #define REG_SECURE0_RANGE0_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x0E) 128 129 #define REG_SECURE0_RANGE1_START_ADDR (SEAL_SECURE0_RANGE0+0x10) 130 #define REG_SECURE0_RANGE1_END_ADDR (SEAL_SECURE0_RANGE0+0x18) 131 #define REG_SECURE0_RANGE1_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x1E) 132 133 #define REG_SECURE0_RANGE2_START_ADDR (SEAL_SECURE0_RANGE0+0x20) 134 #define REG_SECURE0_RANGE2_END_ADDR (SEAL_SECURE0_RANGE0+0x28) 135 #define REG_SECURE0_RANGE2_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x2E) 136 137 #define REG_SECURE0_RANGE3_START_ADDR (SEAL_SECURE0_RANGE0+0x30) 138 #define REG_SECURE0_RANGE3_END_ADDR (SEAL_SECURE0_RANGE0+0x38) 139 #define REG_SECURE0_RANGE3_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x3E) 140 141 #define REG_SECURE0_RANGE4_START_ADDR (SEAL_SECURE0_RANGE0+0x40) 142 #define REG_SECURE0_RANGE4_END_ADDR (SEAL_SECURE0_RANGE0+0x48) 143 #define REG_SECURE0_RANGE4_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x4E) 144 145 #define REG_SECURE0_RANGE5_START_ADDR (SEAL_SECURE0_RANGE0+0x50) 146 #define REG_SECURE0_RANGE5_END_ADDR (SEAL_SECURE0_RANGE0+0x58) 147 #define REG_SECURE0_RANGE5_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x5E) 148 149 #define REG_SECURE0_RANGE6_START_ADDR (SEAL_SECURE0_RANGE0+0x60) 150 #define REG_SECURE0_RANGE6_END_ADDR (SEAL_SECURE0_RANGE0+0x68) 151 #define REG_SECURE0_RANGE6_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x6E) 152 153 #define REG_SECURE0_RANGE7_START_ADDR (SEAL_SECURE0_RANGE0+0x70) 154 #define REG_SECURE0_RANGE7_END_ADDR (SEAL_SECURE0_RANGE0+0x78) 155 #define REG_SECURE0_RANGE7_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x7E) 156 157 #define REG_SECURE0_DETECT_ENABLE (SEAL_SECURE0_RANGE0+0xEC) 158 159 //Secure range hitted log 160 #define REG_SECURE0_HITTED_STATUS (SEAL_SECURE0_RANGE0+0xE0) 161 #define REG_SECURE0_HITTED_ADDR (SEAL_SECURE0_RANGE0+0xE2) 162 #define REG_SECURE_HITTED_LOG_CLR (BIT0) 163 #define REG_SECURE_HITTED_IRQ_MASK (BIT1) 164 #define REG_SECURE_HITTED_FALG (BIT2) 165 #define REG_SECURE_HITTED_IS_WRITE (BIT15) 166 #define REG_SECURE_HITTED_CLIENT_ID 14:8 167 #define REG_SECURE_HITTED_RANGE_ID 6:3 168 #define GET_HIT_RANGE_ID(regval) BITS_RANGE_VAL(regval, REG_SECURE_HITTED_RANGE_ID) 169 #define GET_HIT_CLIENT_ID(regval) BITS_RANGE_VAL(regval, REG_SECURE_HITTED_CLIENT_ID) 170 171 //Secure range lock 172 #define REG_SECURE0_LOCK (SEAL_SECURE0_RANGE0+0xFE) 173 174 //Non secure processor 175 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02) 176 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20) 177 #define REG_TZPC_PM_SECURE_SLAVE (SEAL_TZPC_PM+0x20) 178 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61) 179 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60) 180 181 //IMI secure range 182 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0) 183 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4) 184 185 //Buffer lock 186 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8) 187 188 //Hitted adress offset 189 #define HITTED_ADDRESS_OFFSET (7) 190 191 //Mask control 192 #define REG_TZPC_MASK (SEAL_TZPC_NONPM+0xFC) 193 #define REG_TZPC_RESP_MASK_MIU (BIT1) 194 #define REG_TZPC_RESP_MASK_RIU (BIT2) 195 #define REG_TZPC_RESP_MASK_UNDEF (BIT3) 196 197 //NS Sram control 198 #define REG_TZPC_MIU0_CTL (SEAL_TZPC_NONPM_MIU+0x44) 199 #define REG_TZPC_MIU_TOP_EN BIT0 200 #define REG_TZPC_MIU0_ID0 (SEAL_TZPC_NONPM_MIU+0x58) 201 #define REG_TZPC_MIU_ID_ENABLE BIT12 202 #define REG_TZPC_MIU0_BASE_ADDR_LOW (SEAL_TZPC_NONPM_MIU+0x4E) 203 #define REG_TZPC_MIU0_BASE_ADDR_HIGH (SEAL_TZPC_NONPM_MIU+0x50) 204 205 //------------------------------------------------------------------------------------------------- 206 // Type and Structure 207 //------------------------------------------------------------------------------------------------- 208 209 //NS cluster number 210 #define SEAL_CLIENT_NUM (4) 211 #define SEAL_CLIENT_BITS_COUNT (9) 212 #define SEAL_CLUSTER_SIZE (4) 213 #define SEAL_CLUSTER_NUM (96) 214 215 typedef struct _SRAM_TZPC_NSCluster 216 { 217 volatile MS_U64 flags[SEAL_CLUSTER_SIZE] ; // 32-byte 218 } SRAM_TZPC_NSCluster; 219 220 typedef struct _SRAM_TZPC_NSGroup 221 { 222 SRAM_TZPC_NSCluster cluster[SEAL_CLUSTER_NUM]; 223 } SRAM_TZPC_NSGroup; 224 225 #endif // _REG_SEAL_H_ 226 227