xref: /utopia/UTPA2-700.0.x/modules/seal/hal/curry/seal/regSEAL.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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///////////////////////////////////////////////////////////////////////////////////////////////////
///
/// file    regSEAL.h
/// @brief  SEAL Control Register Definition
/// @author MStar Semiconductor Inc.
///////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _REG_SEAL_H_
#define _REG_SEAL_H_


//-------------------------------------------------------------------------------------------------
//  Hardware Capability
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Macro and Define
//-------------------------------------------------------------------------------------------------
#define BITS_RANGE(range)                       (BIT(((1)?range)+1) - BIT((0)?range))
#define BITS_RANGE_VAL(x, range)                ((x & BITS_RANGE(range)) >> ((0)?range))

#define SEAL_SECURE0_RANGE0                     (0x23700)
#define SEAL_TZPC_NONPM                         (0x23900)
#define SEAL_TZPC_PM                            (0x3900)
#define SEAL_TZPC_NONPM_MIU                     (0x22F00)

#define RANGE_ADDR_OFFSET   (0x10UL)

//Secure0 range
#define REG_SECURE0_RANGE0_START_ADDR           (SEAL_SECURE0_RANGE0+0x00)
#define REG_SECURE0_RANGE0_END_ADDR             (SEAL_SECURE0_RANGE0+0x08)
#define REG_SECURE0_RANGE0_ATTRIBUTE            (SEAL_SECURE0_RANGE0+0x0E)

#define REG_SECURE0_RANGE1_START_ADDR           (SEAL_SECURE0_RANGE0+0x10)
#define REG_SECURE0_RANGE1_END_ADDR             (SEAL_SECURE0_RANGE0+0x18)
#define REG_SECURE0_RANGE1_ATTRIBUTE            (SEAL_SECURE0_RANGE0+0x1E)

#define REG_SECURE0_RANGE2_START_ADDR           (SEAL_SECURE0_RANGE0+0x20)
#define REG_SECURE0_RANGE2_END_ADDR             (SEAL_SECURE0_RANGE0+0x28)
#define REG_SECURE0_RANGE2_ATTRIBUTE            (SEAL_SECURE0_RANGE0+0x2E)

#define REG_SECURE0_RANGE3_START_ADDR           (SEAL_SECURE0_RANGE0+0x30)
#define REG_SECURE0_RANGE3_END_ADDR             (SEAL_SECURE0_RANGE0+0x38)
#define REG_SECURE0_RANGE3_ATTRIBUTE            (SEAL_SECURE0_RANGE0+0x3E)

#define REG_SECURE0_RANGE4_START_ADDR           (SEAL_SECURE0_RANGE0+0x40)
#define REG_SECURE0_RANGE4_END_ADDR             (SEAL_SECURE0_RANGE0+0x48)
#define REG_SECURE0_RANGE4_ATTRIBUTE            (SEAL_SECURE0_RANGE0+0x4E)

#define REG_SECURE0_RANGE5_START_ADDR           (SEAL_SECURE0_RANGE0+0x50)
#define REG_SECURE0_RANGE5_END_ADDR             (SEAL_SECURE0_RANGE0+0x58)
#define REG_SECURE0_RANGE5_ATTRIBUTE            (SEAL_SECURE0_RANGE0+0x5E)

#define REG_SECURE0_RANGE6_START_ADDR           (SEAL_SECURE0_RANGE0+0x60)
#define REG_SECURE0_RANGE6_END_ADDR             (SEAL_SECURE0_RANGE0+0x68)
#define REG_SECURE0_RANGE6_ATTRIBUTE            (SEAL_SECURE0_RANGE0+0x6E)

#define REG_SECURE0_RANGE7_START_ADDR           (SEAL_SECURE0_RANGE0+0x70)
#define REG_SECURE0_RANGE7_END_ADDR             (SEAL_SECURE0_RANGE0+0x78)
#define REG_SECURE0_RANGE7_ATTRIBUTE            (SEAL_SECURE0_RANGE0+0x7E)

#define REG_SECURE0_DETECT_ENABLE               (SEAL_SECURE0_RANGE0+0xEC)

//Secure range hitted log
#define REG_SECURE0_HITTED_STATUS              (SEAL_SECURE0_RANGE0+0xE0)
#define REG_SECURE0_HITTED_ADDR                (SEAL_SECURE0_RANGE0+0xE2)
#define REG_SECURE_HITTED_LOG_CLR              (BIT0)
#define REG_SECURE_HITTED_IRQ_MASK             (BIT1)
#define REG_SECURE_HITTED_FALG                 (BIT2)
#define REG_SECURE_HITTED_IS_WRITE             (BIT15)
#define REG_SECURE_HITTED_CLIENT_ID            14:8
#define REG_SECURE_HITTED_RANGE_ID             6:3
#define GET_HIT_RANGE_ID(regval)               BITS_RANGE_VAL(regval, REG_SECURE_HITTED_RANGE_ID)
#define GET_HIT_CLIENT_ID(regval)              BITS_RANGE_VAL(regval, REG_SECURE_HITTED_CLIENT_ID)

//Secure range lock
#define REG_SECURE0_LOCK                       (SEAL_SECURE0_RANGE0+0xFE)

//Non secure processor
#define REG_TZPC_NONSECURE_PROCESSOR           (SEAL_TZPC_NONPM+0x02)
#define REG_TZPC_NONPM_SECURE_SLAVE            (SEAL_TZPC_NONPM+0x20)
#define REG_TZPC_PM_SECURE_SLAVE               (SEAL_TZPC_PM+0x20)
#define REG_TZPC_NONSECURE_HEMCU               (SEAL_TZPC_NONPM+0x61)
#define REG_TZPC_PROTECT_CTL                   (SEAL_TZPC_NONPM+0x60)

//IMI secure range
#define REG_IMI_RANGE_START_ADDR               (SEAL_TZPC_NONPM+0xE0)
#define REG_IMI_RANGE_END_ADDR                 (SEAL_TZPC_NONPM+0xE4)

//Buffer lock
#define REG_TZPC_BUFFER_LOCK                   (SEAL_TZPC_NONPM+0xC8)

//Hitted adress offset
#define HITTED_ADDRESS_OFFSET                  (7)

//Mask control
#define REG_TZPC_MASK                          (SEAL_TZPC_NONPM+0xFC)
#define REG_TZPC_RESP_MASK_MIU                 (BIT1)
#define REG_TZPC_RESP_MASK_RIU                 (BIT2)
#define REG_TZPC_RESP_MASK_UNDEF               (BIT3)

//NS Sram control
#define REG_TZPC_MIU0_CTL                      (SEAL_TZPC_NONPM_MIU+0x44)
#define REG_TZPC_MIU_TOP_EN                    BIT0
#define REG_TZPC_MIU0_ID0                      (SEAL_TZPC_NONPM_MIU+0x58)
#define REG_TZPC_MIU_ID_ENABLE                 BIT12
#define REG_TZPC_MIU0_BASE_ADDR_LOW            (SEAL_TZPC_NONPM_MIU+0x4E)
#define REG_TZPC_MIU0_BASE_ADDR_HIGH           (SEAL_TZPC_NONPM_MIU+0x50)

//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------

//NS cluster number
#define SEAL_CLIENT_NUM                        (4)
#define SEAL_CLIENT_BITS_COUNT                 (9)
#define SEAL_CLUSTER_SIZE                      (4)
#define SEAL_CLUSTER_NUM                       (96)

typedef struct _SRAM_TZPC_NSCluster
{
    volatile MS_U64 flags[SEAL_CLUSTER_SIZE] ; // 32-byte
} SRAM_TZPC_NSCluster;

typedef struct _SRAM_TZPC_NSGroup
{
    SRAM_TZPC_NSCluster cluster[SEAL_CLUSTER_NUM];
} SRAM_TZPC_NSGroup;

#endif // _REG_SEAL_H_