Searched refs:REG_RNG_TRNG_SCPU (Results 1 – 10 of 10) sorted by relevance
2487 MS_U32 u32Tmp=REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU); in HAL_CIPHER_Misc_Random()2489 REG32_W(_u32RegBase+REG_RNG_TRNG_SCPU, u32Tmp); in HAL_CIPHER_Misc_Random()2491 while( !(REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) ); in HAL_CIPHER_Misc_Random()2493 …while( (u16TRN = (REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN… in HAL_CIPHER_Misc_Random()
453 #define REG_RNG_TRNG_SCPU (REG_RNG_BASE + 0x12 * 4) macro
2446 REG32(_u32RegBase+REG_RNG_TRNG_SCPU) ^= REG_RNG_TRNG_ACK_SCPU; in HAL_CIPHER_Misc_Random()2448 while( !(REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) ); in HAL_CIPHER_Misc_Random()2450 …while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN ); in HAL_CIPHER_Misc_Random()
452 #define REG_RNG_TRNG_SCPU (REG_RNG_BASE + 0x12 * 4) macro
2443 REG32(_u32RegBase+REG_RNG_TRNG_SCPU) ^= REG_RNG_TRNG_ACK_SCPU; in HAL_CIPHER_Misc_Random()2445 while( !(REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) ); in HAL_CIPHER_Misc_Random()2447 …while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN ); in HAL_CIPHER_Misc_Random()
2532 REG32(_u32RegBase+REG_RNG_TRNG_SCPU) ^= REG_RNG_TRNG_ACK_SCPU; in HAL_CIPHER_Misc_Random()2534 while( !(REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) ); in HAL_CIPHER_Misc_Random()2536 …while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN ); in HAL_CIPHER_Misc_Random()
509 #define REG_RNG_TRNG_SCPU (REG_RNG_BASE + 0x12 * 4) macro