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Searched refs:REG_MHL_CBUS_3A (Results 1 – 25 of 35) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c842 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
2311 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
2656 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
2660 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
2825 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h139 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c842 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
2308 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
2653 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
2657 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
2822 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h139 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhalMHL.c615 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
2673 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
2987 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
2991 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
3247 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h174 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhalMHL.c615 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
2673 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
2987 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
2991 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
3247 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h174 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c799 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
3111 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3444 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
3448 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
3704 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h174 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c815 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
3135 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3468 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
3472 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
3728 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h174 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c852 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
3657 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3979 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
3983 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
4243 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h174 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c852 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
3657 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3979 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
3983 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
4243 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h174 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c852 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
3657 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3979 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
3983 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
4243 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h174 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c852 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
3657 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3979 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
3983 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
4243 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h174 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c852 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
3657 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3979 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
3983 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
4243 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
H A DhwregMHL.h174 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_mhl.h116 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_mhl.h116 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_pm_sleep.h585 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) macro

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