xref: /utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/hwregMHL.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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 [Module Name]: hwreg_mhl.h
 [Date]:        04-March-2012
 [Comment]:
 [Reversion History]:
*******************************************************************************/

//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------
enum EN_MUX_INPUTPORT_MHL_INFO
{
    E_MUX_NOT_SUPPORT_MHL = 0x0,
    E_MUX_SUPPORT_MHL_PORT_DVI0 = 0x1,
    E_MUX_SUPPORT_MHL_PORT_DVI1 = 0x2,
    E_MUX_SUPPORT_MHL_PORT_DVI2 = 0x4,
    E_MUX_SUPPORT_MHL_PORT_DVI3 = 0x8,
    E_MUX_ALL_SUPPORT_MHL = 0xF,
};

//-------------------------------------------------------------------------------------------------
//  Global Variables
//-------------------------------------------------------------------------------------------------
extern MS_U8 ucMHLSupportPort;

///////////////////////////////////////////////////////
// Register bank
///////////////////////////////////////////////////////
#define REG_MHL_TMDS_BASE    0x122700
#define REG_MHL_CBUS_BANK    0x001F00
#define REG_PM_MHL_CBUS_BANK    0x002F00


// MHL CBUS Bank - CBUS logic control
#define REG_MHL_CBUS_00    (REG_MHL_CBUS_BANK + 0x00)
#define REG_MHL_CBUS_01    (REG_MHL_CBUS_BANK + 0x02)
#define REG_MHL_CBUS_02    (REG_MHL_CBUS_BANK + 0x04)
#define REG_MHL_CBUS_03    (REG_MHL_CBUS_BANK + 0x06)
#define REG_MHL_CBUS_04    (REG_MHL_CBUS_BANK + 0x08)
#define REG_MHL_CBUS_05    (REG_MHL_CBUS_BANK + 0x0A)
#define REG_MHL_CBUS_06    (REG_MHL_CBUS_BANK + 0x0C)
#define REG_MHL_CBUS_07    (REG_MHL_CBUS_BANK + 0x0E)
#define REG_MHL_CBUS_08    (REG_MHL_CBUS_BANK + 0x10)
#define REG_MHL_CBUS_09    (REG_MHL_CBUS_BANK + 0x12)
#define REG_MHL_CBUS_0B    (REG_MHL_CBUS_BANK + 0x16)
#define REG_MHL_CBUS_0F    (REG_MHL_CBUS_BANK + 0x1E)
#define REG_MHL_CBUS_10    (REG_MHL_CBUS_BANK + 0x20)
#define REG_MHL_CBUS_14    (REG_MHL_CBUS_BANK + 0x28)
#define REG_MHL_CBUS_18    (REG_MHL_CBUS_BANK + 0x30)
#define REG_MHL_CBUS_19    (REG_MHL_CBUS_BANK + 0x32)
#define REG_MHL_CBUS_1B    (REG_MHL_CBUS_BANK + 0x36)
#define REG_MHL_CBUS_1F    (REG_MHL_CBUS_BANK + 0x3E)
#define REG_MHL_CBUS_21    (REG_MHL_CBUS_BANK + 0x42)
#define REG_MHL_CBUS_22    (REG_MHL_CBUS_BANK + 0x44)
#define REG_MHL_CBUS_23    (REG_MHL_CBUS_BANK + 0x46)
#define REG_MHL_CBUS_24    (REG_MHL_CBUS_BANK + 0x48)
#define REG_MHL_CBUS_25    (REG_MHL_CBUS_BANK + 0x4A)
#define REG_MHL_CBUS_26    (REG_MHL_CBUS_BANK + 0x4C)
#define REG_MHL_CBUS_3A    (REG_MHL_CBUS_BANK + 0x74)
#define REG_MHL_CBUS_3B    (REG_MHL_CBUS_BANK + 0x76)
#define REG_MHL_CBUS_3C    (REG_MHL_CBUS_BANK + 0x78)
#define REG_MHL_CBUS_3D    (REG_MHL_CBUS_BANK + 0x7A)
#define REG_MHL_CBUS_50    (REG_MHL_CBUS_BANK + 0xA2)
#define REG_MHL_CBUS_52    (REG_MHL_CBUS_BANK + 0xA4)
#define REG_MHL_CBUS_53    (REG_MHL_CBUS_BANK + 0xA6)
#define REG_MHL_CBUS_55    (REG_MHL_CBUS_BANK + 0xAA)
#define REG_MHL_CBUS_57    (REG_MHL_CBUS_BANK + 0xAE)
#define REG_MHL_CBUS_58    (REG_MHL_CBUS_BANK + 0xB0)
#define REG_MHL_CBUS_59    (REG_MHL_CBUS_BANK + 0xB2)
#define REG_MHL_CBUS_5A    (REG_MHL_CBUS_BANK + 0xB4)
#define REG_MHL_CBUS_5D    (REG_MHL_CBUS_BANK + 0xBA)
#define REG_MHL_CBUS_63    (REG_MHL_CBUS_BANK + 0xC6)
#define REG_MHL_CBUS_65    (REG_MHL_CBUS_BANK + 0xCA)
#define REG_MHL_CBUS_6C    (REG_MHL_CBUS_BANK + 0xD8)
#define REG_MHL_CBUS_6D    (REG_MHL_CBUS_BANK + 0xDA)
#define REG_MHL_CBUS_70    (REG_MHL_CBUS_BANK + 0xE0)
#define REG_MHL_CBUS_71    (REG_MHL_CBUS_BANK + 0xE2)
#define REG_MHL_CBUS_78    (REG_MHL_CBUS_BANK + 0xF0)

// PM MHL CBUS Bank - CBUS PHY control
#define REG_PM_MHL_CBUS_00    (REG_PM_MHL_CBUS_BANK + 0x00)
#define REG_PM_MHL_CBUS_01    (REG_PM_MHL_CBUS_BANK + 0x02)
#define REG_PM_MHL_CBUS_0C    (REG_PM_MHL_CBUS_BANK + 0x18)
#define REG_PM_MHL_CBUS_0D    (REG_PM_MHL_CBUS_BANK + 0x1A)
#define REG_PM_MHL_CBUS_16    (REG_PM_MHL_CBUS_BANK + 0x2C)
#define REG_PM_MHL_CBUS_17    (REG_PM_MHL_CBUS_BANK + 0x2E)
#define REG_PM_MHL_CBUS_18    (REG_PM_MHL_CBUS_BANK + 0x30)
#define REG_PM_MHL_CBUS_20    (REG_PM_MHL_CBUS_BANK + 0x40)
#define REG_PM_MHL_CBUS_21    (REG_PM_MHL_CBUS_BANK + 0x42)
#define REG_PM_MHL_CBUS_30    (REG_PM_MHL_CBUS_BANK + 0x60)
#define REG_PM_MHL_CBUS_31    (REG_PM_MHL_CBUS_BANK + 0x62)
#define REG_PM_MHL_CBUS_38    (REG_PM_MHL_CBUS_BANK + 0x70)


// MHL TMDS Bank
#define REG_MHL_TMDS_68    (REG_MHL_TMDS_BASE + 0xD0)
#define REG_MHL_TMDS_69    (REG_MHL_TMDS_BASE + 0xD2)