xref: /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/hwreg_mhl.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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78 /******************************************************************************
79  Copyright (c) 2012 MStar Semiconductor, Inc.
80  All rights reserved.
81 
82  [Module Name]: hwreg_mhl.h
83  [Date]:        04-March-2012
84  [Comment]:
85  [Reversion History]:
86 *******************************************************************************/
87 
88 ///////////////////////////////////////////////////////
89 // Register bank
90 ///////////////////////////////////////////////////////
91 #define REG_MHL_TMDS_BASE    0x122700
92 #define REG_MHL_CBUS_BANK    0x001F00
93 #define REG_PM_MHL_CBUS_BANK    0x002F00
94 
95 
96 // MHL CBUS Bank - CBUS logic control
97 #define REG_MHL_CBUS_01    (REG_MHL_CBUS_BANK + 0x02)
98 #define REG_MHL_CBUS_02    (REG_MHL_CBUS_BANK + 0x04)
99 #define REG_MHL_CBUS_03    (REG_MHL_CBUS_BANK + 0x06)
100 #define REG_MHL_CBUS_04    (REG_MHL_CBUS_BANK + 0x08)
101 #define REG_MHL_CBUS_05    (REG_MHL_CBUS_BANK + 0x0A)
102 #define REG_MHL_CBUS_06    (REG_MHL_CBUS_BANK + 0x0C)
103 #define REG_MHL_CBUS_07    (REG_MHL_CBUS_BANK + 0x0E)
104 #define REG_MHL_CBUS_08    (REG_MHL_CBUS_BANK + 0x10)
105 #define REG_MHL_CBUS_14    (REG_MHL_CBUS_BANK + 0x28)
106 #define REG_MHL_CBUS_18    (REG_MHL_CBUS_BANK + 0x30)
107 #define REG_MHL_CBUS_19    (REG_MHL_CBUS_BANK + 0x32)
108 #define REG_MHL_CBUS_1B    (REG_MHL_CBUS_BANK + 0x36)
109 #define REG_MHL_CBUS_1F    (REG_MHL_CBUS_BANK + 0x3E)
110 #define REG_MHL_CBUS_21    (REG_MHL_CBUS_BANK + 0x42)
111 #define REG_MHL_CBUS_22    (REG_MHL_CBUS_BANK + 0x44)
112 #define REG_MHL_CBUS_23    (REG_MHL_CBUS_BANK + 0x46)
113 #define REG_MHL_CBUS_24    (REG_MHL_CBUS_BANK + 0x48)
114 #define REG_MHL_CBUS_25    (REG_MHL_CBUS_BANK + 0x4A)
115 #define REG_MHL_CBUS_26    (REG_MHL_CBUS_BANK + 0x4C)
116 #define REG_MHL_CBUS_3A    (REG_MHL_CBUS_BANK + 0x74)
117 #define REG_MHL_CBUS_3B    (REG_MHL_CBUS_BANK + 0x76)
118 #define REG_MHL_CBUS_3C    (REG_MHL_CBUS_BANK + 0x78)
119 #define REG_MHL_CBUS_3D    (REG_MHL_CBUS_BANK + 0x7A)
120 #define REG_MHL_CBUS_52    (REG_MHL_CBUS_BANK + 0xA4)
121 #define REG_MHL_CBUS_53    (REG_MHL_CBUS_BANK + 0xA6)
122 #define REG_MHL_CBUS_55    (REG_MHL_CBUS_BANK + 0xAA)
123 #define REG_MHL_CBUS_57    (REG_MHL_CBUS_BANK + 0xAE)
124 #define REG_MHL_CBUS_58    (REG_MHL_CBUS_BANK + 0xB0)
125 #define REG_MHL_CBUS_5D    (REG_MHL_CBUS_BANK + 0xBA)
126 #define REG_MHL_CBUS_63    (REG_MHL_CBUS_BANK + 0xC6)
127 #define REG_MHL_CBUS_65    (REG_MHL_CBUS_BANK + 0xCA)
128 #define REG_MHL_CBUS_70    (REG_MHL_CBUS_BANK + 0xE0)
129 #define REG_MHL_CBUS_71    (REG_MHL_CBUS_BANK + 0xE2)
130 #define REG_MHL_CBUS_78    (REG_MHL_CBUS_BANK + 0xF0)
131 
132 
133 // PM MHL CBUS Bank - CBUS PHY control
134 #define REG_PM_MHL_CBUS_00    (REG_PM_MHL_CBUS_BANK + 0x00)
135 #define REG_PM_MHL_CBUS_0C    (REG_PM_MHL_CBUS_BANK + 0x18)
136 #define REG_PM_MHL_CBUS_0D    (REG_PM_MHL_CBUS_BANK + 0x1A)
137 #define REG_PM_MHL_CBUS_16    (REG_PM_MHL_CBUS_BANK + 0x2C)
138 #define REG_PM_MHL_CBUS_17    (REG_PM_MHL_CBUS_BANK + 0x2E)
139 #define REG_PM_MHL_CBUS_18    (REG_PM_MHL_CBUS_BANK + 0x30)
140 #define REG_PM_MHL_CBUS_20    (REG_PM_MHL_CBUS_BANK + 0x40)
141 #define REG_PM_MHL_CBUS_21    (REG_PM_MHL_CBUS_BANK + 0x42)
142 #define REG_PM_MHL_CBUS_30    (REG_PM_MHL_CBUS_BANK + 0x60)
143 #define REG_PM_MHL_CBUS_31    (REG_PM_MHL_CBUS_BANK + 0x62)
144 #define REG_PM_MHL_CBUS_38    (REG_PM_MHL_CBUS_BANK + 0x70)
145 
146