Searched refs:REG_DMA_CTRL (Results 1 – 10 of 10) sorted by relevance
651 MS_U32 u32DMACtrl = REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]); in HAL_CIPHER_ResetException()652 …REG32_W(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL], u32DMACtrl | REG_EXCEPT_FLAG_CLEAR); //clear all ex… in HAL_CIPHER_ResetException()653 …REG32_W(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL], u32DMACtrl & ~REG_EXCEPT_FLAG_CLEAR); //enable acpu… in HAL_CIPHER_ResetException()678 MS_U32 DMA_CTRL = REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]); in HAL_CIPHER_SWReset()679 REG32_W(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL], DMA_CTRL | REG_DMA_SW_RESET); //reset CryptoDMA in HAL_CIPHER_SWReset()680 REG32_W(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL], DMA_CTRL & ~REG_DMA_SW_RESET); //enable CryptoDMA in HAL_CIPHER_SWReset()1170 MS_U32 u32DMACtrl = REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]); in HAL_CIPHER_DMA_Start()
105 #define REG_DMA_CTRL 0x0 macro
597 MS_U32 u32DMACtrl = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]); in HAL_CIPHER_ResetException()598 …REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl | REG_EXCEPT_FLAG_CLEAR; //clear all exc… in HAL_CIPHER_ResetException()599 …REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl & ~REG_EXCEPT_FLAG_CLEAR; //enable acpu … in HAL_CIPHER_ResetException()624 MS_U32 DMA_CTRL = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]); in HAL_CIPHER_SWReset()625 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL | REG_DMA_SW_RESET; //reset CryptoDMA in HAL_CIPHER_SWReset()626 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL & ~REG_DMA_SW_RESET; //enable CryptoDMA in HAL_CIPHER_SWReset()
594 MS_U32 u32DMACtrl = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]); in HAL_CIPHER_ResetException()595 …REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl | REG_EXCEPT_FLAG_CLEAR; //clear all exc… in HAL_CIPHER_ResetException()596 …REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl & ~REG_EXCEPT_FLAG_CLEAR; //enable acpu … in HAL_CIPHER_ResetException()621 MS_U32 DMA_CTRL = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]); in HAL_CIPHER_SWReset()622 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL | REG_DMA_SW_RESET; //reset CryptoDMA in HAL_CIPHER_SWReset()623 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL & ~REG_DMA_SW_RESET; //enable CryptoDMA in HAL_CIPHER_SWReset()
610 MS_U32 u32DMACtrl = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]); in HAL_CIPHER_ResetException()611 …REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl | REG_EXCEPT_FLAG_CLEAR; //clear all exc… in HAL_CIPHER_ResetException()612 …REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl & ~REG_EXCEPT_FLAG_CLEAR; //enable acpu … in HAL_CIPHER_ResetException()638 MS_U32 DMA_CTRL = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]); in HAL_CIPHER_SWReset()639 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL | REG_DMA_SW_RESET; //reset CryptoDMA in HAL_CIPHER_SWReset()640 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL & ~REG_DMA_SW_RESET; //enable CryptoDMA in HAL_CIPHER_SWReset()