Home
last modified time | relevance | path

Searched refs:REG_AFEC_BASE (Results 1 – 25 of 49) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_adc.c497 u32Addr = u32Addr | ( REG_AFEC_BASE & 0xFFFF0000 ); in Hal_ADC_LoadTable()
781 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
782 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
793 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_AV_Calibration()
794 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
809 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
810 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
821 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_SV_Calibration()
822 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_adc.c497 u32Addr = u32Addr | ( REG_AFEC_BASE & 0xFFFF0000 ); in Hal_ADC_LoadTable()
781 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
782 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
793 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_AV_Calibration()
794 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
809 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
810 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
821 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_SV_Calibration()
822 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_adc.c500 u32Addr = u32Addr | ( REG_AFEC_BASE & 0xFFFF0000 ); in Hal_ADC_LoadTable()
789 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
790 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
801 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_AV_Calibration()
802 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
818 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
819 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
830 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_SV_Calibration()
831 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_adc.c497 u32Addr = u32Addr | ( REG_AFEC_BASE & 0xFFFF0000 ); in Hal_ADC_LoadTable()
781 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
782 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
793 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_AV_Calibration()
794 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
809 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
810 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
821 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_SV_Calibration()
822 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_adc.c502 u32Addr = u32Addr | ( REG_AFEC_BASE & 0xFFFF0000 ); in Hal_ADC_LoadTable()
799 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
800 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
811 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_AV_Calibration()
812 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
828 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
829 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
840 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_SV_Calibration()
841 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_adc.c502 u32Addr = u32Addr | ( REG_AFEC_BASE & 0xFFFF0000 ); in Hal_ADC_LoadTable()
791 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
792 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
803 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_AV_Calibration()
804 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
820 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
821 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
832 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_SV_Calibration()
833 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_adc.c502 u32Addr = u32Addr | ( REG_AFEC_BASE & 0xFFFF0000 ); in Hal_ADC_LoadTable()
791 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
792 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
803 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_AV_Calibration()
804 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
820 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
821 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
832 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_SV_Calibration()
833 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_adc.c502 u32Addr = u32Addr | ( REG_AFEC_BASE & 0xFFFF0000 ); in Hal_ADC_LoadTable()
791 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
792 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
803 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_AV_Calibration()
804 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
820 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
821 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
832 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_SV_Calibration()
833 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_adc.c502 u32Addr = u32Addr | ( REG_AFEC_BASE & 0xFFFF0000 ); in Hal_ADC_LoadTable()
791 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
792 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
803 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_AV_Calibration()
804 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_AV_Calibration()
820 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
821 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg | BIT(5) | BIT(6) , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
832 reg = R2BYTEMSK(REG_AFEC_BASE+0x94 , ~(BIT(5) | BIT(6)) ); in _Hal_ADC_Set_SV_Calibration()
833 W2BYTEMSK(REG_AFEC_BASE+0x94 , reg , 0xFFFF ); in _Hal_ADC_Set_SV_Calibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dxc_Analog_Reg.h125 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
126 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
H A Dhwreg_adc_atop.h368 #define REG_ADC_AFEC_7A_L (REG_AFEC_BASE + 0xF4)
369 #define REG_ADC_AFEC_7A_H (REG_AFEC_BASE + 0xF5)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dxc_Analog_Reg.h125 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
126 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dxc_Analog_Reg.h125 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
126 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dxc_Analog_Reg.h125 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
126 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dxc_Analog_Reg.h125 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
126 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dxc_Analog_Reg.h125 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
126 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
H A Dhwreg_adc_atop.h368 #define REG_ADC_AFEC_7A_L (REG_AFEC_BASE + 0xF4)
369 #define REG_ADC_AFEC_7A_H (REG_AFEC_BASE + 0xF5)
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dxc_Analog_Reg.h125 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
126 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
H A Dhwreg_adc_atop.h368 #define REG_ADC_AFEC_7A_L (REG_AFEC_BASE + 0xF4)
369 #define REG_ADC_AFEC_7A_H (REG_AFEC_BASE + 0xF5)
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dxc_Analog_Reg.h125 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
126 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
H A Dhwreg_adc_atop.h368 #define REG_ADC_AFEC_7A_L (REG_AFEC_BASE + 0xF4)
369 #define REG_ADC_AFEC_7A_H (REG_AFEC_BASE + 0xF5)
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dxc_Analog_Reg.h125 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
126 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dxc_Analog_Reg.h260 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
261 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dxc_Analog_Reg.h260 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x)
261 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x)
H A Dhwreg_adc_atop.h619 #define REG_ADC_AFEC_7A_L (REG_AFEC_BASE + 0xF4)
620 #define REG_ADC_AFEC_7A_H (REG_AFEC_BASE + 0xF5)

12