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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef XC_ANALOG_REG_H 96 #define XC_ANALOG_REG_H 97 98 /******************************************************************************/ 99 /* Macro */ 100 /******************************************************************************/ 101 102 #ifndef UNUSED 103 #define UNUSED(x) ((x)=(x)) 104 #endif 105 106 /////////////////////////////////////////////////////// 107 // Scaler Bank 108 /////////////////////////////////////////////////////// 109 110 #define BK_SELECT_00 REG_SCALER_BASE 111 112 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 113 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 114 115 /* LPLL */ 116 #define L_BK_LPLL(x) BK_REG_L(REG_LPLL_BASE, x) 117 #define H_BK_LPLL(x) BK_REG_H(REG_LPLL_BASE, x) 118 119 /* Chip Top */ 120 #define L_BK_CHIPTOP(x) BK_REG_L(REG_CLKGEN0_BASE, x) 121 #define H_BK_CHIPTOP(x) BK_REG_H(REG_CLKGEN0_BASE, x) 122 123 124 /* VD:AFEC */ 125 #define L_BK_AFEC(x) BK_REG_L(REG_AFEC_BASE, x) 126 #define H_BK_AFEC(x) BK_REG_H(REG_AFEC_BASE, x) 127 128 //------------------------------------------------------------------------------ 129 // Input source select 130 131 // BK_IP1F2_02 [2:0] 132 #define IP_INSSEL_ANALOG1 0x0000 133 #define IP_INSSEL_ANALOG2 0x0001 134 #define IP_INSSEL_ANALOG3 0x0002 135 #define IP_INSSEL_DVI 0x0003 136 #define IP_INSSEL_VIDEO 0x0004 137 #define IP_INSSEL_HDTV 0x0005 138 #define IP_INSSEL_HDMI 0x0007 139 140 #define IP_INSSEL_MASK BITMASK(2:0) 141 #define IP_VDOSEL_MASK BITMASK(1:0) 142 143 typedef enum 144 { 145 IP_CCIR656_A, 146 IP_MST_VD_A, 147 IP_CCIR601, 148 IP_MST_VD_B, // Don't use; RD's suggestion. 149 IP_CCIR656_B=0x20 150 } VDOSEL; 151 152 typedef enum 153 { 154 VE_IPMUX_ADC_A = 0, ///< ADC A 155 VE_IPMUX_HDMI_DVI = 1, ///< DVI 156 VE_IPMUX_VD = 2, ///< VD 157 VE_IPMUX_MVOP = 3, ///< MPEG/DC0 158 VE_IPMUX_SC_IP1 = 4, ///< Scaler IP1 output 159 VE_IPMUX_EXT_VD = 5, ///< External VD 160 VE_IPMUX_ADC_B = 6, ///< ADC B 161 } VE_IPMUX_TYPE; 162 163 typedef enum 164 { 165 AUTO_DETECT =0x00, 166 HV_SEPARATED =0x01, 167 COMPOSITE_SYNC =0x02, 168 SYNC_ON_GREEN =0x03 169 }STYPE; 170 171 typedef enum 172 { 173 CSYNC = 0, 174 SOG = 1 175 }COMP; 176 177 //------------------------------------------------------------------------------ 178 // ADC 179 180 #define ADC_AMUXA_MASK BITMASK(1:0) 181 #define ADC_YMUX_MASK BITMASK(3:0) 182 #define ADC_CMUX_MASK BITMASK(7:4) 183 184 185 //------------------------------------------------------------------------------ 186 // MUX 187 188 typedef enum 189 { 190 ADC_RGB1, 191 ADC_RGB2, 192 ADC_RGB3, 193 }AMUX_SEL; 194 195 typedef enum // For PC/YPbPr input mux 196 { 197 ANALOG_RGB0 = ADC_RGB1, 198 ANALOG_RGB1 = ADC_RGB2, 199 ANALOG_RGB2 = ADC_RGB3, 200 ANALOG_RGB_DUMMY, 201 }ANALOG_RGB; 202 203 typedef enum 204 { 205 MSVD_YMUX_CVBS0, 206 MSVD_YMUX_CVBS1, 207 MSVD_YMUX_CVBS2, 208 MSVD_YMUX_CVBS3, 209 210 MSVD_YMUX_Y0, 211 MSVD_YMUX_Y1, 212 MSVD_YMUX_C0, 213 MSVD_YMUX_C1, 214 215 MSVD_YMUX_SOG0 = 8, 216 MSVD_YMUX_SOG1, 217 MSVD_YMUX_SOG2, 218 219 MSVD_YMUX_G0 = 11, 220 MSVD_YMUX_G1 = 12, 221 MSVD_YMUX_G2 = 13, 222 MSVD_YMUX_CVBS4 = MSVD_YMUX_Y0, 223 MSVD_YMUX_CVBS5 = MSVD_YMUX_Y1, 224 MSVD_YMUX_CVBS6 = MSVD_YMUX_C0, 225 MSVD_YMUX_CVBS7 = MSVD_YMUX_C1, 226 MSVD_YMUX_NONE = 0xF, 227 228 MSVD_YMUX_DUMMY, 229 }MS_VD_YMUX; 230 231 typedef enum 232 { 233 MSVD_CMUX_CVBS0, 234 MSVD_CMUX_CVBS1, 235 MSVD_CMUX_CVBS2, 236 MSVD_CMUX_CVBS3, 237 238 MSVD_CMUX_Y0 = 4, 239 MSVD_CMUX_Y1, 240 MSVD_CMUX_C0, 241 MSVD_CMUX_C1, 242 243 MSVD_CMUX_SOG0 = 8, 244 MSVD_CMUX_SOG1, 245 MSVD_CMUX_SOG2, 246 247 MSVD_CMUX_R0 = 11, 248 MSVD_CMUX_R1 = 12, 249 MSVD_CMUX_R2 = 13, 250 MSVD_CMUX_CVBS4 = MSVD_CMUX_Y0, 251 MSVD_CMUX_CVBS5 = MSVD_CMUX_C0, 252 MSVD_CMUX_CVBS6 = MSVD_CMUX_Y1, 253 MSVD_CMUX_CVBS7 = MSVD_CMUX_C1, 254 MSVD_CMUX_NONE = 0xF, 255 256 MSVD_CMUX_DUMMY, 257 }MS_VD_CMUX; 258 259 #endif // ANALOG_REG_H 260